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x86: tgl: remove binary FSP_S upd parameters 

The parameters are configured in fsp_set_silicon_cfg
pull/443/head
Marco Oliverio 2023-11-23 10:30:23 +00:00
parent ffb8653f57
commit 62c938f99d
7 changed files with 413 additions and 19 deletions
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1
arch.mk
View File

@ -707,7 +707,6 @@ ifeq ("${FSP}", "1")
CFLAGS += -fno-stack-protector -m32 -fno-PIC -fno-pie -mno-mmx -mno-sse -DDEBUG_UART
ifeq ($(FSP_TGL), 1)
OBJS+=src/x86/tgl_fsp.o
OBJS+=src/fsp_tgl_s_upd.o
OBJS+=src/ucode0.o
CFLAGS += -DUCODE0_ADDRESS=$(UCODE0_BASE)
endif

1
config/examples/kontron_vx3060_s2.config
View File

@ -23,7 +23,6 @@ WOLFBOOT_DATA_ADDRESS=0x1000000
FSP_S_BASE=0xffea0000
FSP_S_UPD_DATA_BASE=0xffd00000
FSP_T_BASE=0xfff59000
FSP_M_BASE=0xfff60000

6
hal/x86_fsp_tgl_stage1.ld.in
View File

@ -1,6 +1,5 @@
FLASH_SIZE = @BOOTLOADER_PARTITION_SIZE@;
FLASH_START = 0x100000000 - @BOOTLOADER_PARTITION_SIZE@;
FSP_S_UPD_DATA_BASE = @FSP_S_UPD_DATA_BASE@;
UCODE0_BASE = @UCODE0_BASE@;
FIT_TABLE = 0xffe00000;
FSP_S_ORIGIN = @FSP_S_BASE@;
@ -42,11 +41,6 @@ SECTIONS
_end_policy = .;
} > FLASH
.fsps_upd FSP_S_UPD_DATA_BASE :
{
KEEP(./fsp_tgl_s_upd.o(.fsps_upd))
} > FLASH
.ucode_update0 UCODE0_BASE :
{
*(.ucode0)

1
options.mk
View File

@ -733,7 +733,6 @@ ifeq ($(FSP), 1)
PCI_USE_ECAM \
PCH_PCR_BASE \
PCI_ECAM_BASE \
FSP_S_UPD_DATA_BASE \
WOLFBOOT_LOAD_BASE \
FSP_S_LOAD_BASE

3
src/boot_x86_fsp.c
View File

@ -374,7 +374,6 @@ static int fsp_silicon_init(struct fsp_info_header *fsp_info, uint8_t *fsp_s_bas
memcpy(silicon_init_parameter, fsp_s_base + fsp_info->CfgRegionOffset,
FSP_S_PARAM_SIZE);
status = fsp_machine_update_s_parameters(silicon_init_parameter);
fsp_info = (struct fsp_info_header *)(fsp_s_base + FSP_INFO_HEADER_OFFSET);
SiliconInit = (silicon_init_cb)(fsp_s_base + fsp_info->FspSiliconInitEntryOffset);
wolfBoot_printf("call silicon..." ENDLINE);
@ -523,6 +522,8 @@ static void memory_ready_entry(void *ptr)
#endif /* WOLFBOOT_MEASURED_BOOT */
/* Call FSP_S initialization */
fsp_info =
(struct fsp_info_header *)(fsp_s_base + FSP_INFO_HEADER_OFFSET);
if (fsp_silicon_init(fsp_info, fsp_s_base) != EFI_SUCCESS)
panic();
/* Get CPUID */

413
src/x86/tgl_fsp.c
View File

@ -472,6 +472,414 @@ static int disable_watchdog_tco()
return 0;
}
static void fsp_set_silicon_cfg(FSPS_UPD *fsps)
{
FSP_S_CONFIG *upd = &fsps->FspsConfig;
upd->GraphicsConfigPtr = 2024131364;
upd->SataPortsEnable[0] = 1;
upd->SataPortsEnable[1] = 1;
upd->SataPortsEnable[2] = 0;
upd->SataPortsEnable[3] = 0;
upd->SataPortsEnable[4] = 0;
upd->SataPortsEnable[5] = 0;
upd->SataPortsEnable[6] = 0;
upd->SataPortsEnable[7] = 0;
upd->PortUsb30Enable[0] = 1;
upd->PortUsb30Enable[1] = 1;
upd->PortUsb30Enable[2] = 1;
upd->PortUsb30Enable[3] = 1;
upd->PortUsb30Enable[4] = 0;
upd->PortUsb30Enable[5] = 0;
upd->PortUsb30Enable[6] = 0;
upd->PortUsb30Enable[7] = 0;
upd->PortUsb30Enable[8] = 0;
upd->PortUsb30Enable[9] = 0;
upd->XdciEnable = 1;
upd->DevIntConfigPtr = 2023910720;
upd->NumOfDevIntConfig = 52;
upd->SerialIoSpiMode[0] = 1;
upd->SerialIoSpiMode[1] = 0;
upd->SerialIoSpiMode[2] = 0;
upd->SerialIoSpiMode[3] = 0;
upd->SerialIoSpiMode[4] = 0;
upd->SerialIoSpiMode[5] = 0;
upd->SerialIoSpiMode[6] = 0;
upd->SerialIoUartMode[0] = 4;
upd->SerialIoUartMode[1] = 1;
upd->SerialIoUartMode[2] = 1;
upd->SerialIoUartMode[3] = 0;
upd->SerialIoUartMode[4] = 0;
upd->SerialIoUartMode[5] = 0;
upd->SerialIoUartMode[6] = 0;
upd->SerialIoUartDmaEnable[0] = 1;
upd->SerialIoUartDmaEnable[1] = 1;
upd->SerialIoUartDmaEnable[2] = 1;
upd->SerialIoUartDmaEnable[3] = 1;
upd->SerialIoUartDmaEnable[4] = 1;
upd->SerialIoUartDmaEnable[5] = 1;
upd->SerialIoUartDmaEnable[6] = 1;
upd->SerialIoUartAutoFlow[0] = 0;
upd->SerialIoUartAutoFlow[1] = 0;
upd->SerialIoUartAutoFlow[2] = 0;
upd->SerialIoUartAutoFlow[3] = 1;
upd->SerialIoUartAutoFlow[4] = 1;
upd->SerialIoUartAutoFlow[5] = 0;
upd->SerialIoUartAutoFlow[6] = 0;
upd->SerialIoUartRtsPinMuxPolicy[0] = 420160010;
upd->SerialIoUartRtsPinMuxPolicy[1] = 0;
upd->SerialIoUartRtsPinMuxPolicy[2] = 0;
upd->SerialIoUartRtsPinMuxPolicy[3] = 0;
upd->SerialIoUartRtsPinMuxPolicy[4] = 0;
upd->SerialIoUartRtsPinMuxPolicy[5] = 0;
upd->SerialIoUartRtsPinMuxPolicy[6] = 0;
upd->SerialIoUartCtsPinMuxPolicy[0] = 420164107;
upd->SerialIoUartCtsPinMuxPolicy[1] = 0;
upd->SerialIoUartCtsPinMuxPolicy[2] = 0;
upd->SerialIoUartCtsPinMuxPolicy[3] = 0;
upd->SerialIoUartCtsPinMuxPolicy[4] = 0;
upd->SerialIoUartCtsPinMuxPolicy[5] = 0;
upd->SerialIoUartCtsPinMuxPolicy[6] = 0;
upd->SerialIoUartRxPinMuxPolicy[0] = 420151816;
upd->SerialIoUartRxPinMuxPolicy[1] = 0;
upd->SerialIoUartRxPinMuxPolicy[2] = 0;
upd->SerialIoUartRxPinMuxPolicy[3] = 0;
upd->SerialIoUartRxPinMuxPolicy[4] = 0;
upd->SerialIoUartRxPinMuxPolicy[5] = 0;
upd->SerialIoUartRxPinMuxPolicy[6] = 0;
upd->SerialIoUartTxPinMuxPolicy[0] = 420155913;
upd->SerialIoUartTxPinMuxPolicy[1] = 0;
upd->SerialIoUartTxPinMuxPolicy[2] = 0;
upd->SerialIoUartTxPinMuxPolicy[3] = 0;
upd->SerialIoUartTxPinMuxPolicy[4] = 0;
upd->SerialIoUartTxPinMuxPolicy[5] = 0;
upd->SerialIoUartTxPinMuxPolicy[6] = 0;
upd->SerialIoDebugUartNumber = 0;
upd->SerialIoI2cMode[0] = 0;
upd->SerialIoI2cMode[1] = 0;
upd->SerialIoI2cMode[2] = 0;
upd->SerialIoI2cMode[3] = 0;
upd->SerialIoI2cMode[4] = 0;
upd->SerialIoI2cMode[5] = 0;
upd->SerialIoI2cMode[6] = 0;
upd->SerialIoI2cMode[7] = 0;
upd->Usb2PhyPetxiset[0] = 6;
upd->Usb2PhyPetxiset[1] = 6;
upd->Usb2PhyPetxiset[2] = 6;
upd->Usb2PhyPetxiset[3] = 6;
upd->Usb2PhyPetxiset[4] = 6;
upd->Usb2PhyPetxiset[5] = 6;
upd->Usb2PhyPetxiset[6] = 6;
upd->Usb2PhyPetxiset[7] = 6;
upd->Usb2PhyPetxiset[8] = 6;
upd->Usb2PhyPetxiset[9] = 6;
upd->Usb2PhyPetxiset[10] = 6;
upd->Usb2PhyPetxiset[11] = 6;
upd->Usb2PhyPetxiset[12] = 6;
upd->Usb2PhyPetxiset[13] = 6;
upd->Usb2PhyPetxiset[14] = 0;
upd->Usb2PhyPetxiset[15] = 0;
upd->Usb2PhyTxiset[0] = 0;
upd->Usb2PhyTxiset[1] = 0;
upd->Usb2PhyTxiset[2] = 0;
upd->Usb2PhyTxiset[3] = 0;
upd->Usb2PhyTxiset[4] = 0;
upd->Usb2PhyTxiset[5] = 0;
upd->Usb2PhyTxiset[6] = 0;
upd->Usb2PhyTxiset[7] = 0;
upd->Usb2PhyTxiset[8] = 0;
upd->Usb2PhyTxiset[9] = 0;
upd->Usb2PhyTxiset[10] = 0;
upd->Usb2PhyTxiset[11] = 0;
upd->Usb2PhyTxiset[12] = 0;
upd->Usb2PhyTxiset[13] = 0;
upd->Usb2PhyTxiset[14] = 0;
upd->Usb2PhyTxiset[15] = 0;
upd->Usb2PhyPredeemp[0] = 3;
upd->Usb2PhyPredeemp[1] = 3;
upd->Usb2PhyPredeemp[2] = 3;
upd->Usb2PhyPredeemp[3] = 3;
upd->Usb2PhyPredeemp[4] = 3;
upd->Usb2PhyPredeemp[5] = 3;
upd->Usb2PhyPredeemp[6] = 3;
upd->Usb2PhyPredeemp[7] = 3;
upd->Usb2PhyPredeemp[8] = 3;
upd->Usb2PhyPredeemp[9] = 3;
upd->Usb2PhyPredeemp[10] = 3;
upd->Usb2PhyPredeemp[11] = 3;
upd->Usb2PhyPredeemp[12] = 3;
upd->Usb2PhyPredeemp[13] = 3;
upd->Usb2PhyPredeemp[14] = 0;
upd->Usb2PhyPredeemp[15] = 0;
upd->Usb2PhyPehalfbit[0] = 0;
upd->Usb2PhyPehalfbit[1] = 0;
upd->Usb2PhyPehalfbit[2] = 0;
upd->Usb2PhyPehalfbit[3] = 0;
upd->Usb2PhyPehalfbit[4] = 0;
upd->Usb2PhyPehalfbit[5] = 0;
upd->Usb2PhyPehalfbit[6] = 0;
upd->Usb2PhyPehalfbit[7] = 0;
upd->Usb2PhyPehalfbit[8] = 0;
upd->Usb2PhyPehalfbit[9] = 0;
upd->Usb2PhyPehalfbit[10] = 0;
upd->Usb2PhyPehalfbit[11] = 0;
upd->Usb2PhyPehalfbit[12] = 0;
upd->Usb2PhyPehalfbit[13] = 0;
upd->Usb2PhyPehalfbit[14] = 0;
upd->Usb2PhyPehalfbit[15] = 0;
upd->PchLanEnable = 0;
upd->PchTsnEnable[0] = 0;
upd->PchTsnEnable[1] = 0;
upd->CnviMode = 0;
upd->CnviBtCore = 0;
upd->SataLedEnable = 1;
upd->IomTypeCPortPadCfg[0] = 0;
upd->IomTypeCPortPadCfg[1] = 0;
upd->IomTypeCPortPadCfg[2] = 0;
upd->IomTypeCPortPadCfg[3] = 0;
upd->IomTypeCPortPadCfg[4] = 0;
upd->IomTypeCPortPadCfg[5] = 0;
upd->IomTypeCPortPadCfg[6] = 0;
upd->IomTypeCPortPadCfg[7] = 0;
upd->UsbTcPortEn = 15;
upd->PchWriteProtectionEnable[0] = 1;
upd->PchWriteProtectionEnable[1] = 1;
upd->PchWriteProtectionEnable[2] = 0;
upd->PchWriteProtectionEnable[3] = 0;
upd->PchWriteProtectionEnable[4] = 0;
upd->PchProtectedRangeLimit[0] = 62992;
upd->PchProtectedRangeLimit[1] = 0;
upd->PchProtectedRangeLimit[2] = 0;
upd->PchProtectedRangeLimit[3] = 0;
upd->PchProtectedRangeLimit[4] = 0;
upd->PchProtectedRangeBase[0] = 0;
upd->PchProtectedRangeBase[1] = 63057;
upd->PchProtectedRangeBase[2] = 0;
upd->PchProtectedRangeBase[3] = 0;
upd->PchProtectedRangeBase[4] = 0;
upd->PcieRpClkReqDetect[0] = 1;
upd->PcieRpClkReqDetect[1] = 1;
upd->PcieRpClkReqDetect[2] = 1;
upd->PcieRpClkReqDetect[3] = 1;
upd->PcieRpClkReqDetect[4] = 1;
upd->PcieRpClkReqDetect[5] = 1;
upd->PcieRpClkReqDetect[6] = 1;
upd->PcieRpClkReqDetect[7] = 1;
upd->PcieRpClkReqDetect[8] = 1;
upd->PcieRpClkReqDetect[9] = 1;
upd->PcieRpClkReqDetect[10] = 1;
upd->PcieRpClkReqDetect[11] = 1;
upd->PcieRpClkReqDetect[12] = 0;
upd->PcieRpClkReqDetect[13] = 0;
upd->PcieRpClkReqDetect[14] = 0;
upd->PcieRpClkReqDetect[15] = 0;
upd->PcieRpClkReqDetect[16] = 0;
upd->PcieRpClkReqDetect[17] = 0;
upd->PcieRpClkReqDetect[18] = 0;
upd->PcieRpClkReqDetect[19] = 0;
upd->PcieRpClkReqDetect[20] = 0;
upd->PcieRpClkReqDetect[21] = 0;
upd->PcieRpClkReqDetect[22] = 0;
upd->PcieRpClkReqDetect[23] = 0;
upd->PcieRpAdvancedErrorReporting[0] = 1;
upd->PcieRpAdvancedErrorReporting[1] = 1;
upd->PcieRpAdvancedErrorReporting[2] = 1;
upd->PcieRpAdvancedErrorReporting[3] = 1;
upd->PcieRpAdvancedErrorReporting[4] = 1;
upd->PcieRpAdvancedErrorReporting[5] = 1;
upd->PcieRpAdvancedErrorReporting[6] = 1;
upd->PcieRpAdvancedErrorReporting[7] = 1;
upd->PcieRpAdvancedErrorReporting[8] = 1;
upd->PcieRpAdvancedErrorReporting[9] = 1;
upd->PcieRpAdvancedErrorReporting[10] = 1;
upd->PcieRpAdvancedErrorReporting[11] = 1;
upd->PcieRpAdvancedErrorReporting[12] = 0;
upd->PcieRpAdvancedErrorReporting[13] = 0;
upd->PcieRpAdvancedErrorReporting[14] = 0;
upd->PcieRpAdvancedErrorReporting[15] = 0;
upd->PcieRpAdvancedErrorReporting[16] = 0;
upd->PcieRpAdvancedErrorReporting[17] = 0;
upd->PcieRpAdvancedErrorReporting[18] = 0;
upd->PcieRpAdvancedErrorReporting[19] = 0;
upd->PcieRpAdvancedErrorReporting[20] = 0;
upd->PcieRpAdvancedErrorReporting[21] = 0;
upd->PcieRpAdvancedErrorReporting[22] = 0;
upd->PcieRpAdvancedErrorReporting[23] = 0;
upd->PcieRpMaxPayload[0] = 1;
upd->PcieRpMaxPayload[1] = 1;
upd->PcieRpMaxPayload[2] = 1;
upd->PcieRpMaxPayload[3] = 1;
upd->PcieRpMaxPayload[4] = 1;
upd->PcieRpMaxPayload[5] = 1;
upd->PcieRpMaxPayload[6] = 1;
upd->PcieRpMaxPayload[7] = 1;
upd->PcieRpMaxPayload[8] = 1;
upd->PcieRpMaxPayload[9] = 1;
upd->PcieRpMaxPayload[10] = 1;
upd->PcieRpMaxPayload[11] = 1;
upd->PcieRpMaxPayload[12] = 0;
upd->PcieRpMaxPayload[13] = 0;
upd->PcieRpMaxPayload[14] = 0;
upd->PcieRpMaxPayload[15] = 0;
upd->PcieRpMaxPayload[16] = 0;
upd->PcieRpMaxPayload[17] = 0;
upd->PcieRpMaxPayload[18] = 0;
upd->PcieRpMaxPayload[19] = 0;
upd->PcieRpMaxPayload[20] = 0;
upd->PcieRpMaxPayload[21] = 0;
upd->PcieRpMaxPayload[22] = 0;
upd->PcieRpMaxPayload[23] = 0;
upd->PcieRpL1Substates[0] = 1;
upd->PcieRpL1Substates[1] = 1;
upd->PcieRpL1Substates[2] = 1;
upd->PcieRpL1Substates[3] = 1;
upd->PcieRpL1Substates[4] = 1;
upd->PcieRpL1Substates[5] = 1;
upd->PcieRpL1Substates[6] = 1;
upd->PcieRpL1Substates[7] = 1;
upd->PcieRpL1Substates[8] = 1;
upd->PcieRpL1Substates[9] = 1;
upd->PcieRpL1Substates[10] = 1;
upd->PcieRpL1Substates[11] = 1;
upd->PcieRpL1Substates[12] = 3;
upd->PcieRpL1Substates[13] = 3;
upd->PcieRpL1Substates[14] = 3;
upd->PcieRpL1Substates[15] = 3;
upd->PcieRpL1Substates[16] = 3;
upd->PcieRpL1Substates[17] = 3;
upd->PcieRpL1Substates[18] = 3;
upd->PcieRpL1Substates[19] = 3;
upd->PcieRpL1Substates[20] = 3;
upd->PcieRpL1Substates[21] = 3;
upd->PcieRpL1Substates[22] = 3;
upd->PcieRpL1Substates[23] = 3;
upd->PcieRpLtrEnable[0] = 1;
upd->PcieRpLtrEnable[1] = 1;
upd->PcieRpLtrEnable[2] = 1;
upd->PcieRpLtrEnable[3] = 1;
upd->PcieRpLtrEnable[4] = 1;
upd->PcieRpLtrEnable[5] = 1;
upd->PcieRpLtrEnable[6] = 1;
upd->PcieRpLtrEnable[7] = 1;
upd->PcieRpLtrEnable[8] = 1;
upd->PcieRpLtrEnable[9] = 1;
upd->PcieRpLtrEnable[10] = 1;
upd->PcieRpLtrEnable[11] = 1;
upd->PcieRpLtrEnable[12] = 0;
upd->PcieRpLtrEnable[13] = 0;
upd->PcieRpLtrEnable[14] = 0;
upd->PcieRpLtrEnable[15] = 0;
upd->PcieRpLtrEnable[16] = 0;
upd->PcieRpLtrEnable[17] = 0;
upd->PcieRpLtrEnable[18] = 0;
upd->PcieRpLtrEnable[19] = 0;
upd->PcieRpLtrEnable[20] = 0;
upd->PcieRpLtrEnable[21] = 0;
upd->PcieRpLtrEnable[22] = 0;
upd->PcieRpLtrEnable[23] = 0;
upd->SataPwrOptEnable = 1;
upd->IehMode = 1;
upd->Usb2OverCurrentPin[0] = 255;
upd->Usb2OverCurrentPin[1] = 3;
upd->Usb2OverCurrentPin[2] = 255;
upd->Usb2OverCurrentPin[3] = 255;
upd->Usb2OverCurrentPin[4] = 255;
upd->Usb2OverCurrentPin[5] = 255;
upd->Usb2OverCurrentPin[6] = 3;
upd->Usb2OverCurrentPin[7] = 255;
upd->Usb2OverCurrentPin[8] = 1;
upd->Usb2OverCurrentPin[9] = 255;
upd->Usb2OverCurrentPin[10] = 5;
upd->Usb2OverCurrentPin[11] = 5;
upd->Usb2OverCurrentPin[12] = 6;
upd->Usb2OverCurrentPin[13] = 6;
upd->Usb2OverCurrentPin[14] = 7;
upd->Usb2OverCurrentPin[15] = 7;
upd->Usb3OverCurrentPin[0] = 2;
upd->Usb3OverCurrentPin[1] = 255;
upd->Usb3OverCurrentPin[2] = 255;
upd->Usb3OverCurrentPin[3] = 255;
upd->Usb3OverCurrentPin[4] = 2;
upd->Usb3OverCurrentPin[5] = 2;
upd->Usb3OverCurrentPin[6] = 3;
upd->Usb3OverCurrentPin[7] = 3;
upd->Usb3OverCurrentPin[8] = 4;
upd->Usb3OverCurrentPin[9] = 4;
upd->SgxEpoch0 = 6142344250440060711U;
upd->SgxEpoch1 = 15521488688214965697U;
upd->CpuPcieSetSecuredRegisterLock = 1;
upd->CpuPcieRpPmSci[0] = 1;
upd->CpuPcieRpPmSci[1] = 0;
upd->CpuPcieRpPmSci[2] = 0;
upd->CpuPcieRpPmSci[3] = 0;
upd->CpuPcieRpMaxPayload[0] = 1;
upd->CpuPcieRpMaxPayload[1] = 0;
upd->CpuPcieRpMaxPayload[2] = 0;
upd->CpuPcieRpMaxPayload[3] = 0;
upd->CpuPcieRpLtrEnable[0] = 1;
upd->CpuPcieRpLtrEnable[1] = 0;
upd->CpuPcieRpLtrEnable[2] = 0;
upd->CpuPcieRpLtrEnable[3] = 0;
upd->Eist = 0;
upd->EnableItbm = 0;
upd->PcieRpLtrMaxSnoopLatency[0] = 4099;
upd->PcieRpLtrMaxSnoopLatency[1] = 4099;
upd->PcieRpLtrMaxSnoopLatency[2] = 4099;
upd->PcieRpLtrMaxSnoopLatency[3] = 4099;
upd->PcieRpLtrMaxSnoopLatency[4] = 4099;
upd->PcieRpLtrMaxSnoopLatency[5] = 4099;
upd->PcieRpLtrMaxSnoopLatency[6] = 4099;
upd->PcieRpLtrMaxSnoopLatency[7] = 4099;
upd->PcieRpLtrMaxSnoopLatency[8] = 4099;
upd->PcieRpLtrMaxSnoopLatency[9] = 4099;
upd->PcieRpLtrMaxSnoopLatency[10] = 4099;
upd->PcieRpLtrMaxSnoopLatency[11] = 4099;
upd->PcieRpLtrMaxSnoopLatency[12] = 0;
upd->PcieRpLtrMaxSnoopLatency[13] = 0;
upd->PcieRpLtrMaxSnoopLatency[14] = 0;
upd->PcieRpLtrMaxSnoopLatency[15] = 0;
upd->PcieRpLtrMaxSnoopLatency[16] = 0;
upd->PcieRpLtrMaxSnoopLatency[17] = 0;
upd->PcieRpLtrMaxSnoopLatency[18] = 0;
upd->PcieRpLtrMaxSnoopLatency[19] = 0;
upd->PcieRpLtrMaxSnoopLatency[20] = 0;
upd->PcieRpLtrMaxSnoopLatency[21] = 0;
upd->PcieRpLtrMaxSnoopLatency[22] = 0;
upd->PcieRpLtrMaxSnoopLatency[23] = 0;
upd->PcieRpLtrMaxNoSnoopLatency[0] = 4099;
upd->PcieRpLtrMaxNoSnoopLatency[1] = 4099;
upd->PcieRpLtrMaxNoSnoopLatency[2] = 4099;
upd->PcieRpLtrMaxNoSnoopLatency[3] = 4099;
upd->PcieRpLtrMaxNoSnoopLatency[4] = 4099;
upd->PcieRpLtrMaxNoSnoopLatency[5] = 4099;
upd->PcieRpLtrMaxNoSnoopLatency[6] = 4099;
upd->PcieRpLtrMaxNoSnoopLatency[7] = 4099;
upd->PcieRpLtrMaxNoSnoopLatency[8] = 4099;
upd->PcieRpLtrMaxNoSnoopLatency[9] = 4099;
upd->PcieRpLtrMaxNoSnoopLatency[10] = 4099;
upd->PcieRpLtrMaxNoSnoopLatency[11] = 4099;
upd->PcieRpLtrMaxNoSnoopLatency[12] = 0;
upd->PcieRpLtrMaxNoSnoopLatency[13] = 0;
upd->PcieRpLtrMaxNoSnoopLatency[14] = 0;
upd->PcieRpLtrMaxNoSnoopLatency[15] = 0;
upd->PcieRpLtrMaxNoSnoopLatency[16] = 0;
upd->PcieRpLtrMaxNoSnoopLatency[17] = 0;
upd->PcieRpLtrMaxNoSnoopLatency[18] = 0;
upd->PcieRpLtrMaxNoSnoopLatency[19] = 0;
upd->PcieRpLtrMaxNoSnoopLatency[20] = 0;
upd->PcieRpLtrMaxNoSnoopLatency[21] = 0;
upd->PcieRpLtrMaxNoSnoopLatency[22] = 0;
upd->PcieRpLtrMaxNoSnoopLatency[23] = 0;
upd->CpuPcieRpLtrMaxSnoopLatency[0] = 4099;
upd->CpuPcieRpLtrMaxSnoopLatency[1] = 4111;
upd->CpuPcieRpLtrMaxSnoopLatency[2] = 4111;
upd->CpuPcieRpLtrMaxSnoopLatency[3] = 4111;
upd->CpuPcieRpLtrMaxNoSnoopLatency[0] = 4099;
upd->CpuPcieRpLtrMaxNoSnoopLatency[1] = 4111;
upd->CpuPcieRpLtrMaxNoSnoopLatency[2] = 4111;
upd->CpuPcieRpLtrMaxNoSnoopLatency[3] = 4111;
}
/**
* @brief Update S parameters in FSPS_UPD structure.
*
@ -486,11 +894,10 @@ int fsp_machine_update_s_parameters(uint8_t *default_s_params)
FSP_S_CONFIG *upd;
unsigned int i;
(void)default_s_params;
memcpy(default_s_params, (uint8_t*)FSP_S_UPD_DATA_BASE, 0xee0);
fsp_set_silicon_cfg((FSPS_UPD*)default_s_params);
upd = &((FSPS_UPD*)default_s_params)->FspsConfig;
upd->MicrocodeRegionBase = 0x0;
upd->MicrocodeRegionSize = 0x0;
upd->DevIntConfigPtr = (uint32_t)mPchHDevIntConfig;

7
stage1/x86_fsp.mk
View File

@ -11,8 +11,7 @@ $(LSCRIPT_IN): $(WOLFBOOT_ROOT)/hal/$(LSCRIPT_IN).in FORCE
sed -e "s/@FSP_S_BASE@/$(FSP_S_BASE)/g" | \
sed -e "s/@WOLFBOOT_LOAD_BASE@/$(WOLFBOOT_LOAD_BASE)/g" | \
sed -e "s/@UCODE0_BASE@/$(UCODE0_BASE)/g" | \
sed -e "s/@UCODE1_BASE@/$(UCODE1_BASE)/g" | \
sed -e "s/@FSP_S_UPD_DATA_BASE@/$(FSP_S_UPD_DATA_BASE)/g" \
sed -e "s/@UCODE1_BASE@/$(UCODE1_BASE)/g" \
> $@
./boot_x86_fsp_start.o: boot_x86_fsp_start.S
@ -45,10 +44,6 @@ sig_wolfboot_raw.o: wolfboot_raw.bin $(SIGN_KEY)
@dd if=wolfboot_raw_v1_signed.bin of=wolfboot_raw_signature.bin bs=$(IMAGE_HEADER_SIZE) count=1
$(OBJCOPY) -I binary -O elf32-i386 -B i386 --rename-section .data=.sig_wolfboot_raw wolfboot_raw_signature.bin sig_wolfboot_raw.o
fsp_tgl_s_upd.o: ../$(FSP_S_UPD_DATA_BIN)
$(OBJCOPY) -I binary -O elf32-i386 -B i386 --rename-section .data=.fsps_upd $^ $@
ucode0.o: ../$(UCODE0_BIN)
$(OBJCOPY) -I binary -O elf32-i386 -B i386 --rename-section .data=.ucode0 $^ $@