mirror of https://github.com/wolfSSL/wolfBoot.git
Add uart driver for stm32u5
Mattia Moffa
Daniele Lacamera
parent
4efc00a806
commit
6b8702dd63
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@ -24,6 +24,7 @@
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#include <string.h>
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#include "hal/stm32u5.h"
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#include "hal.h"
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#include "uart_drv.h"
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static void RAMFUNCTION flash_set_waitstates(unsigned int waitstates)
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@ -33,7 +34,7 @@ static void RAMFUNCTION flash_set_waitstates(unsigned int waitstates)
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FLASH_ACR = (reg & ~FLASH_ACR_LATENCY_MASK) | waitstates;
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}
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static RAMFUNCTION void flash_wait_complete(uint8_t bank)
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void RAMFUNCTION hal_flash_wait_complete(uint8_t bank)
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{
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while ((FLASH_NS_SR & (FLASH_SR_BSY | FLASH_SR_WDW)) != 0)
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;
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@ -44,7 +45,7 @@ static RAMFUNCTION void flash_wait_complete(uint8_t bank)
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}
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static void RAMFUNCTION flash_clear_errors(uint8_t bank)
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void RAMFUNCTION hal_flash_clear_errors(uint8_t bank)
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{
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FLASH_NS_SR |= (FLASH_SR_OPERR | FLASH_SR_PROGERR | FLASH_SR_WRPERR |
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@ -68,7 +69,7 @@ int RAMFUNCTION hal_flash_write(uint32_t address, const uint8_t *data, int len)
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uint32_t qword[4];
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volatile uint32_t *sr, *cr;
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flash_clear_errors(0);
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hal_flash_clear_errors(0);
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src = (uint32_t*)data;
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dst = (uint32_t*)address;
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@ -105,7 +106,7 @@ int RAMFUNCTION hal_flash_write(uint32_t address, const uint8_t *data, int len)
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ISB();
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dst[(i >> 2) + 3] = qword[3];
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ISB();
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flash_wait_complete(0);
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hal_flash_wait_complete(0);
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if ((*sr & FLASH_SR_EOP) != 0)
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*sr |= FLASH_SR_EOP;
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*cr &= ~FLASH_CR_PG;
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@ -117,7 +118,7 @@ int RAMFUNCTION hal_flash_write(uint32_t address, const uint8_t *data, int len)
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void RAMFUNCTION hal_flash_unlock(void)
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{
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flash_wait_complete(0);
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hal_flash_wait_complete(0);
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#if (TZ_SECURE())
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if ((FLASH_CR & FLASH_CR_LOCK) != 0) {
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FLASH_KEYR = FLASH_KEY1;
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@ -140,7 +141,7 @@ void RAMFUNCTION hal_flash_unlock(void)
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void RAMFUNCTION hal_flash_lock(void)
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{
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flash_wait_complete(0);
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hal_flash_wait_complete(0);
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#if (TZ_SECURE())
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if ((FLASH_CR & FLASH_CR_LOCK) == 0)
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FLASH_CR |= FLASH_CR_LOCK;
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@ -151,7 +152,7 @@ void RAMFUNCTION hal_flash_lock(void)
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void RAMFUNCTION hal_flash_opt_unlock(void)
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{
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flash_wait_complete(0);
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hal_flash_wait_complete(0);
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if ((FLASH_NS_CR & FLASH_CR_OPTLOCK) != 0) {
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FLASH_NS_OPTKEYR = FLASH_OPTKEY1;
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@ -167,7 +168,7 @@ void RAMFUNCTION hal_flash_opt_lock(void)
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{
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FLASH_NS_CR |= FLASH_CR_OPTSTRT;
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flash_wait_complete(0);
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hal_flash_wait_complete(0);
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FLASH_NS_CR |= FLASH_CR_OBL_LAUNCH;
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if ((FLASH_NS_CR & FLASH_CR_OPTLOCK) == 0)
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FLASH_NS_CR |= FLASH_CR_OPTLOCK;
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@ -179,7 +180,7 @@ int RAMFUNCTION hal_flash_erase(uint32_t address, int len)
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uint32_t p;
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volatile uint32_t *cr = &FLASH_NS_CR;
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flash_clear_errors(0);
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hal_flash_clear_errors(0);
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if (len == 0)
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return -1;
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@ -219,7 +220,7 @@ int RAMFUNCTION hal_flash_erase(uint32_t address, int len)
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*cr = reg;
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DMB();
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*cr |= FLASH_CR_STRT;
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flash_wait_complete(0);
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hal_flash_wait_complete(0);
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}
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/* If the erase operation is completed, disable the associated bits */
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*cr &= ~FLASH_CR_PER ;
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@ -500,6 +501,8 @@ static void led_unsecure()
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#define TZSC1_BASE 0x50032400u
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#define TZSC_SECCFGR1 (*(volatile uint32_t *)(TZSC1_BASE + 0x10u))
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#define TZSC_SECCFGR1_USART3SEC (1u << 10)
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#define TZSC_SECCFGR2 (*(volatile uint32_t *)(TZSC1_BASE + 0x14u))
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#define TZSC_SECCFGR2_USART1SEC (1u << 3)
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static void periph_unsecure(void)
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{
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@ -522,6 +525,24 @@ static void periph_unsecure(void)
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DMB();
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TZSC_SECCFGR1 = reg;
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}
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/* Enable clock for GPIO A (USART1 pins PA9/PA10) */
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RCC_AHB2ENR1_CLOCK_ER |= GPIOA_AHB2ENR1_CLOCK_ER;
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/* Enable clock for USART1 */
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RCC_APB2ENR |= UART1_APB2_CLOCK_ER_VAL;
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/* Unsecure USART1 pins (PA9 TX, PA10 RX) */
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GPIOA_SECCFGR &= ~(1u << UART1_TX_PIN);
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GPIOA_SECCFGR &= ~(1u << UART1_RX_PIN);
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/* Unsecure USART1 peripheral in GTZC TZSC */
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reg = TZSC_SECCFGR2;
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if (reg & TZSC_SECCFGR2_USART1SEC) {
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reg &= ~TZSC_SECCFGR2_USART1SEC;
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DMB();
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TZSC_SECCFGR2 = reg;
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}
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}
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#endif
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@ -554,6 +575,12 @@ void hal_init(void)
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fork_bootloader();
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#endif
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clock_pll_on(0);
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#ifdef DEBUG_UART
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uart_init(115200, 8, 'N', 1);
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uart_write("wolfBoot Init\n", 14);
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#endif
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#if TZ_SECURE()
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hal_tz_sau_init();
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hal_gtzc_init();
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@ -277,6 +277,68 @@
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#define RCC_AHB2_CLOCK_ER RCC_AHB2ENR1_CLOCK_ER
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/* UART */
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#if (TZ_SECURE())
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#define UART1 (0x50013800) /* USART1 - RM0456 - Table 4 */
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#define GPIOA_BASE (0x52020000)
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#else
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#define UART1 (0x40013800) /* USART1 - RM0456 - Table 4 */
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#define GPIOA_BASE (0x42020000)
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#endif
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#define UART_CR1(base) (*(volatile uint32_t *)((base) + 0x00))
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#define UART_CR2(base) (*(volatile uint32_t *)((base) + 0x04))
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#define UART_CR3(base) (*(volatile uint32_t *)((base) + 0x08))
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#define UART_BRR(base) (*(volatile uint32_t *)((base) + 0x0c))
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#define UART_ISR(base) (*(volatile uint32_t *)((base) + 0x1c))
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#define UART_ICR(base) (*(volatile uint32_t *)((base) + 0x20))
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#define UART_RDR(base) (*(volatile uint32_t *)((base) + 0x24))
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#define UART_TDR(base) (*(volatile uint32_t *)((base) + 0x28))
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#define UART_PRE(base) (*(volatile uint32_t *)((base) + 0x2C))
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#define UART_CR1_UART_ENABLE (1 << 0)
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#define UART_CR1_OVER8 (1 << 15)
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#define UART_CR1_SYMBOL_LEN (1 << 12)
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#define UART_CR1_PARITY_ENABLED (1 << 10)
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#define UART_CR1_PARITY_ODD (1 << 9)
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#define UART_CR1_TX_ENABLE (1 << 3)
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#define UART_CR1_RX_ENABLE (1 << 2)
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#define UART_CR2_STOPBITS (3 << 12)
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#define UART_CR2_LINEN (1 << 14)
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#define UART_CR2_CLKEN (1 << 11)
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#define UART_CR3_HDSEL (1 << 3)
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#define UART_CR3_SCEN (1 << 5)
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#define UART_CR3_IREN (1 << 1)
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#define UART_ISR_TX_EMPTY (1 << 7)
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#define UART_ISR_TX_COMPLETE (1 << 6)
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#define UART_ISR_RX_NOTEMPTY (1 << 5)
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#define UART_EPE (1 << 0) /* Parity error */
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#define UART_EFE (1 << 1) /* Framing error */
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#define UART_ENE (1 << 2) /* Noise error */
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#define UART_ORE (1 << 3) /* Overrun error */
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#define UART1_APB2_CLOCK_ER_VAL (1 << 14) /* RM0456 - RCC_APB2ENR - USART1EN */
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#define RCC_APB2ENR (*(volatile uint32_t *)(RCC_BASE + 0xA4)) /* RM0456 - Table 108 */
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#define RCC_CCIPR1 (*(volatile uint32_t *)(RCC_BASE + 0xE0)) /* RM0456 - 11.8.46 */
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#define RCC_CCIPR1_USART1SEL_SHIFT (0)
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#define RCC_CCIPR1_USART1SEL_MASK (0x3)
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#define RCC_CCIPR1_USART1SEL_HSI16 (0x2)
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#define HSI16_FREQ (16000000)
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/* USART1 pin configuration: PA9 (TX) / PA10 (RX), AF7.
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* Connected to the ST-LINK VCP on Nucleo-U575ZI-Q. */
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#define UART1_PIN_AF 7
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#define UART1_TX_PIN 9
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#define UART1_RX_PIN 10
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#define GPIOA_AHB2ENR1_CLOCK_ER (1 << 0)
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#define GPIOA_MODE (*(volatile uint32_t *)(GPIOA_BASE + 0x00))
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#define GPIOA_AFL (*(volatile uint32_t *)(GPIOA_BASE + 0x20))
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#define GPIOA_AFH (*(volatile uint32_t *)(GPIOA_BASE + 0x24))
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#define GPIOA_SECCFGR (*(volatile uint32_t *)(GPIOA_BASE + 0x30))
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/* Reset */
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#define OPTR_SWAP_BANK (1 << 20)
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@ -0,0 +1,157 @@
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/* uart_drv_stm32u5.c
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*
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* Driver for the back-end of the UART_FLASH module.
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*
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* Example implementation for stm32U5
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* using USART1 (PA9/PA10, ST-LINK VCP on B-U585I-IOT02A).
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*
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*
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* Copyright (C) 2026 wolfSSL Inc.
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*
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* This file is part of wolfBoot.
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*
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* wolfBoot is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 3 of the License, or
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* (at your option) any later version.
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*
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* wolfBoot is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
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*/
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#ifdef TARGET_stm32u5
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#include <stdint.h>
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#include "hal/stm32u5.h"
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static void uart_pins_setup(void)
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{
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uint32_t reg;
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RCC_AHB2ENR1_CLOCK_ER |= GPIOA_AHB2ENR1_CLOCK_ER;
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/* Set mode = AF */
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reg = GPIOA_MODE & ~(0x03 << (UART1_RX_PIN * 2));
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GPIOA_MODE = reg | (2 << (UART1_RX_PIN * 2));
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reg = GPIOA_MODE & ~(0x03 << (UART1_TX_PIN * 2));
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GPIOA_MODE = reg | (2 << (UART1_TX_PIN * 2));
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/* Alternate function: use hi pins (9 and 10) */
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reg = GPIOA_AFH & ~(0xf << ((UART1_TX_PIN - 8) * 4));
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GPIOA_AFH = reg | (UART1_PIN_AF << ((UART1_TX_PIN - 8) * 4));
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reg = GPIOA_AFH & ~(0xf << ((UART1_RX_PIN - 8) * 4));
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GPIOA_AFH = reg | (UART1_PIN_AF << ((UART1_RX_PIN - 8) * 4));
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}
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static void uart_clear_errors(uint32_t base)
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{
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UART_ICR(base) = UART_ISR(base) & (UART_ENE | UART_EPE | UART_ORE | UART_EFE);
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}
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int uart_tx(const uint8_t c)
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{
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volatile uint32_t reg;
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do {
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reg = UART_ISR(UART1);
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if (reg & (UART_ENE | UART_EPE | UART_ORE | UART_EFE))
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uart_clear_errors(UART1);
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} while ((reg & UART_ISR_TX_EMPTY) == 0);
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UART_TDR(UART1) = c;
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return 1;
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}
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int uart_rx(uint8_t *c)
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{
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volatile uint32_t reg;
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reg = UART_ISR(UART1);
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if (reg & (UART_ENE | UART_EPE | UART_ORE | UART_EFE))
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uart_clear_errors(UART1);
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if (reg & UART_ISR_RX_NOTEMPTY) {
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*c = (uint8_t)UART_RDR(UART1);
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return 1;
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}
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return 0;
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}
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int uart_init(uint32_t bitrate, uint8_t data, char parity, uint8_t stop)
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{
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uint32_t reg;
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/* Enable USART1 peripheral clock */
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RCC_APB2ENR |= UART1_APB2_CLOCK_ER_VAL;
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/* If the UART is already running (e.g. left enabled by the secure
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* bootloader), let the last frame finish shifting out before
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* reconfiguring, or the character is cut mid-frame */
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if (UART_CR1(UART1) & UART_CR1_UART_ENABLE) {
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while ((UART_ISR(UART1) & UART_ISR_TX_COMPLETE) == 0) {};
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}
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uart_pins_setup();
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/* Use HSI16 as USART1 kernel clock, so the baud rate does not
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* depend on the current SYSCLK/PLL configuration */
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RCC_CR |= RCC_CR_HSION;
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while ((RCC_CR & RCC_CR_HSIRDY) == 0) {};
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reg = RCC_CCIPR1 & (~(RCC_CCIPR1_USART1SEL_MASK << RCC_CCIPR1_USART1SEL_SHIFT));
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RCC_CCIPR1 = reg | (RCC_CCIPR1_USART1SEL_HSI16 << RCC_CCIPR1_USART1SEL_SHIFT);
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/* Disable UART to configure BRR (only writable while disabled) */
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UART_CR1(UART1) &= ~UART_CR1_UART_ENABLE;
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/* Enable 16-bit oversampling */
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UART_CR1(UART1) &= ~UART_CR1_OVER8;
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/* Configure baud rate */
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UART_BRR(UART1) = (uint16_t)(HSI16_FREQ / bitrate);
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/* Configure data bits */
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if (data == 8)
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UART_CR1(UART1) &= ~UART_CR1_SYMBOL_LEN;
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else
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UART_CR1(UART1) |= UART_CR1_SYMBOL_LEN;
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/* Configure parity */
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switch (parity) {
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case 'O':
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UART_CR1(UART1) |= UART_CR1_PARITY_ODD;
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/* fall through to enable parity */
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/* FALL THROUGH */
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case 'E':
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UART_CR1(UART1) |= UART_CR1_PARITY_ENABLED;
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break;
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default:
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UART_CR1(UART1) &= ~(UART_CR1_PARITY_ENABLED | UART_CR1_PARITY_ODD);
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}
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/* Set stop bits */
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reg = UART_CR2(UART1) & ~UART_CR2_STOPBITS;
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if (stop > 1)
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UART_CR2(UART1) = reg | (2 << 12);
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else
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UART_CR2(UART1) = reg;
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/* Clear flags for async mode */
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UART_CR2(UART1) &= ~(UART_CR2_LINEN | UART_CR2_CLKEN);
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UART_CR3(UART1) &= ~(UART_CR3_SCEN | UART_CR3_HDSEL | UART_CR3_IREN);
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/* Configure for RX+TX, turn on. */
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UART_CR1(UART1) |= UART_CR1_TX_ENABLE | UART_CR1_RX_ENABLE | UART_CR1_UART_ENABLE;
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return 0;
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}
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#ifdef DEBUG_UART
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void uart_write(const char *buf, unsigned int len)
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{
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while (len--) {
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uart_tx(*buf);
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buf++;
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}
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}
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#endif
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#endif /* TARGET_stm32u5 */
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@ -654,6 +654,9 @@ ifeq ($(TARGET),stm32u5)
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endif
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CFLAGS+=-mcpu=cortex-m33
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LDFLAGS+=-mcpu=cortex-m33
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ifeq ($(DEBUG_UART),1)
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APP_OBJS+=../hal/uart/uart_drv_$(UART_TARGET)_ns.o
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endif
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endif
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ifeq ($(TARGET),stm32u3)
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@ -1382,6 +1385,9 @@ delta-extra-data: image.bin
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../hal/spi/spi_drv_$(SPI_TARGET)_ns.o: ../hal/spi/spi_drv_$(SPI_TARGET).c FORCE
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$(Q)$(CC) $(CFLAGS) -c -o $(@) ../hal/spi/spi_drv_$(SPI_TARGET).c -DNONSECURE_APP
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../hal/uart/uart_drv_$(UART_TARGET)_ns.o: ../hal/uart/uart_drv_$(UART_TARGET).c FORCE
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$(Q)$(CC) $(CFLAGS) -c -o $(@) ../hal/uart/uart_drv_$(UART_TARGET).c -DNONSECURE_APP
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board_$(BOARD).o: ../hal/boards/$(BOARD)/board.c
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@echo "\t[CC-$(ARCH)] $@"
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$(Q)$(CC) $(CFLAGS) -DDEBUG_UART -c $(OUTPUT_FLAG) $@ $<
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