diff --git a/Makefile b/Makefile
index cd89afec..5775577a 100644
--- a/Makefile
+++ b/Makefile
@@ -18,6 +18,7 @@ SECURE_LDFLAGS:=
 LD_START_GROUP:=-Wl,--start-group
 LD_END_GROUP:=-Wl,--end-group
 LSCRIPT_IN:=hal/$(TARGET).ld
+L2SRAM_ADDR?=0xF8F00000
 V?=0
 DEBUG?=0
 DEBUG_UART?=0
@@ -527,7 +528,8 @@ $(LSCRIPT): $(LSCRIPT_IN) FORCE
 		sed -e "s/@BOOTLOADER_START@/$(BOOTLOADER_START)/g" | \
 		sed -e "s/@IMAGE_HEADER_SIZE@/$(IMAGE_HEADER_SIZE)/g" | \
 		sed -e "s/@FSP_S_LOAD_BASE@/$(FSP_S_LOAD_BASE)/g" | \
-		sed -e "s/@WOLFBOOT_L2LIM_SIZE@/$(WOLFBOOT_L2LIM_SIZE)/g" \
+		sed -e "s/@WOLFBOOT_L2LIM_SIZE@/$(WOLFBOOT_L2LIM_SIZE)/g" | \
+		sed -e "s/@L2SRAM_ADDR@/$(L2SRAM_ADDR)/g" \
 		> $@
 
 hex: wolfboot.hex
diff --git a/config/examples/nxp-t2080.config b/config/examples/nxp-t2080.config
index a0ea638d..6627f5b7 100644
--- a/config/examples/nxp-t2080.config
+++ b/config/examples/nxp-t2080.config
@@ -41,6 +41,11 @@ OPTIMIZATION_LEVEL?=1
 ARCH_FLASH_OFFSET?=0xEFFE0000
 #ARCH_FLASH_OFFSET?=0xFFFE0000  # CW VPX3-152
 
+# CPC SRAM address (must match L2SRAM_ADDR in nxp_ppc.h)
+# CW VPX3-152: relocated to 0xEE900000 to avoid 256MB flash TLB overlap
+L2SRAM_ADDR?=0xF8F00000
+#L2SRAM_ADDR?=0xEE900000  # CW VPX3-152
+
 # Flash Sector Size
 WOLFBOOT_SECTOR_SIZE?=0x10000
 
diff --git a/hal/nxp_ppc.h b/hal/nxp_ppc.h
index ca4c8584..06c0d6d3 100644
--- a/hal/nxp_ppc.h
+++ b/hal/nxp_ppc.h
@@ -118,13 +118,18 @@
      * CPC SRAM (via CoreNet) is unreliable on cold power cycle —
      * store buffer drains cause bus errors. L1 locked cache is
      * core-local and works reliably from first instruction.
-     * Address chosen below CPC SRAM range, no backing memory needed. */
+     * Address chosen below CPC SRAM range, no backing memory needed.
+     *
+     * VPX3-152: default addresses (0xF8E/F8F) fall within 256MB flash
+     * VA range (0xF0000000-0xFFFFFFFF), causing TLB overlap on e6500.
+     * Relocated below CCSRBAR (0xEF000000) to avoid conflict. */
+#ifdef BOARD_CW_VPX3152
+    #define L1_CACHE_ADDR (0xEE800000UL)
+    #define L2SRAM_ADDR   (0xEE900000UL) /* CPC as SRAM (1MB) */
+#else
     #define L1_CACHE_ADDR (0xF8E00000UL)
-
-    /* T2080 CPC SRAM config - 1MB for ECC P384 stack requirements.
-     * CPC hardware is configured in early ASM but NOT used for stack.
-     * CPC SRAM becomes usable after cache hierarchy is initialized in C. */
     #define L2SRAM_ADDR   (0xF8F00000UL) /* CPC as SRAM (1MB) */
+#endif
     #define L2SRAM_SIZE   (1024UL * 1024UL)
 
     #define INITIAL_SRAM_ADDR     L2SRAM_ADDR
@@ -137,6 +142,14 @@
 
     #define ENABLE_INTERRUPTS
 
+#ifdef BOARD_CW_VPX3152
+    /* Relocate CCSRBAR: default 0xFE000000 (16MB) falls within 256MB flash
+     * VA range 0xF0000000-0xFFFFFFFF. Move to 0xEF000000 (just below flash).
+     * The existing relocation code in boot_ppc_start.S handles the hardware
+     * CCSRBAR register write when CCSRBAR_DEF != CCSRBAR_PHYS. */
+    #define CCSRBAR 0xEF000000UL
+#endif
+
     #define ENABLE_DDR
     #ifndef DDR_SIZE
     #ifdef BOARD_CW_VPX3152
diff --git a/hal/nxp_t2080.ld b/hal/nxp_t2080.ld
index a688b998..36812db3 100644
--- a/hal/nxp_t2080.ld
+++ b/hal/nxp_t2080.ld
@@ -2,20 +2,27 @@ OUTPUT_ARCH( "powerpc" )
 
 ENTRY( _reset )
 
-/* On initial start, only a limited space(4k) is accessible.
- * Code here bootstraps to enable access to other needed address spaces */
-BOOTSTRAP_TLB = 0xEFFFF000;
+/* On initial start, only a limited space (4K) is accessible.
+ * Code here bootstraps to enable access to other needed address spaces.
+ * Boot code must be at the top of flash (last 4KB of bootloader partition).
+ * Computed from FLASH region so it adapts to any board flash layout:
+ *   T2080 RDB (128MB @ 0xE8000000):   0xEFFFF000 / 0xEFFFFFFC
+ *   CW VPX3-152 (256MB @ 0xF0000000): 0xFFFFF000 / 0xFFFFFFFC */
+BOOTSTRAP_TLB = ORIGIN(FLASH) + LENGTH(FLASH) - 0x1000;
 
 /* Entry point where RCW directs code to execute from */
-BOOTSTRAP_ENTRY = 0xEFFFFFFC;
+BOOTSTRAP_ENTRY = ORIGIN(FLASH) + LENGTH(FLASH) - 0x4;
 
 MEMORY
 {
     FLASH (rx) : ORIGIN = @WOLFBOOT_ORIGIN@, LENGTH = @BOOTLOADER_PARTITION_SIZE@
 
     /* CPC as SRAM - 1MB (T2080 supports up to 2MB, using 1MB for P384 stack)
-     * Layout: .ramcode at bottom, stack grows down from top */
-    RAM (rwx) : ORIGIN = 0xF8F00000, LENGTH = 0x100000
+     * Layout: .ramcode at bottom, stack grows down from top
+     * Address must match L2SRAM_ADDR in nxp_ppc.h:
+     *   T2080 RDB:   0xF8F00000
+     *   CW VPX3-152: 0xEE900000 (relocated to avoid 256MB flash VA overlap) */
+    RAM (rwx) : ORIGIN = @L2SRAM_ADDR@, LENGTH = 0x100000
 
     /* DDR - 2GB */
     DRAM (rwx) : ORIGIN = 0x00000000, LENGTH = 0x7FFFFFFF