diff --git a/arch.mk b/arch.mk
index 4436093b..1586af82 100644
--- a/arch.mk
+++ b/arch.mk
@@ -316,15 +316,16 @@ endif
 
 ifeq ($(TARGET),nxp_p1021)
   # Power PC big endian
-  ARCH_FLAGS=-m32 -mhard-float -mcpu=e500mc
+  ARCH_FLAGS=-m32 -mhard-float -mcpu=e500mc -mno-powerpc64
+  ARCH_FLAGS+=-fno-builtin -ffreestanding -nostartfiles
+  ARCH_FLAGS+=-mno-pointers-to-nested-functions
   CFLAGS+=$(ARCH_FLAGS) -DBIG_ENDIAN_ORDER
   CFLAGS+=-DWOLFBOOT_DUALBOOT
   CFLAGS+=-pipe # use pipes instead of temp files
-  CFLAGS+=-feliminate-unused-debug-types
   LDFLAGS+=$(ARCH_FLAGS)
-  LDFLAGS+=-Wl,--hash-style=both # generate both sysv and gnu symbol hash table
   LDFLAGS+=-Wl,--as-needed # remove weak functions not used
   UPDATE_OBJS:=src/update_ram.o
+
   ifeq ($(SPMATH),1)
     MATH_OBJS += ./lib/wolfssl/wolfcrypt/src/sp_c32.o
   else
diff --git a/config/examples/nxp-p1021.config b/config/examples/nxp-p1021.config
old mode 100755
new mode 100644
diff --git a/docs/Targets.md b/docs/Targets.md
old mode 100755
new mode 100644
diff --git a/hal/nxp_p1021.c b/hal/nxp_p1021.c
old mode 100755
new mode 100644
index 8b1215b4..2c818179
--- a/hal/nxp_p1021.c
+++ b/hal/nxp_p1021.c
@@ -27,7 +27,7 @@
 
 #define ENABLE_ELBC
 #define ENABLE_DDR
-
+#define ENABLE_BUS_CLK_CALC
 #ifndef BUILD_LOADER_STAGE1
     #define ENABLE_PCIE
     #define ENABLE_CPLD /* Board Configuration and Status Registers (BCSR) */
@@ -60,10 +60,11 @@ static int test_tpm(void);
 
 
 /* P1021 Platform */
-//#define SYS_CLK (533000000) /* 533MHz */
-  #define SYS_CLK (400000000) /* 400MHz */
+/* System input clock */
+#define SYS_CLK (66666666) /* 66.666666 MHz */
 
-#define RESET_BPTR ((volatile uint32_t*)(CCSRBAR + 0x42)) /* Boot page translation register */
+/* Boot page translation register */
+#define RESET_BPTR ((volatile uint32_t*)(CCSRBAR + 0x42))
 
 /* Global Utilities (GUTS) */
 #define GUTS_BASE      (CCSRBAR + 0xE0000)
@@ -426,12 +427,25 @@ enum elbc_amask_sizes {
 #define ESPI_CSMODE_CSAFT(x) (((x) & 0xF) << 8)  /* CS assertion time in bits after frame end */
 #define ESPI_CSMODE_CSCG(x)  (((x) & 0xF) << 3)  /* Clock gaps between transmitted frames according to this size */
 
+static uint32_t hal_get_bus_clk(void)
+{
+    uint32_t bus_clk;
+#ifdef ENABLE_BUS_CLK_CALC
+    /* compute bus clock (system input 66MHz * ratio */
+    uint32_t plat_ratio = get32(GUTS_PORPLLSR);
+    /* mask and shift by 1 to get platform ratio */
+    plat_ratio = ((plat_ratio & 0x3E) >> 1);
+    bus_clk = SYS_CLK * plat_ratio;
+    return bus_clk;
+#else
+    return (uint32_t)(SYS_CLK * 6); /* can also be 8 */
+#endif
+}
 
 #if defined(ENABLE_ESPI) || defined(ENABLE_DDR)
 static void udelay(unsigned long delay_us)
 {
-    static const uint32_t oneus = (SYS_CLK / 1000000);
-    delay_us *= oneus;
+    delay_us *= (hal_get_bus_clk() / 1000000);
     wait_ticks(delay_us);
 }
 #endif
@@ -439,7 +453,7 @@ static void udelay(unsigned long delay_us)
 #ifdef ENABLE_ESPI
 void hal_espi_init(uint32_t cs, uint32_t clock_hz, uint32_t mode)
 {
-    uint32_t spibrg = SYS_CLK / 2, pm, csmode;
+    uint32_t spibrg = hal_get_bus_clk() / 2, pm, csmode;
 
     /* Enable eSPI with TX threadshold 4 and TX threshold 3 */
     set32(ESPI_SPMODE, (ESPI_SPMODE_EN | ESPI_SPMODE_TXTHR(4) |
@@ -536,17 +550,8 @@ void uart_init(void)
     /* calc divisor for UART
      * baud rate = CCSRBAR frequency ÷ (16 x [UDMB||UDLB])
      */
-#if 1
-    /* build time computed UART divisor */
-    const uint32_t div = (SYS_CLK / 16 / BAUD_RATE) + 1; /* round up */
-#else
-    /* example for how to compute based on PORPLLSR */
-    uint32_t plat_ratio, bus_clk, div;
-    plat_ratio = (get32(GUTS_PORPLLSR) & 0x0000003E);
-    plat_ratio >>= 1; /* divide by two */
-    bus_clk = plat_ratio * SYS_CLK;
-    div = (bus_clk / 16 / BAUD_RATE);
-#endif
+    /* compute UART divisor - round up */
+    uint32_t div = (hal_get_bus_clk() + (16/2 * BAUD_RATE)) / (16 * BAUD_RATE);
 
     while (!(get8(UART_LSR(UART_SEL)) & UART_LSR_TEMT))
        ;
@@ -1066,23 +1071,11 @@ static void hal_io_init(void)
 
 void hal_init(void)
 {
-#ifdef GET_PSVR
-    uint32_t pvr, svr;
-#endif
-
 #ifdef DEBUG_UART
     uart_init();
     uart_write("wolfBoot HAL Init\n", 19);
 #endif
 
-#ifdef GET_PSVR
-    /* Platform and System version information */
-    pvr = GUTS_PVR;
-    svr = GUTS_SVR;
-    (void)pvr;
-    (void)svr;
-#endif
-
 #ifdef ENABLE_PCIE
     hal_pcie_init();
 #endif
@@ -1361,7 +1354,7 @@ void ext_flash_unlock(void)
 #ifdef MMU
 void* hal_get_dts_address(void)
 {
-    return (void*)WOLFBOOT_LOAD_DTS_ADDRESS;
+    return NULL; /* WOLFBOOT_LOAD_DTS_ADDRESS not required */
 }
 #endif
 
diff --git a/hal/nxp_p1021_stage1.ld b/hal/nxp_p1021_stage1.ld
old mode 100755
new mode 100644
index 64ddf180..fefdcd49
--- a/hal/nxp_p1021_stage1.ld
+++ b/hal/nxp_p1021_stage1.ld
@@ -4,11 +4,11 @@ ENTRY( _reset )
 
 /* Adjust base address to 0xF8F80000 is debugging (run from L2 cache) */
 /* Boot ROM out of reset mapped to 0xFFFF0000 */
-BASE_ADDR = 0xFFFF0000;
+BASE_ADDR = 0xFFFF0000; /* 0xF8F80000 */
 
 /* Boot ROM requires it must be < 4KB */
 /* If debugging this can be increased */
-LOADER_STAGE1_SIZE = @WOLFBOOT_STAGE1_SIZE@;
+LOADER_STAGE1_SIZE = @WOLFBOOT_STAGE1_SIZE@; /* 0x4000 */
 
 /* Boot initialization code */
 BOOTSTRAP_TLB = BASE_ADDR;
@@ -61,6 +61,10 @@ SECTIONS
     .data : AT (_stored_data)
     {
         _start_data = .;
+        KEEP(*(.iplt*))
+        KEEP(*(.plt*))
+        KEEP(*(.got1*))
+        KEEP(*(.got2*))
         KEEP(*(.data*))
         . = ALIGN(4);
         KEEP(*(.ramcode))
diff --git a/hal/nxp_ppc.h b/hal/nxp_ppc.h
old mode 100755
new mode 100644
index 9fd5a7e9..a5ee76b4
--- a/hal/nxp_ppc.h
+++ b/hal/nxp_ppc.h
@@ -26,8 +26,6 @@
 #define CCSRBAR_DEF (0xFF700000) /* P1021RM 4.3 default base */
 #define CCSRBAR_SIZE BOOKE_PAGESZ_1M
 #define MMU_V1
-#define ENABLE_L1_CACHE
-#define ENABLE_L2_CACHE
 
 /* Memory used for transferring blocks to/from NAND.
  * Maps to eLBC FCM internal 8KB region (by hardware) */
@@ -35,6 +33,9 @@
 
 /* For full wolfBoot */
 #ifndef BUILD_LOADER_STAGE1
+    #define ENABLE_L1_CACHE
+    #define ENABLE_L2_CACHE
+
     /* Relocate CCSRBAR */
     #define CCSRBAR 0xFFE00000
 
@@ -134,6 +135,10 @@
 #define L1_CACHE_SZ     (32 * 1024)
 #endif
 
+#ifndef L1_CACHE_LINE_SIZE
+#define L1_CACHE_LINE_SIZE (1 << L1_CACHE_LINE_SHIFT)
+#endif
+
 
 /* MMU Assist Registers */
 #define MAS0     0x270
diff --git a/src/boot_ppc.c b/src/boot_ppc.c
index f2b8f571..4975d67d 100644
--- a/src/boot_ppc.c
+++ b/src/boot_ppc.c
@@ -108,6 +108,31 @@ void boot_entry_C(void)
     main();
 }
 
+#ifndef BUILD_LOADER_STAGE1
+void flush_cache(uint32_t start_addr, uint32_t size)
+{
+    uint32_t addr, start, end;
+
+    start = start_addr & ~(L1_CACHE_LINE_SIZE - 1);
+    end = start_addr + size - 1;
+
+    for (addr = start; (addr <= end) && (addr >= start);
+            addr += L1_CACHE_LINE_SIZE) {
+        asm volatile("dcbst 0,%0" : : "r" (addr) : "memory");
+    }
+    /* wait for all dcbst to complete on bus */
+    asm volatile("sync" : : : "memory");
+
+    for (addr = start; (addr <= end) && (addr >= start);
+            addr += L1_CACHE_LINE_SIZE) {
+        asm volatile("icbi 0,%0" : : "r" (addr) : "memory");
+    }
+    asm volatile("sync" : : : "memory");
+    /* flush prefetch queue */
+    asm volatile("isync" : : : "memory");
+}
+#endif
+
 #ifdef MMU
 void do_boot(const uint32_t *app_offset, const uint32_t* dts_offset)
 #else
@@ -119,6 +144,12 @@ void do_boot(const uint32_t *app_offset)
     (void)dts_offset;
 #endif
 
+#ifndef BUILD_LOADER_STAGE1
+    /* invalidate cache */
+    flush_cache((uint32_t)app_offset, L1_CACHE_SZ);
+#endif
+
+    /* do branch unconditionally */
     asm volatile("mtlr %0; blr":: "r"(app_offset));
 }
 
diff --git a/src/boot_ppc_start.S b/src/boot_ppc_start.S
old mode 100755
new mode 100644
index c22cfaa3..f9559c1c
--- a/src/boot_ppc_start.S
+++ b/src/boot_ppc_start.S
@@ -123,12 +123,10 @@ Also see MPC8544ERM
 
 _reset:
 
-#ifdef DEBUG
         /* CRM 9.9.2 and EREF 10.4 enable debug interrupt */
         /* Set MSR DE (Debug Interrupt Enable = 1) */
         li      r1, MSR_DE
         mtmsr   r1
-#endif
 
 #ifdef PLATFORM_nxp_p1021
         /* Errata: A-005125 - force the core to process all snoops of IO device
@@ -461,18 +459,16 @@ switch_as:
 #endif
 
 setup_l1:
+#ifdef ENABLE_L1_CACHE
         /* L1 Instruction Cache */
         l1_cache_invalidate(L1CSR1);
-        #ifdef ENABLE_L1_CACHE
         l1_cache_enable(L1CSR1);
-        #endif
+
         /* L1 Data Cache */
         l1_cache_invalidate(L1CSR0);
-        #ifdef ENABLE_L1_CACHE
         l1_cache_enable(L1CSR0);
-        #endif
+#endif
 
-#ifdef ENABLE_L1_CACHE
 l1_tlb:
 
         /* L1: TLB 0, Supervisor X/R/W, TS=0, 16K */
@@ -486,13 +482,15 @@ l1_tlb:
         set_tlb(0, 0, L1_CACHE_ADDR+0x3000, L1_CACHE_ADDR+0x1000, 0,
                 (MAS3_SX | MAS3_SW | MAS3_SR), 0, 0, BOOKE_PAGESZ_4K, 0, r3);
 
+#ifdef ENABLE_L1_CACHE
 l1_cache:
         /* setup L1 cache */
         lis     r3, L1_CACHE_ADDR@h
         ori     r3, r3, L1_CACHE_ADDR@l
+        /* read the cache size */
         mfspr   r2, L1CFG0
         andi.   r2, r2, 0x1FF
-        /* cache size * 1024 / (2 * L1 line size) */
+        /* calculate (cache size * 1024 / (2 * L1 line size)) */
         slwi    r2, r2, (10 - 1 - L1_CACHE_LINE_SHIFT)
         mtctr   r2
         li      r0, 0
@@ -500,7 +498,7 @@ l1_cache:
 l1_cache_init:
         dcbz    r0, r3
         dcbtls  0, r0, r3
-        addi    r3, r3, (1 << L1_CACHE_LINE_SHIFT)
+        addi    r3, r3, L1_CACHE_LINE_SIZE
         bdnz    l1_cache_init
 #endif /* ENABLE_L1_CACHE */
 
diff --git a/stage1/Makefile b/stage1/Makefile
index ba27802e..7a372f18 100644
--- a/stage1/Makefile
+++ b/stage1/Makefile
@@ -46,9 +46,9 @@ CFLAGS+= \
 
 # Setup default optimizations (for GCC)
 ifeq ($(USE_GCC_HEADLESS),1)
-  CFLAGS+=-Wall -Wextra -Wno-main -ffreestanding -Wno-unused -nostartfiles
-  CFLAGS+=-ffunction-sections -fdata-sections -fomit-frame-pointer
-  LDFLAGS+=-Wl,-gc-sections -Wl,-Map=loader_stage1.map -ffreestanding -nostartfiles
+  CFLAGS+=-Wall -Wextra -Wno-main -Wno-unused
+  CFLAGS+=-ffunction-sections -fdata-sections
+  LDFLAGS+=-Wl,-gc-sections -Wl,-Map=loader_stage1.map
   LSCRIPT_FLAGS+=-T $(LSCRIPT)
 endif
 
@@ -73,6 +73,10 @@ CFLAGS+=\
 # For printf support (disable NO_PRINTF_UART) and increase WOLFBOOT_STAGE1_SIZE
 CFLAGS+=-DNO_PRINTF_UART
 
+# Use PIC (Position Independent Code) for first stage loader
+CFLAGS+=-fPIC
+
+
 BUILD_DIR=.
 LS1_OBJS=$(addprefix $(BUILD_DIR)/, $(notdir $(OBJS)))
 vpath %.c $(dir ../src)
diff --git a/stage1/loader_stage1.c b/stage1/loader_stage1.c
old mode 100755
new mode 100644
index 583452c3..f9e9a94e
--- a/stage1/loader_stage1.c
+++ b/stage1/loader_stage1.c
@@ -46,6 +46,14 @@
 #include "hal/nxp_ppc.h"
 #endif
 
+#ifndef DO_BOOT
+#ifdef MMU
+#define DO_BOOT(addr) do_boot((addr), NULL)
+#else
+#define DO_BOOT(addr) do_boot((addr))
+#endif
+#endif
+
 int main(void)
 {
     int ret = -1;
@@ -71,7 +79,7 @@ int main(void)
         memmove((void*)WOLFBOOT_STAGE1_BASE_ADDR, (void*)BOOT_ROM_ADDR,
             BOOT_ROM_SIZE);
 
-        do_boot(wolfboot_start); /* never returns */
+        DO_BOOT(wolfboot_start); /* never returns */
     }
 #endif
 
@@ -88,7 +96,7 @@ int main(void)
         uart_write("Jump to relocated wolfboot_start\r\n", 34);
     #endif
 
-        do_boot(wolfboot_start); /* never returns */
+        DO_BOOT(wolfboot_start); /* never returns */
     }
 
     return 0;
diff --git a/test-app/Makefile b/test-app/Makefile
old mode 100755
new mode 100644
diff --git a/test-app/PPC.ld b/test-app/PPC.ld
old mode 100755
new mode 100644
diff --git a/test-app/app_nxp_p1021.c b/test-app/app_nxp_p1021.c
old mode 100755
new mode 100644