mirror of https://github.com/wolfSSL/wolfBoot.git
Fix RT1050 example app LED. Fix documentation for test-app location. Peer review feedback to clarify RT1050 flash chip configuration.
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b33da11d7d
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7073bf33b4
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@ -1053,6 +1053,8 @@ DCP support (hardware acceleration for SHA256 operations) can be enabled by usin
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Firmware can be directly uploaded to the target by copying `factory.bin` to the virtual USB drive associated to the device, or by loading the image directly into flash using a JTAG/SWD debugger.
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Firmware can be directly uploaded to the target by copying `factory.bin` to the virtual USB drive associated to the device, or by loading the image directly into flash using a JTAG/SWD debugger.
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For the RT1050 board it comes wired to use the HyperFlash, but wolfBoot is setup for QSPI. There is a rework that can be performed (see AN12183) to use the onboard 8MB ISSI IS25WP064A. Optionally you can define `CONFIG_FLASH_W25Q64JV` for the Winbond W25Q64JV.
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### Testing Update
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### Testing Update
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```sh
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```sh
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@ -1072,7 +1074,7 @@ loadbin update.bin 0x60030000
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```sh
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```sh
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JLinkGDBServer -Device MIMXRT1052xxx6A -speed 5000 -if swd -port 3333
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JLinkGDBServer -Device MIMXRT1052xxx6A -speed 5000 -if swd -port 3333
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arm-none-eabi-gdb
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arm-none-eabi-gdb
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add-symbol-file test-app/image.elf 0x60010000
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add-symbol-file test-app/image.elf 0x60010100
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mon reset init
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mon reset init
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b main
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b main
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c
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c
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@ -285,14 +285,10 @@ const flexspi_nor_config_t __attribute__((section(".flash_config"))) qspiflash_c
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#define CONFIG_FLASH_ADDR_WIDTH 24u /* Width of flash addresses (either 24 or 32) */
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#define CONFIG_FLASH_ADDR_WIDTH 24u /* Width of flash addresses (either 24 or 32) */
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#define CONFIG_FLASH_QE_ENABLE 1
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#define CONFIG_FLASH_QE_ENABLE 1
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/* Please define one of these */
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#ifdef CONFIG_FLASH_W25Q64JV /* Winbond W25Q64JV */
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//#define CONFIG_FLASH_IS25WP064A /* ISSI IS25WP064A */
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//#define CONFIG_FLASH_W25Q64JV /* Winbond W25Q64JV */
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#ifdef CONFIG_FLASH_W25Q64JV
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#define WRITE_STATUS_CMD 0x31
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#define WRITE_STATUS_CMD 0x31
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#define QE_ENABLE 0x02 /* S9 */
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#define QE_ENABLE 0x02 /* S9 */
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#else
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#else /* Default - ISSI IS25WP064A (on EVKB) */
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#define WRITE_STATUS_CMD 0x1
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#define WRITE_STATUS_CMD 0x1
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#define QE_ENABLE 0x40 /* S6 */
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#define QE_ENABLE 0x40 /* S6 */
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#endif
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#endif
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@ -551,7 +547,6 @@ void hal_init(void)
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ARM_MPU_Disable();
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ARM_MPU_Disable();
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clock_init();
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clock_init();
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hal_flash_init();
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hal_flash_init();
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//SCB_EnableICache();
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}
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}
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void hal_prepare_boot(void)
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void hal_prepare_boot(void)
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@ -28,20 +28,26 @@
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static int g_pinSet = false;
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static int g_pinSet = false;
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extern void imx_rt_init_boot_clock(void);
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extern void imx_rt_init_boot_clock(void);
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#ifndef USER_LED_GPIO
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#define USER_LED_GPIO GPIO1
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#endif
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#ifndef USER_LED_PIN
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#define USER_LED_PIN 9U
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#endif
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/* Get debug console frequency. */
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/* Get debug console frequency. */
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static uint32_t debug_console_get_freq(void)
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static uint32_t debug_console_get_freq(void)
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{
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{
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uint32_t freq;
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uint32_t freq;
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/* To make it simple, we assume default PLL and divider settings, and the only variable
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from application is use PLL3 source or OSC source */
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/* To make it simple, we assume default PLL and divider settings, and the
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if (CLOCK_GetMux(kCLOCK_UartMux) == 0) /* PLL3 div6 80M */
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* only variable from application is use PLL3 source or OSC source */
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{
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if (CLOCK_GetMux(kCLOCK_UartMux) == 0) { /* PLL3 div6 80M */
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freq = (CLOCK_GetPllFreq(kCLOCK_PllUsb1) / 6U) / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U);
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freq = (CLOCK_GetPllFreq(kCLOCK_PllUsb1) / 6U) /
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(CLOCK_GetDiv(kCLOCK_UartDiv) + 1U);
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}
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}
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else
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else {
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{
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freq = CLOCK_GetOscFreq() / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U);
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freq = CLOCK_GetOscFreq() / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U);
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}
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}
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@ -60,41 +66,47 @@ void init_debug_console(void)
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#if defined(CPU_MIMXRT1062DVL6A) || defined(CPU_MIMXRT1064DVL6A)
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#if defined(CPU_MIMXRT1062DVL6A) || defined(CPU_MIMXRT1064DVL6A)
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/* Pin settings (same for both 1062 and 1064) */
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/* Pin settings (same for both 1062 and 1064) */
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void rt1060_init_pins(void) {
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void rt1060_init_pins(void)
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CLOCK_EnableClock(kCLOCK_Iomuxc); /* iomuxc clock (iomuxc_clk_enable): 0x03U */
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{
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gpio_pin_config_t USER_LED_config = {
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gpio_pin_config_t USER_LED_config = {
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.direction = kGPIO_DigitalOutput,
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.direction = kGPIO_DigitalOutput,
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.outputLogic = 0U,
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.outputLogic = 0U,
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.interruptMode = kGPIO_NoIntmode
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.interruptMode = kGPIO_NoIntmode
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};
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};
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GPIO_PinInit(GPIO1, 9U, &USER_LED_config);
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IOMUXC_SetPinMux(
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CLOCK_EnableClock(kCLOCK_Iomuxc); /* iomuxc clock (iomuxc_clk_enable): 0x03U */
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IOMUXC_GPIO_AD_B0_10_ARM_TRACE_SWO, /* GPIO_AD_B0_10 is configured as ARM_TRACE_SWO */
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0U);
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GPIO_PinInit(USER_LED_GPIO, USER_LED_PIN, &USER_LED_config);
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IOMUXC_SetPinMux(
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IOMUXC_GPIO_AD_B0_12_LPUART1_TX, /* GPIO_AD_B0_12 is configured as LPUART1_TX */
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IOMUXC_SetPinMux( /* GPIO_AD_B0_10 is configured as ARM_TRACE_SWO */
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0U);
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IOMUXC_GPIO_AD_B0_10_ARM_TRACE_SWO, 0U);
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IOMUXC_SetPinMux(
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IOMUXC_SetPinMux( /* GPIO_AD_B0_12 is configured as LPUART1_TX */
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IOMUXC_GPIO_AD_B0_13_LPUART1_RX, /* GPIO_AD_B0_13 is configured as LPUART1_RX */
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IOMUXC_GPIO_AD_B0_12_LPUART1_TX, 0U);
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0U);
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IOMUXC_SetPinMux( /* GPIO_AD_B0_13 is configured as LPUART1_RX */
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IOMUXC_SetPinConfig(
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IOMUXC_GPIO_AD_B0_13_LPUART1_RX, 0U);
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IOMUXC_GPIO_AD_B0_10_ARM_TRACE_SWO, /* GPIO_AD_B0_10 PAD functional properties : */
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IOMUXC_SetPinConfig( /* GPIO_AD_B0_10 PAD functional properties : */
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0x90B1U);
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IOMUXC_GPIO_AD_B0_10_ARM_TRACE_SWO, 0x90B1U);
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IOMUXC_SetPinConfig(
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IOMUXC_SetPinConfig( /* GPIO_AD_B0_12 PAD functional properties : */
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IOMUXC_GPIO_AD_B0_12_LPUART1_TX, /* GPIO_AD_B0_12 PAD functional properties : */
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IOMUXC_GPIO_AD_B0_12_LPUART1_TX, 0x10B0U);
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0x10B0U);
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IOMUXC_SetPinConfig( /* GPIO_AD_B0_13 PAD functional properties : */
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IOMUXC_SetPinConfig(
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IOMUXC_GPIO_AD_B0_13_LPUART1_RX, 0x10B0U);
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IOMUXC_GPIO_AD_B0_13_LPUART1_RX, /* GPIO_AD_B0_13 PAD functional properties : */
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0x10B0U);
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}
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}
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#endif
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#endif
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#ifdef CPU_MIMXRT1052DVJ6B
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#ifdef CPU_MIMXRT1052DVJ6B
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void rt1050_init_pins(void) {
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void rt1050_init_pins(void)
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{
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gpio_pin_config_t USER_LED_config = {
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.direction = kGPIO_DigitalOutput,
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.outputLogic = 0U,
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.interruptMode = kGPIO_NoIntmode
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};
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CLOCK_EnableClock(kCLOCK_Iomuxc);
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CLOCK_EnableClock(kCLOCK_Iomuxc);
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GPIO_PinInit(USER_LED_GPIO, USER_LED_PIN, &USER_LED_config);
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IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_12_LPUART1_TXD, 0U);
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IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_12_LPUART1_TXD, 0U);
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IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_13_LPUART1_RXD, 0U);
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IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_13_LPUART1_RXD, 0U);
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IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_04_CCM_CLKO1, 0U);
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IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_04_CCM_CLKO1, 0U);
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@ -107,34 +119,38 @@ void rt1050_init_pins(void) {
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#endif
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#endif
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void main(void)
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void main()
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{
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{
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imx_rt_init_boot_clock();
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imx_rt_init_boot_clock();
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#if defined(CPU_MIMXRT1062DVL6A) || defined(CPU_MIMXRT1064DVL6A)
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#if defined(CPU_MIMXRT1062DVL6A) || defined(CPU_MIMXRT1064DVL6A)
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rt1060_init_pins();
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rt1060_init_pins();
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#endif
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#elif defined(CPU_MIMXRT1052DVJ6B)
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#ifdef CPU_MIMXRT1052DVJ6B
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rt1050_init_pins();
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rt1050_init_pins();
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#endif
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#endif
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SystemCoreClockUpdate();
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SystemCoreClockUpdate();
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SysTick_Config(SystemCoreClock / 1000U);
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SysTick_Config(SystemCoreClock / 1000U);
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init_debug_console();
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init_debug_console();
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PRINTF("wolfBoot Test app, version = %d\n", wolfBoot_current_firmware_version());
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PRINTF("wolfBoot Test app, version = %d\r\n",
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wolfBoot_current_firmware_version());
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/* enable to test update trigger on reboot */
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#if 0
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wolfBoot_update_trigger();
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#endif
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while (1) {
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while (1) {
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SDK_DelayAtLeastUs(100000, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);
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/* 100ms delay */
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if (g_pinSet)
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SDK_DelayAtLeastUs(100 * 1000, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);
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{
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GPIO_PinWrite(GPIO1, 9U, 0U);
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/* toggle user LED */
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if (g_pinSet) {
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GPIO_PinWrite(USER_LED_GPIO, USER_LED_PIN, 0U);
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g_pinSet = false;
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g_pinSet = false;
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}
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}
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else
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else {
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{
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GPIO_PinWrite(USER_LED_GPIO, USER_LED_PIN, 1U);
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GPIO_PinWrite(GPIO1, 9U, 1U);
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g_pinSet = true;
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g_pinSet = true;
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}
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}
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}
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}
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}
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}
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