mirror of https://github.com/wolfSSL/wolfBoot.git
Add wolfBoot target for NXP i.MX95 Cortex-M7
David Garske
Daniele Lacamera
parent
8015a1fa4f
commit
724ca34677
3
arch.mk
3
arch.mk
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@ -284,6 +284,9 @@ ifeq ($(ARCH),ARM)
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ifeq ($(TARGET),imx_rt)
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CORTEX_M7=1
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endif
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ifeq ($(TARGET),imx95_m7)
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CORTEX_M7=1
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endif
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ifeq ($(TARGET),stm32l0)
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CORTEX_M0=1
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SPI_TARGET=stm32
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@ -0,0 +1,35 @@
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ARCH?=ARM
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TARGET?=imx95_m7
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SIGN?=ECC256
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HASH?=SHA256
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DEBUG?=0
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VTOR?=1
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CORTEX_M0?=0
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NO_ASM?=0
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NO_MPU?=1
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EXT_FLASH?=0
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SPI_FLASH?=0
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ALLOW_DOWNGRADE?=0
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NVM_FLASH_WRITEONCE?=0
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WOLFBOOT_VERSION?=0
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V?=0
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SPMATH?=1
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RAM_CODE?=1
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DUALBANK_SWAP?=0
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PKA?=0
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# wolfBoot runs from ITCM; the partitions live in the M7's reserved DDR window
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# (memory@80000000, 16 MiB) where Linux stages images before restarting the
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# core. See hal/imx95_m7.c for why "flash" here is ordinary DDR.
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WOLFBOOT_PARTITION_SIZE?=0x400000
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WOLFBOOT_PARTITION_BOOT_ADDRESS?=0x80100000
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WOLFBOOT_PARTITION_UPDATE_ADDRESS?=0x80500000
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WOLFBOOT_PARTITION_SWAP_ADDRESS?=0x80900000
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# Sized for ML-DSA-87 from the start, even though bring-up signs with ECC256,
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# so switching to SIGN=ML_DSA is a config change rather than a re-layout.
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# ML-DSA-87: 4627-byte signature, 2592-byte public key.
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WOLFBOOT_SECTOR_SIZE?=0x4000
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IMAGE_HEADER_SIZE?=12288
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WOLFBOOT_SMALL_STACK?=0
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@ -0,0 +1,290 @@
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/* imx95_m7.c
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*
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* HAL for the Cortex-M7 on the NXP i.MX95.
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*
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* Copyright (C) 2026 wolfSSL Inc.
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*
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* This file is part of wolfBoot.
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*
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* wolfBoot is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 3 of the License, or
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* (at your option) any later version.
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*
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* wolfBoot is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
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*/
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/* The M7 on this part has no dedicated flash. wolfBoot is loaded into TCM by
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* the Linux remoteproc driver on the A55 cluster, and the images it verifies
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* live in the DDR region reserved for the M7 (memory@80000000, 16 MiB). The
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* "flash" the partitions sit in is therefore ordinary DDR: writes are copies
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* and erases are fills. Updates are staged by Linux writing the update
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* partition before restarting the core.
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*
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* Addresses come from the i.MX 95 Reference Manual rev 5 ch. 123 and from the
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* board's own device tree; see BOARD-FINDINGS.md in the demo tree.
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*
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* ITCM core view 0x00000000 system view 0x203C0000 256 KiB
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* DTCM core view 0x20000000 system view 0x20400000 256 KiB
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* DDR 0x80000000 16 MiB
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*
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* The core/system distinction matters: wolfBoot is linked for the core view,
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* while remoteproc loads through the system view and the imx_rproc driver
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* translates between them.
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*/
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#include <stdint.h>
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#include <stddef.h>
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#include <string.h>
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#include <target.h>
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#include "image.h"
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/* ---------------------------------------------------------------------------
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* remoteproc resource table
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*
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* Linux finds the resource table by looking for a .resource_table section in
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* the ELF *it* loads. On this target that ELF is wolfBoot, not the payload, so
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* the vdev/vring declaration has to live here even though the RPMsg endpoint is
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* serviced later by whatever wolfBoot boots. Without it the kernel logs
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* "No resource table in elf" and never creates the virtio device.
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*
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* The addresses are the ones the board's device tree already reserves, so the
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* two sides agree by construction rather than by convention:
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*
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* vdev0vring0 0x88000000 32 KiB
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* vdev0vring1 0x88008000 32 KiB
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* vdevbuffer 0x88020000 1 MiB
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*
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* A vring of 256 buffers at 4 KiB alignment needs about 10 KiB, so each fits
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* its 32 KiB reservation with room to spare.
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* ------------------------------------------------------------------------- */
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#define RSC_VDEV 3U
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#define VIRTIO_ID_RPMSG 7U
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#define VIRTIO_RPMSG_F_NS (1U << 0) /* name service announcements */
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#define RSC_VRING0_DA 0x88000000U
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#define RSC_VRING1_DA 0x88008000U
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#define RSC_VRING_ALIGN 0x1000U
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#define RSC_VRING_NUM 256U
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struct fw_rsc_vdev_vring {
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uint32_t da;
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uint32_t align;
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uint32_t num;
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uint32_t notifyid;
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uint32_t reserved;
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};
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struct fw_rsc_vdev {
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uint32_t type;
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uint32_t id;
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uint32_t notifyid;
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uint32_t dfeatures;
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uint32_t gfeatures;
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uint32_t config_len;
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uint8_t status;
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uint8_t num_of_vrings;
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uint8_t reserved[2];
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struct fw_rsc_vdev_vring vring[2];
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};
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struct imx95_rsc_table {
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uint32_t ver;
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uint32_t num;
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uint32_t reserved[2];
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uint32_t offset[1];
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struct fw_rsc_vdev vdev;
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};
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const struct imx95_rsc_table resource_table
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__attribute__((section(".resource_table"), used)) = {
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1, /* ver */
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1, /* num: one entry */
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{ 0, 0 }, /* reserved */
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{ offsetof(struct imx95_rsc_table, vdev) },
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{
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RSC_VDEV,
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VIRTIO_ID_RPMSG,
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0, /* notifyid, assigned by the host */
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VIRTIO_RPMSG_F_NS, /* dfeatures */
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0, /* gfeatures, filled by the host */
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0, /* config_len */
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0, /* status, driven by the host */
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2, /* num_of_vrings */
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{ 0, 0 },
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{
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{ RSC_VRING0_DA, RSC_VRING_ALIGN, RSC_VRING_NUM, 0, 0 },
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{ RSC_VRING1_DA, RSC_VRING_ALIGN, RSC_VRING_NUM, 1, 0 }
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}
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}
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};
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/* Erased state of the DDR-backed pseudo-flash. */
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#define FLASH_ERASED_BYTE 0xFFU
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/* Bounds of the M7's reserved DDR window. Anything outside it is rejected
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* rather than silently corrupting memory that belongs to Linux. */
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#define M7_DDR_BASE 0x80000000UL
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#define M7_DDR_SIZE 0x01000000UL
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/* Liveness marker. The M7 has no confirmed UART route on this carrier, so
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* early bring-up reports progress through shared memory that Linux can read
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* with devmem instead of over a serial port.
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*
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* This lives inside the M7's own DDR window, immediately above the console
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* ring at 0x80F00000, and deliberately NOT in the 0x88000000 block: the device
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* tree reserves that for RPMsg (vdev0/vdev1 vrings, and a 1 MiB vdevbuffer at
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* 0x88020000), so a status word there would be scribbling on buffers Linux
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* owns as soon as RPMsg is brought up. */
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#define WOLFBOOT_STATUS_ADDR 0x80F10000UL
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#define WOLFBOOT_STATUS_MAGIC 0x57424F54UL /* "WBOT" */
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/* Cortex-M7 DWT cycle counter. With no usable console on this carrier the
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* cycle counter is how the signature-verification cost gets measured: it is
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* exact, free to read, and needs no peripheral. Timestamps are published
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* alongside the status word for the A55 to read. */
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#define CORE_DEMCR (*(volatile uint32_t *)0xE000EDFCUL)
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#define DEMCR_TRCENA (1UL << 24)
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#define DWT_CTRL (*(volatile uint32_t *)0xE0001000UL)
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#define DWT_CYCCNTENA (1UL << 0)
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#define DWT_CYCCNT (*(volatile uint32_t *)0xE0001004UL)
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/* Cortex-M7 cache maintenance. Both caches are OFF out of reset, and this
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* image runs its text from DDR, so leaving them off means every instruction
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* fetch and data access goes to external memory - measured at ~664 cycles per
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* byte for SHA-256, roughly fifty times slower than the core is capable of.
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*
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* The ARMv7-M default memory map already marks 0x80000000-0x9FFFFFFF as normal
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* cacheable memory, so no MPU region is needed to make this take effect. */
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#define SCB_CCR (*(volatile uint32_t *)0xE000ED14UL)
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#define SCB_CCSIDR (*(volatile uint32_t *)0xE000ED80UL)
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#define SCB_CSSELR (*(volatile uint32_t *)0xE000ED84UL)
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#define SCB_ICIALLU (*(volatile uint32_t *)0xE000EF50UL)
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#define SCB_DCISW (*(volatile uint32_t *)0xE000EF60UL)
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#define CCR_IC (1UL << 17)
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#define CCR_DC (1UL << 16)
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#define DSB() __asm__ volatile ("dsb 0xF" ::: "memory")
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#define ISB() __asm__ volatile ("isb 0xF" ::: "memory")
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static void hal_cache_enable(void)
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{
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uint32_t ccsidr, sets, ways, s, w;
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/* I-cache: invalidate, then enable. */
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DSB(); ISB();
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SCB_ICIALLU = 0UL;
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DSB(); ISB();
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SCB_CCR |= CCR_IC;
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DSB(); ISB();
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/* D-cache: invalidate every set/way before enabling, otherwise stale
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* lines from reset can be written back over live DDR. */
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SCB_CSSELR = 0UL; /* select L1 data cache */
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DSB();
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ccsidr = SCB_CCSIDR;
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sets = (ccsidr >> 13) & 0x7FFFUL;
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ways = (ccsidr >> 3) & 0x3FFUL;
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for (s = 0; s <= sets; s++) {
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for (w = 0; w <= ways; w++) {
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/* DCISW: way in [31:30], set in [13:5] for a 32-byte line. */
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SCB_DCISW = ((w << 30) | (s << 5));
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}
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}
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DSB();
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SCB_CCR |= CCR_DC;
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DSB(); ISB();
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}
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static void hal_cycle_counter_start(void)
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{
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CORE_DEMCR |= DEMCR_TRCENA;
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DWT_CYCCNT = 0;
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DWT_CTRL |= DWT_CYCCNTENA;
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}
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static int hal_addr_is_valid(uint32_t address, int len)
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{
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uint64_t start = (uint64_t)address;
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uint64_t end;
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if (len < 0)
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return 0;
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end = start + (uint64_t)len;
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if (start < (uint64_t)M7_DDR_BASE)
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return 0;
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if (end > (uint64_t)M7_DDR_BASE + (uint64_t)M7_DDR_SIZE)
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return 0;
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return 1;
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}
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#ifdef __WOLFBOOT
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/* Record a progress code where the A55 side can see it. Kept deliberately
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* trivial: no locking, no ordering guarantees beyond the write itself. */
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void hal_status(uint32_t code)
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{
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volatile uint32_t *status = (volatile uint32_t *)WOLFBOOT_STATUS_ADDR;
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status[0] = WOLFBOOT_STATUS_MAGIC;
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status[1] = code;
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/* status[2] is stamped at hal_init, status[3] at hal_prepare_boot; the
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* difference is the cost of everything wolfBoot does in between, which is
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* dominated by the signature verification. */
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status[code + 1] = DWT_CYCCNT;
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}
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void hal_init(void)
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{
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/* Clocks, DDR and the TCM split are configured before this core is
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* released: DDR by the OEI/SPL stage, the TCM split by the System Manager
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* on the M33 via M7_CFG[TCM_SIZE] in BLK_CTRL_Secure_AON. There is
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* nothing for wolfBoot to bring up here except the caches, which are off
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* out of reset and which this image needs because it runs from DDR. */
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hal_cache_enable();
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hal_cycle_counter_start();
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hal_status(1);
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}
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void hal_prepare_boot(void)
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{
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hal_status(2);
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}
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#endif /* __WOLFBOOT */
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int RAMFUNCTION hal_flash_write(uint32_t address, const uint8_t *data, int len)
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{
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if (data == NULL)
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return -1;
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if (!hal_addr_is_valid(address, len))
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return -1;
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memcpy((void *)(uintptr_t)address, data, (size_t)len);
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return 0;
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}
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void RAMFUNCTION hal_flash_unlock(void)
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{
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}
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void RAMFUNCTION hal_flash_lock(void)
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{
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}
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int RAMFUNCTION hal_flash_erase(uint32_t address, int len)
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{
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if (!hal_addr_is_valid(address, len))
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return -1;
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memset((void *)(uintptr_t)address, FLASH_ERASED_BYTE, (size_t)len);
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return 0;
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}
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@ -0,0 +1,72 @@
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/* Linker script for wolfBoot on the i.MX95 Cortex-M7.
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*
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* Linked for the *core* view of TCM. The Linux remoteproc driver loads through
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* the system view (ITCM 0x203C0000, DTCM 0x20400000 at the default 256K/256K
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* TCM split) and imx_rproc translates between the two. Linking for the system
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* view produces an image that loads cleanly and faults on the first fetch.
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*
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* Sizes assume M7_CFG[TCM_SIZE] = 000b (256 KiB ITCM + 256 KiB DTCM), which is
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* the reset default. The System Manager on the M33 owns that field.
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*/
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MEMORY
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{
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ITCM (rx) : ORIGIN = 0x00000000, LENGTH = 256K
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DTCM (rwx) : ORIGIN = 0x20000000, LENGTH = 256K
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}
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SECTIONS
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{
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.text :
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{
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_start_text = .;
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KEEP(*(.isr_vector))
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. = ALIGN(8);
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*(.text*)
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*(.rodata*)
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*(.init*)
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*(.fini*)
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. = ALIGN(4);
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_end_text = .;
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} > ITCM
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/* Consumed by the remoteproc ELF loader. Not required to start the core,
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* but RPMsg needs it, so keep it even when empty. */
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.resource_table :
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{
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. = ALIGN(8);
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KEEP(*(.resource_table*))
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. = ALIGN(8);
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} > ITCM
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.edidx :
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{
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. = ALIGN(4);
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*(.ARM.exidx*)
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} > ITCM
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_stored_data = .;
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.data : AT (_stored_data)
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{
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_start_data = .;
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KEEP(*(.data*))
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. = ALIGN(4);
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_end_data = .;
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} > DTCM
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.bss (NOLOAD) :
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{
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_start_bss = .;
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__bss_start__ = .;
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*(.bss*)
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*(COMMON)
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. = ALIGN(4);
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_end_bss = .;
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__bss_end__ = .;
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_end = .;
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} > DTCM
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. = ALIGN(4);
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}
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END_STACK = ORIGIN(DTCM) + LENGTH(DTCM);
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@ -0,0 +1,106 @@
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/* uart_drv_imx95_m7.c
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*
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* Console for the Cortex-M7 on the NXP i.MX95.
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*
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* Copyright (C) 2026 wolfSSL Inc.
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*
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* This file is part of wolfBoot.
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*
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* wolfBoot is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 3 of the License, or
|
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* (at your option) any later version.
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*
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* wolfBoot is distributed in the hope that it will be useful,
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||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
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*/
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/* This is a shared-memory console, not a peripheral driver.
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*
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* The M7's LPUART is not routed to an accessible header on the Toradex SMARC
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* Development Board: markers written to /dev/ttyLP1..3 from Linux appear on no
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* host serial channel, and Linux owns all four LPUART instances anyway, so an
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* M7 writing to one would contend with it. Rather than depend on unproven pin
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* routing, the console is a ring buffer in the M7's own reserved DDR window,
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||||
* which the A55 cluster reads with the memtool helper.
|
||||
*
|
||||
* The buffer sits at the top of the M7's 16 MiB carveout (memory@80000000),
|
||||
* clear of the wolfBoot partitions lower down (BOOT 0x80100000, UPDATE
|
||||
* 0x80500000, SWAP 0x80900000). It deliberately does NOT use the RPMsg
|
||||
* vdevbuffer carveout, which belongs to the RPMsg transport.
|
||||
*
|
||||
* Reader contract: `wr` counts bytes ever written and never wraps within a run,
|
||||
* so a reader tracks its own position and copies (wr - pos) bytes from
|
||||
* data[pos % size]. Overrun is possible and expected for very chatty output;
|
||||
* the reader detects it when (wr - pos) > size and reports the gap rather than
|
||||
* silently printing corrupt text.
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#define CONSOLE_BASE 0x80F00000UL
|
||||
#define CONSOLE_MAGIC 0x4E4F4357UL /* "WCON" little-endian */
|
||||
#define CONSOLE_SIZE 0x10000UL /* 64 KiB of text */
|
||||
|
||||
struct console_hdr {
|
||||
volatile uint32_t magic;
|
||||
volatile uint32_t wr; /* total bytes written, monotonic */
|
||||
volatile uint32_t size; /* == CONSOLE_SIZE */
|
||||
volatile uint32_t rsvd;
|
||||
};
|
||||
|
||||
#define CONSOLE_HDR ((struct console_hdr *)CONSOLE_BASE)
|
||||
#define CONSOLE_DATA ((volatile uint8_t *)(CONSOLE_BASE + sizeof(struct console_hdr)))
|
||||
|
||||
int uart_init(uint32_t bitrate, uint8_t data, char parity, uint8_t stop)
|
||||
{
|
||||
struct console_hdr *h = CONSOLE_HDR;
|
||||
|
||||
(void)bitrate;
|
||||
(void)data;
|
||||
(void)parity;
|
||||
(void)stop;
|
||||
|
||||
h->wr = 0;
|
||||
h->size = CONSOLE_SIZE;
|
||||
/* Magic last: a reader that samples mid-init sees no valid console rather
|
||||
* than a valid magic with a stale size. */
|
||||
h->magic = CONSOLE_MAGIC;
|
||||
return 0;
|
||||
}
|
||||
|
||||
int uart_tx(const uint8_t c)
|
||||
{
|
||||
struct console_hdr *h = CONSOLE_HDR;
|
||||
uint32_t w;
|
||||
|
||||
if (h->magic != CONSOLE_MAGIC)
|
||||
(void)uart_init(0, 0, 'N', 0);
|
||||
|
||||
w = h->wr;
|
||||
CONSOLE_DATA[w % CONSOLE_SIZE] = c;
|
||||
/* Publish the byte before advancing the counter, so a reader never sees a
|
||||
* count covering a byte that has not been stored yet. */
|
||||
h->wr = w + 1;
|
||||
return 0;
|
||||
}
|
||||
|
||||
int uart_rx(uint8_t *c)
|
||||
{
|
||||
(void)c;
|
||||
return -1; /* console is write-only */
|
||||
}
|
||||
|
||||
void uart_write(const char *buf, unsigned int len)
|
||||
{
|
||||
unsigned int i;
|
||||
|
||||
for (i = 0; i < len; i++)
|
||||
(void)uart_tx((const uint8_t)buf[i]);
|
||||
}
|
||||
|
|
@ -0,0 +1,89 @@
|
|||
/* Linker script for the wolfBoot test app on the i.MX95 Cortex-M7.
|
||||
*
|
||||
* The generic ARM.ld is not usable here: it gives RAM only 16 KiB and defines
|
||||
* no heap symbols, and wolfCrypt's test/benchmark need both a real heap (RSA
|
||||
* and ECC key material) and syscalls.c's _sbrk, which references
|
||||
* _Min_Heap_Size.
|
||||
*
|
||||
* Code runs from the BOOT partition in the M7's reserved DDR window; data and
|
||||
* heap live in DTCM (core view 0x20000000, 256 KiB at the reset-default
|
||||
* M7_CFG[TCM_SIZE] split). Keeping the working set in TCM is the point of the
|
||||
* exercise -- these numbers are meant to characterise the real-time core, not
|
||||
* DDR latency.
|
||||
*/
|
||||
|
||||
_Min_Heap_Size = 0x00018000; /* 96 KiB - RSA/ECC test vectors and key structs */
|
||||
_Min_Stack_Size = 0x00008000; /* 32 KiB */
|
||||
|
||||
MEMORY
|
||||
{
|
||||
FLASH (rx) : ORIGIN = @WOLFBOOT_TEST_APP_ADDRESS@, LENGTH = @WOLFBOOT_TEST_APP_SIZE@
|
||||
RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 256K /* DTCM, core view */
|
||||
}
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
.text :
|
||||
{
|
||||
_start_text = .;
|
||||
KEEP(*(.isr_vector))
|
||||
*(.init)
|
||||
*(.fini)
|
||||
*(.text*)
|
||||
KEEP(*(.rodata*))
|
||||
. = ALIGN(4);
|
||||
_end_text = .;
|
||||
} > FLASH
|
||||
|
||||
.ARM :
|
||||
{
|
||||
__exidx_start = .;
|
||||
*(.ARM.exidx*)
|
||||
__exidx_end = .;
|
||||
} > FLASH
|
||||
|
||||
_stored_data = .;
|
||||
|
||||
.data : AT (_stored_data)
|
||||
{
|
||||
_start_data = .;
|
||||
KEEP(*(.data*))
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.ramcode))
|
||||
. = ALIGN(4);
|
||||
_end_data = .;
|
||||
} > RAM
|
||||
|
||||
.bss :
|
||||
{
|
||||
_start_bss = .;
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
_end_bss = .;
|
||||
_end = .;
|
||||
} > RAM
|
||||
|
||||
/* Reserve heap and stack explicitly so the link fails loudly if DTCM is
|
||||
* over-committed, rather than overflowing at run time. */
|
||||
.heap (NOLOAD) :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
PROVIDE ( _start_heap = . );
|
||||
. = . + _Min_Heap_Size;
|
||||
. = ALIGN(8);
|
||||
} > RAM
|
||||
|
||||
.stack (NOLOAD) :
|
||||
{
|
||||
. = . + _Min_Stack_Size;
|
||||
. = ALIGN(8);
|
||||
PROVIDE ( END_STACK = . );
|
||||
PROVIDE ( _end_stack = . );
|
||||
} > RAM
|
||||
}
|
||||
|
||||
_wolfboot_partition_boot_address = @WOLFBOOT_PARTITION_BOOT_ADDRESS@;
|
||||
_wolfboot_partition_size = @WOLFBOOT_PARTITION_SIZE@;
|
||||
_wolfboot_partition_update_address = @WOLFBOOT_PARTITION_UPDATE_ADDRESS@;
|
||||
_wolfboot_partition_swap_address = @WOLFBOOT_PARTITION_SWAP_ADDRESS@;
|
||||
|
|
@ -616,6 +616,16 @@ ifeq ($(TARGET),stm32l5)
|
|||
APP_OBJS+=../hal/uart/uart_drv_$(UART_TARGET).o
|
||||
endif
|
||||
|
||||
# i.MX95 Cortex-M7. The console is a shared-memory ring buffer rather than an
|
||||
# LPUART: no M7 UART is routed to a host-accessible channel on the Toradex SMARC
|
||||
# carrier, and Linux owns all four LPUART instances. -mcpu/-mfpu come from
|
||||
# arch.mk via CORTEX_M7.
|
||||
ifeq ($(TARGET),imx95_m7)
|
||||
CFLAGS+=-I..
|
||||
APP_OBJS+=../hal/uart/uart_drv_$(UART_TARGET).o
|
||||
LSCRIPT_TEMPLATE=ARM-imx95_m7.ld
|
||||
endif
|
||||
|
||||
ifeq ($(TARGET),stm32h5)
|
||||
ifeq ($(TZEN),1)
|
||||
LSCRIPT_TEMPLATE=ARM-stm32h5-ns.ld
|
||||
|
|
|
|||
|
|
@ -0,0 +1,113 @@
|
|||
/* app_imx95_m7.c
|
||||
*
|
||||
* Test application for the Cortex-M7 on the NXP i.MX95.
|
||||
*
|
||||
* Copyright (C) 2026 wolfSSL Inc.
|
||||
*
|
||||
* This file is part of wolfBoot.
|
||||
*
|
||||
* wolfBoot is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* wolfBoot is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
|
||||
*/
|
||||
|
||||
/* Output goes to the shared-memory console in hal/uart/uart_drv_imx95_m7.c,
|
||||
* because this part has no M7 UART routed to a host-accessible channel on the
|
||||
* Toradex SMARC carrier. wolfCrypt's test and benchmark call printf(), which
|
||||
* test-app/syscalls.c routes to uart_write(), so their output lands there too.
|
||||
*
|
||||
* Liveness markers stay in a shared status block so the demo's right pane can
|
||||
* poll them cheaply without parsing console text:
|
||||
*
|
||||
* devmem 0x80F10010 -> 0x41505031 ("APP1") once the app is running
|
||||
* devmem 0x80F10014 -> heartbeat, increments continuously
|
||||
*
|
||||
* wolfBoot writes its own progress codes at 0x80F10000, so a reader can tell
|
||||
* "bootloader ran" from "payload ran" with no peripheral wired up. The block
|
||||
* sits just above the console ring in the M7's DDR window, clear of the
|
||||
* RPMsg reservations at 0x88000000.
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include "wolfboot/wolfboot.h"
|
||||
|
||||
#if defined(WOLFCRYPT_TEST) || defined(WOLFCRYPT_BENCHMARK)
|
||||
#include <wolfssl/wolfcrypt/settings.h>
|
||||
#include <wolfssl/wolfcrypt/wc_port.h>
|
||||
#endif
|
||||
#ifdef WOLFCRYPT_TEST
|
||||
int wolfcrypt_test(void *args);
|
||||
#endif
|
||||
#ifdef WOLFCRYPT_BENCHMARK
|
||||
int benchmark_test(void *args);
|
||||
#endif
|
||||
|
||||
#define APP_STATUS_ADDR 0x80F10010UL
|
||||
#define APP_STATUS_MAGIC 0x41505031UL /* "APP1" */
|
||||
|
||||
extern int uart_init(uint32_t bitrate, uint8_t data, char parity, uint8_t stop);
|
||||
extern void uart_write(const char *buf, unsigned int len);
|
||||
|
||||
/* Local, so the banner works in builds that do not link ../src/string.o. */
|
||||
static void say(const char *s)
|
||||
{
|
||||
unsigned int n = 0;
|
||||
|
||||
while (s[n] != '\0')
|
||||
n++;
|
||||
uart_write(s, n);
|
||||
}
|
||||
|
||||
void main(void)
|
||||
{
|
||||
volatile uint32_t *status = (volatile uint32_t *)APP_STATUS_ADDR;
|
||||
uint32_t heartbeat = 0;
|
||||
/* remoteproc loads only PT_LOAD segments, and .bss is NOBITS - nothing
|
||||
* zeroes it before entry, so do it here before any static is read. */
|
||||
extern char _start_bss[], _end_bss[];
|
||||
char *p;
|
||||
|
||||
for (p = _start_bss; p < _end_bss; p++)
|
||||
*p = 0;
|
||||
|
||||
(void)uart_init(115200, 8, 'N', 1);
|
||||
|
||||
status[0] = APP_STATUS_MAGIC;
|
||||
status[1] = heartbeat;
|
||||
|
||||
say("\r\nwolfBoot test app: i.MX95 Cortex-M7\r\n");
|
||||
|
||||
#if defined(WOLFCRYPT_TEST) || defined(WOLFCRYPT_BENCHMARK)
|
||||
wolfCrypt_Init();
|
||||
#ifdef WOLFCRYPT_TEST
|
||||
say("\r\nRunning wolfCrypt tests...\r\n");
|
||||
wolfcrypt_test(NULL);
|
||||
say("Tests complete.\r\n");
|
||||
#endif
|
||||
#ifdef WOLFCRYPT_BENCHMARK
|
||||
say("\r\nRunning wolfCrypt benchmarks...\r\n");
|
||||
benchmark_test(NULL);
|
||||
say("Benchmarks complete.\r\n");
|
||||
#endif
|
||||
wolfCrypt_Cleanup();
|
||||
#endif
|
||||
|
||||
say("Idle.\r\n");
|
||||
|
||||
/* Confirm this image booted so wolfBoot does not roll it back. */
|
||||
wolfBoot_success();
|
||||
|
||||
while (1) {
|
||||
status[1] = ++heartbeat;
|
||||
}
|
||||
}
|
||||
|
|
@ -44,6 +44,47 @@
|
|||
extern volatile uint64_t HAL_time_ms;
|
||||
#elif defined(TARGET_lpc55s69)
|
||||
extern volatile uint64_t SysTick_time_ms;
|
||||
#elif defined(TARGET_imx95_m7)
|
||||
/* Cortex-M7 DWT cycle counter. Exact, free to read, and needs no
|
||||
* peripheral - which matters here because the M7 has no console UART
|
||||
* routed on this carrier. The core runs at 800 MHz (read from the board's
|
||||
* clk_summary: "m7 800000000"), not assumed. CYCCNT is 32-bit and wraps
|
||||
* every ~5.4 s at that rate, so accumulate into 64 bits on each read;
|
||||
* benchmark intervals are shorter than one wrap, so sampling on every call
|
||||
* is sufficient to catch it. */
|
||||
#define IMX95_M7_HZ 800000000ULL
|
||||
static uint64_t m7_cyc_hi = 0;
|
||||
static uint32_t m7_cyc_last = 0;
|
||||
static int m7_cyc_inited = 0;
|
||||
|
||||
static void m7_cyc_init(void);
|
||||
|
||||
static uint64_t m7_get_ticks(void)
|
||||
{
|
||||
uint32_t now;
|
||||
|
||||
if (!m7_cyc_inited) {
|
||||
m7_cyc_init();
|
||||
m7_cyc_inited = 1;
|
||||
}
|
||||
now = *(volatile uint32_t *)0xE0001004UL; /* DWT_CYCCNT */
|
||||
|
||||
if (now < m7_cyc_last)
|
||||
m7_cyc_hi += 0x100000000ULL; /* wrapped since last read */
|
||||
m7_cyc_last = now;
|
||||
return m7_cyc_hi + now;
|
||||
}
|
||||
|
||||
static void m7_cyc_init(void)
|
||||
{
|
||||
*(volatile uint32_t *)0xE000EDFCUL |= (1UL << 24); /* DEMCR.TRCENA */
|
||||
*(volatile uint32_t *)0xE0001004UL = 0; /* DWT_CYCCNT = 0 */
|
||||
*(volatile uint32_t *)0xE0001000UL |= 1UL; /* DWT_CTRL.CYCCNTENA */
|
||||
m7_cyc_hi = 0;
|
||||
m7_cyc_last = 0;
|
||||
}
|
||||
|
||||
static uint64_t m7_start_ticks = 0;
|
||||
#elif defined(TARGET_nxp_t2080) || defined(TARGET_nxp_t1024)
|
||||
/* PPC time base register for accurate timing (e6500). */
|
||||
static uint32_t ppc_tb_hz = 0;
|
||||
|
|
@ -147,6 +188,12 @@ unsigned long my_time(unsigned long* timer)
|
|||
unsigned long t = (unsigned long)(SysTick_time_ms / 1000);
|
||||
if (timer) *timer = t;
|
||||
return t;
|
||||
#elif defined(TARGET_imx95_m7)
|
||||
{
|
||||
unsigned long t = (unsigned long)(m7_get_ticks() / IMX95_M7_HZ);
|
||||
if (timer) *timer = t;
|
||||
return t;
|
||||
}
|
||||
#elif defined(TARGET_nxp_t2080) || defined(TARGET_nxp_t1024)
|
||||
if (ppc_tb_hz == 0)
|
||||
ppc_tb_hz = ppc_get_timebase_hz();
|
||||
|
|
@ -191,6 +238,13 @@ double current_time(int reset)
|
|||
#elif defined(TARGET_lpc55s69)
|
||||
(void)reset;
|
||||
return (double)SysTick_time_ms / 1000.0;
|
||||
#elif defined(TARGET_imx95_m7)
|
||||
if (reset) {
|
||||
m7_cyc_init();
|
||||
m7_cyc_inited = 1;
|
||||
m7_start_ticks = 0;
|
||||
}
|
||||
return (double)(m7_get_ticks() - m7_start_ticks) / (double)IMX95_M7_HZ;
|
||||
#elif defined(TARGET_nxp_t2080) || defined(TARGET_nxp_t1024)
|
||||
if (ppc_tb_hz == 0)
|
||||
ppc_tb_hz = ppc_get_timebase_hz();
|
||||
|
|
|
|||
Loading…
Reference in New Issue