From 80f881dab5560e5d8b9b9140f7a0bf34efac65a8 Mon Sep 17 00:00:00 2001 From: Daniele Lacamera Date: Mon, 23 Jan 2023 11:52:50 +0100 Subject: [PATCH] Fixed STM32L5 TRNG driver + simplified GTZC and SAU setup --- Makefile | 1 + hal/stm32l5.c | 158 +++++++++----- hal/stm32l5_ns.c | 2 - hal/stm32l5_partition.h | 443 ---------------------------------------- src/loader.c | 1 + test-app/app_stm32l5.c | 6 +- 6 files changed, 113 insertions(+), 498 deletions(-) delete mode 100644 hal/stm32l5_partition.h diff --git a/Makefile b/Makefile index db735cf7..bd39f5c8 100644 --- a/Makefile +++ b/Makefile @@ -139,6 +139,7 @@ wolfboot.bin: wolfboot.elf $(Q)$(SIZE) wolfboot.elf @echo + test-app/image.bin: wolfboot.elf $(Q)$(MAKE) -C test-app WOLFBOOT_ROOT="$(WOLFBOOT_ROOT)" $(Q)$(SIZE) test-app/image.elf diff --git a/hal/stm32l5.c b/hal/stm32l5.c index fe57d4e1..76913fdd 100644 --- a/hal/stm32l5.c +++ b/hal/stm32l5.c @@ -22,7 +22,6 @@ #include #include #include -#include "stm32l5_partition.h" /* Assembly helpers */ #define DMB() __asm__ volatile ("dmb") @@ -116,6 +115,9 @@ #define RCC_APB2ENR (*(volatile uint32_t *)(RCC_BASE + 0x60)) #define RCC_APB2ENR_SYSCFGEN (1 << 0) +#define RCC_CRRCR (*(volatile uint32_t *)(RCC_BASE + 0x98)) +#define RCC_CRRCR_HSI48ON (1 << 0) +#define RCC_CRRCR_HSI48RDY (1 << 1) /*** PWR ***/ /*!< Memory & Instance aliases and base addresses for Non-Secure/Secure peripherals */ @@ -241,12 +243,8 @@ #define TRNG_AHB2_CLOCK_ER (1 << 18) #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - -#define SCS_BASE (0xE000E000UL) -#define SCB_BASE (SCS_BASE + 0x0D00UL) -#define SCB_SHCSR (*(volatile uint32_t *)(SCB_BASE + 0x24)) +#define SCB_SHCSR (*(volatile uint32_t *)(0xE000ED24)) #define SCB_SHCSR_SECUREFAULT_EN (1<<19) - #endif static void RAMFUNCTION flash_set_waitstates(unsigned int waitstates) @@ -393,9 +391,6 @@ int RAMFUNCTION hal_flash_write(uint32_t address, const uint8_t *data, int len) return 0; } - - - void RAMFUNCTION hal_flash_unlock(void) { flash_wait_complete(0); @@ -409,8 +404,6 @@ void RAMFUNCTION hal_flash_unlock(void) } } - - void RAMFUNCTION hal_flash_lock(void) { flash_wait_complete(0); @@ -600,44 +593,90 @@ static void clock_pll_on(int powersave) DMB(); } + +static void hsi48_on(void) +{ + RCC_CRRCR |= RCC_CRRCR_HSI48ON; + while(RCC_CRRCR & RCC_CRRCR_HSI48RDY) + ; +} + +/* SAU registers, used to define memory mapped regions */ +#define SAU_CTRL (*(volatile uint32_t *)(0xE000EDD0)) +#define SAU_RNR (*(volatile uint32_t *)(0xE000EDD8)) /** SAU_RNR - region number register **/ +#define SAU_RBAR (*(volatile uint32_t *)(0xE000EDDC)) /** SAU_RBAR - region base address register **/ +#define SAU_RLAR (*(volatile uint32_t *)(0xE000EDE0)) /** SAU_RLAR - region limit address register **/ + +#define SAU_REGION_MASK 0x000000FF +#define SAU_ADDR_MASK 0xFFFFFFE0 /* LS 5 bit are reserved or used for flags */ + +/* Flag for the SAU region limit register */ +#define SAU_REG_ENABLE (1 << 0) /* Indicates that the region is enabled. */ +#define SAU_REG_SECURE (1 << 1) /* When on, the region is S or NSC */ + +#define SAU_INIT_CTRL_ENABLE (1 << 0) +#define SAU_INIT_CTRL_ALLNS (1 << 1) + +static void sau_init_region(uint32_t region, uint32_t start_addr, + uint32_t end_addr, int secure) +{ + uint32_t secure_flag = 0; + if (secure) + secure_flag = SAU_REG_SECURE; + SAU_RNR = region & SAU_REGION_MASK; + SAU_RBAR = start_addr & SAU_ADDR_MASK; + SAU_RLAR = (end_addr & SAU_ADDR_MASK) + | secure_flag | SAU_REG_ENABLE; +} + + +static void tz_sau_init(void) +{ + /* Non-secure callable: NSC functions area */ + sau_init_region(0, 0x0C020000, 0x0C040000, 1); + + /* Non-secure: application flash area */ + sau_init_region(1, 0x08040000, 0x0804FFFF, 0); + + /* Non-secure RAM region in SRAM1 */ + sau_init_region(2, 0x20018000, 0x2002FFFF, 0); + + /* Non-secure: internal peripherals */ + sau_init_region(3, 0x40000000, 0x4FFFFFFF, 0); + + /* Enable SAU */ + SAU_CTRL = SAU_INIT_CTRL_ENABLE; + + /* Enable securefault handler */ + SCB_SHCSR |= SCB_SHCSR_SECUREFAULT_EN; + +} + +#define GTZC_MPCBB1_S_BASE (0x50032C00) +#define GTZC_MPCBB1_S_VCTR_BASE (GTZC_MPCBB1_S_BASE + 0x100) + +#define GTZC_MPCBB2_S_BASE (0x50033000) +#define GTZC_MPCBB2_S_VCTR_BASE (GTZC_MPCBB2_S_BASE + 0x100) + +#define SET_GTZC_MPCBBx_S_VCTR(bank,n,val) \ + (*((volatile uint32_t *)(GTZC_MPCBB##bank##_S_VCTR_BASE ) + n ))= val + static void gtzc_init(void) { - /*configure SRAM1 */ - SET_GTZC_MPCBBx_S_VCTR(1,0); - SET_GTZC_MPCBBx_S_VCTR(1,1); - SET_GTZC_MPCBBx_S_VCTR(1,2); - SET_GTZC_MPCBBx_S_VCTR(1,3); - SET_GTZC_MPCBBx_S_VCTR(1,4); - SET_GTZC_MPCBBx_S_VCTR(1,5); - SET_GTZC_MPCBBx_S_VCTR(1,6); - SET_GTZC_MPCBBx_S_VCTR(1,7); - SET_GTZC_MPCBBx_S_VCTR(1,8); - SET_GTZC_MPCBBx_S_VCTR(1,9); - SET_GTZC_MPCBBx_S_VCTR(1,10); - SET_GTZC_MPCBBx_S_VCTR(1,11); - SET_GTZC_MPCBBx_S_VCTR(1,12); - SET_GTZC_MPCBBx_S_VCTR(1,13); - SET_GTZC_MPCBBx_S_VCTR(1,14); - SET_GTZC_MPCBBx_S_VCTR(1,15); - SET_GTZC_MPCBBx_S_VCTR(1,16); - SET_GTZC_MPCBBx_S_VCTR(1,17); - SET_GTZC_MPCBBx_S_VCTR(1,18); - SET_GTZC_MPCBBx_S_VCTR(1,19); - SET_GTZC_MPCBBx_S_VCTR(1,20); - SET_GTZC_MPCBBx_S_VCTR(1,21); - SET_GTZC_MPCBBx_S_VCTR(1,22); - SET_GTZC_MPCBBx_S_VCTR(1,23); - - /*configure SRAM2 */ - SET_GTZC_MPCBBx_S_VCTR(2,0); - SET_GTZC_MPCBBx_S_VCTR(2,1); - SET_GTZC_MPCBBx_S_VCTR(2,2); - SET_GTZC_MPCBBx_S_VCTR(2,3); - SET_GTZC_MPCBBx_S_VCTR(2,4); - SET_GTZC_MPCBBx_S_VCTR(2,5); - SET_GTZC_MPCBBx_S_VCTR(2,6); - SET_GTZC_MPCBBx_S_VCTR(2,7); + int i; + /* Configure lower half of SRAM1 as secure */ + for (i = 0; i < 12; i++) { + SET_GTZC_MPCBBx_S_VCTR(1, i, 0xFFFFFFFF); + } + /* Configure upper half of SRAM1 as non-secure */ + for (i = 12; i < 24; i++) { + SET_GTZC_MPCBBx_S_VCTR(1, i, 0x0); + } + /* Configure SRAM2 as secure */ + for (i = 0; i < 8; i++) { + SET_GTZC_MPCBBx_S_VCTR(2, i, 0xFFFFFFFF); + } } @@ -707,18 +746,19 @@ static void RAMFUNCTION fork_bootloader(void) void hal_init(void) { - TZ_SAU_Setup(); + #if defined(DUALBANK_SWAP) && defined(__WOLFBOOT) if ((FLASH_OPTR & (FLASH_OPTR_SWAP_BANK | FLASH_OPTR_DBANK)) == FLASH_OPTR_DBANK) fork_bootloader(); #endif - clock_pll_on(0); #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /* Enable SecureFault handler (HardFault is default) */ SCB_SHCSR |= SCB_SHCSR_SECUREFAULT_EN; + tz_sau_init(); gtzc_init(); #endif + clock_pll_on(0); } @@ -739,11 +779,31 @@ void hal_prepare_boot(void) #define TRNG_SR_DRDY (1 << 0) #define TRNG_CR_RNGEN (1 << 2) +#define TRNG_CR_CONFIG3_SHIFT (8) +#define TRNG_CR_CONFIG2_SHIFT (13) +#define TRNG_CR_CLKDIV_SHIFT (16) +#define TRNG_CR_CONFIG1_SHIFT (20) +#define TRNG_CR_CONDRST (1 << 30) + void hal_trng_init(void) { + uint32_t reg_val; + hsi48_on(); RCC_AHB2_CLOCK_ER |= TRNG_AHB2_CLOCK_ER; - TRNG_CR |= TRNG_CR_RNGEN; + + reg_val = TRNG_CR; + reg_val &= ~(0x1F << TRNG_CR_CONFIG1_SHIFT); + reg_val &= ~(0x7 << TRNG_CR_CLKDIV_SHIFT); + reg_val &= ~(0x3 << TRNG_CR_CONFIG2_SHIFT); + reg_val &= ~(0x7 << TRNG_CR_CONFIG3_SHIFT); + + reg_val |= 0x0F << TRNG_CR_CONFIG1_SHIFT; + reg_val |= 0x0D << TRNG_CR_CONFIG3_SHIFT; + TRNG_CR = TRNG_CR_CONDRST | reg_val; + while ((TRNG_CR & TRNG_CR_CONDRST) == 0) + ; + TRNG_CR = reg_val | TRNG_CR_RNGEN; while ((TRNG_SR & TRNG_SR_DRDY) == 0) ; } diff --git a/hal/stm32l5_ns.c b/hal/stm32l5_ns.c index 95ea720e..34e639bd 100644 --- a/hal/stm32l5_ns.c +++ b/hal/stm32l5_ns.c @@ -21,8 +21,6 @@ #include #include -#include "stm32l5_partition.h" - /* Assembly helpers */ #define DMB() __asm__ volatile ("dmb") #define ISB() __asm__ volatile ("isb") diff --git a/hal/stm32l5_partition.h b/hal/stm32l5_partition.h deleted file mode 100644 index 8bbe6068..00000000 --- a/hal/stm32l5_partition.h +++ /dev/null @@ -1,443 +0,0 @@ -/* stm32l5_partition.h - * - * Copyright (C) 2021 wolfSSL Inc. - * - * This file is part of wolfBoot. - * - * wolfBoot is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * wolfBoot is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA - */ - -#ifndef STM32L5_PARTITION_H -#define STM32L5_PARTITION_H - -#define SCS_BASE (0xE000E000UL) -#define SCB_BASE (SCS_BASE + 0x0D00UL) -#define SAU_BASE (SCS_BASE + 0x0DD0UL) -#define FPU_BASE (SCS_BASE + 0x0F30UL) -#define NVIC_BASE (SCS_BASE + 0x0100UL) - -#define SAU_CTRL (*(volatile uint32_t *)(SAU_BASE + 0x00)) -#define SAU_RNR (*(volatile uint32_t *)(SAU_BASE + 0x08)) -#define SAU_RBAR (*(volatile uint32_t *)(SAU_BASE + 0x0C)) -#define SAU_RLAR (*(volatile uint32_t *)(SAU_BASE + 0x10)) -#define SCB_NSACR (*(volatile uint32_t *)(SCB_BASE + 0x8C)) -#define FPU_FPCCR (*(volatile uint32_t *)(FPU_BASE + 0x04)) - -/* SAU Control Register Definitions */ -#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ -#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ - -#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ -#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ - -/* SAU Type Register Definitions */ -#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ -#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ - -/* SAU Region Number Register Definitions */ -#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ -#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ - -/* SAU Region Base Address Register Definitions */ -#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ -#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ - -/* SAU Region Limit Address Register Definitions */ -#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ -#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ - -#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ -#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ - -#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ -#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ - -/* SCB Non-Secure Access Control Register Definitions */ -#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ -#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ - -#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ -#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ - -#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ -#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) - -#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ -#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ - -#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ -#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ - -#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ -#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) - -/* -// Enable SAU -// Value for SAU_CTRL register bit ENABLE -*/ -#define SAU_INIT_CTRL_ENABLE 1 - -/* -// When SAU is disabled -// <0=> All Memory is Secure -// <1=> All Memory is Non-Secure -// Value for SAU_CTRL register bit ALLNS -// When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration. -*/ -#define SAU_INIT_CTRL_ALLNS 0 - -/* -// Initialize Security Attribution Unit (SAU) Address Regions -// SAU configuration specifies regions to be one of: -// - Secure and Non-Secure Callable -// - Non-Secure -// Note: All memory regions not configured by SAU are Secure -*/ -#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */ - -/* -// Initialize SAU Region 0 -// Setup SAU Region 0 memory attributes -*/ -#define SAU_INIT_REGION0 1 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START0 0x0C03E000 /* start address of SAU region 0 */ - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END0 0x0C03FFFF /* end address of SAU region 0 */ - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC0 1 - -/* -// Initialize SAU Region 1 -// Setup SAU Region 1 memory attributes -*/ -#define SAU_INIT_REGION1 1 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START1 0x08040000 /* start address of SAU region 1 */ -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END1 0x0807FFFF /* end address of SAU region 1 */ -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC1 0 - -/* -// Initialize SAU Region 2 -// Setup SAU Region 2 memory attributes -*/ -#define SAU_INIT_REGION2 1 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START2 0x20018000 /* start address of SAU region 2 */ - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END2 0x2003FFFF /* end address of SAU region 2 */ - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC2 0 - -/* -// Initialize SAU Region 3 -// Setup SAU Region 3 memory attributes -*/ -#define SAU_INIT_REGION3 1 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START3 0x40000000 /* start address of SAU region 3 */ - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END3 0x4FFFFFFF /* end address of SAU region 3 */ - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC3 0 - -/* -// Initialize SAU Region 4 -// Setup SAU Region 4 memory attributes -*/ -#define SAU_INIT_REGION4 1 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START4 0x60000000 /* start address of SAU region 4 */ - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END4 0x9FFFFFFF /* end address of SAU region 4 */ - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC4 0 - -/* -// Initialize SAU Region 5 -// Setup SAU Region 5 memory attributes -*/ -#define SAU_INIT_REGION5 1 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START5 0x0BF90000 /* start address of SAU region 5 */ - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END5 0x0BFA8FFF /* end address of SAU region 5 */ - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC5 0 - -/* -// Initialize SAU Region 6 -// Setup SAU Region 6 memory attributes -*/ -#define SAU_INIT_REGION6 0 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START6 0x00000000 /* start address of SAU region 6 */ - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END6 0x00000000 /* end address of SAU region 6 */ - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC6 0 - -/* -// Initialize SAU Region 7 -// Setup SAU Region 7 memory attributes -*/ -#define SAU_INIT_REGION7 0 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START7 0x00000000 /* start address of SAU region 7 */ - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END7 0x00000000 /* end address of SAU region 7 */ - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC7 0 - -// Setup behaviour of Floating Point Unit - -#define TZ_FPU_NS_USAGE 1 - -/* -// Floating Point Unit usage -// <0=> Secure state only -// <3=> Secure and Non-Secure state -// Value for SCB_NSACR register bits CP10, CP11 -*/ -#define SCB_NSACR_CP10_11_VAL 3 - -/* -// Treat floating-point registers as Secure -// <0=> Disabled -// <1=> Enabled -// Value for FPU_FPCCR register bit TS -*/ -#define FPU_FPCCR_TS_VAL 0 - -/* -// Clear on return (CLRONRET) accessibility -// <0=> Secure and Non-Secure state -// <1=> Secure state only -// Value for FPU_FPCCR register bit CLRONRETS -*/ -#define FPU_FPCCR_CLRONRETS_VAL 0 - -/* -// Clear floating-point caller saved registers on exception return -// <0=> Disabled -// <1=> Enabled -// Value for FPU_FPCCR register bit CLRONRET -*/ -#define FPU_FPCCR_CLRONRET_VAL 1 - - -#define SAU_INIT_REGION(n) \ - SAU_RNR = (n & SAU_RNR_REGION_Msk); \ - SAU_RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \ - SAU_RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \ - ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U - - -#define GTZC_MPCBB1_S_BASE (0x50032C00) -#define GTZC_MPCBB1_S_CR (*(volatile uint32_t *)(GTZC_MPCBB1_S_BASE + 0x00)) -#define GTZC_MPCBB1_S_LCKVTR1 (*(volatile uint32_t *)(GTZC_MPCBB1_S_BASE + 0x10)) -#define GTZC_MPCBB1_S_LCKVTR2 (*(volatile uint32_t *)(GTZC_MPCBB1_S_BASE + 0x14)) -#define GTZC_MPCBB1_S_VCTR_BASE (GTZC_MPCBB1_S_BASE + 0x100) - -#define GTZC_MPCBB2_S_BASE (0x50033000) -#define GTZC_MPCBB2_S_CR (*(volatile uint32_t *)(GTZC_MPCBB2_S_BASE + 0x00)) -#define GTZC_MPCBB2_S_LCKVTR1 (*(volatile uint32_t *)(GTZC_MPCBB2_S_BASE + 0x10)) -#define GTZC_MPCBB2_S_LCKVTR2 (*(volatile uint32_t *)(GTZC_MPCBB2_S_BASE + 0x14)) -#define GTZC_MPCBB2_S_VCTR_BASE (GTZC_MPCBB2_S_BASE + 0x100) - -#define SET_GTZC_MPCBBx_S_VCTR(x,n) \ - (*((volatile uint32_t *)(GTZC_MPCBB##x##_S_VCTR_BASE ) + n ))= GTZC_MPCBB##x##_S_VCTR##n##_VAL - -/*SRAM1*/ -#define GTZC_MPCBB1_S_VCTR0_VAL (0xFFFFFFFF) -#define GTZC_MPCBB1_S_VCTR1_VAL (0xFFFFFFFF) -#define GTZC_MPCBB1_S_VCTR2_VAL (0xFFFFFFFF) -#define GTZC_MPCBB1_S_VCTR3_VAL (0xFFFFFFFF) -#define GTZC_MPCBB1_S_VCTR4_VAL (0xFFFFFFFF) -#define GTZC_MPCBB1_S_VCTR5_VAL (0xFFFFFFFF) -#define GTZC_MPCBB1_S_VCTR6_VAL (0xFFFFFFFF) -#define GTZC_MPCBB1_S_VCTR7_VAL (0xFFFFFFFF) -#define GTZC_MPCBB1_S_VCTR8_VAL (0xFFFFFFFF) -#define GTZC_MPCBB1_S_VCTR9_VAL (0xFFFFFFFF) -#define GTZC_MPCBB1_S_VCTR10_VAL (0xFFFFFFFF) -#define GTZC_MPCBB1_S_VCTR11_VAL (0xFFFFFFFF) -#define GTZC_MPCBB1_S_VCTR12_VAL (0xFFFFFFFF) -#define GTZC_MPCBB1_S_VCTR13_VAL (0x00000000) -#define GTZC_MPCBB1_S_VCTR14_VAL (0x00000000) -#define GTZC_MPCBB1_S_VCTR15_VAL (0x00000000) -#define GTZC_MPCBB1_S_VCTR16_VAL (0x00000000) -#define GTZC_MPCBB1_S_VCTR17_VAL (0x00000000) -#define GTZC_MPCBB1_S_VCTR18_VAL (0x00000000) -#define GTZC_MPCBB1_S_VCTR19_VAL (0x00000000) -#define GTZC_MPCBB1_S_VCTR20_VAL (0x00000000) -#define GTZC_MPCBB1_S_VCTR21_VAL (0x00000000) -#define GTZC_MPCBB1_S_VCTR22_VAL (0x00000000) -#define GTZC_MPCBB1_S_VCTR23_VAL (0x00000000) - -/*SRAM2*/ -#define GTZC_MPCBB2_S_VCTR0_VAL (0x00000000) -#define GTZC_MPCBB2_S_VCTR1_VAL (0x00000000) -#define GTZC_MPCBB2_S_VCTR2_VAL (0x00000000) -#define GTZC_MPCBB2_S_VCTR3_VAL (0x00000000) -#define GTZC_MPCBB2_S_VCTR4_VAL (0x00000000) -#define GTZC_MPCBB2_S_VCTR5_VAL (0x00000000) -#define GTZC_MPCBB2_S_VCTR6_VAL (0x00000000) -#define GTZC_MPCBB2_S_VCTR7_VAL (0x00000000) - -/** - \brief Setup a SAU Region - \details Writes the region information contained in SAU_Region to the - registers SAU_RNR, SAU_RBAR, and SAU_RLAR - */ -static __inline void TZ_SAU_Setup (void) -{ - - #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U) - SAU_INIT_REGION(0); - #endif - - #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U) - SAU_INIT_REGION(1); - #endif - - #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U) - SAU_INIT_REGION(2); - #endif - - #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U) - SAU_INIT_REGION(3); - #endif - - #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U) - SAU_INIT_REGION(4); - #endif - - #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U) - SAU_INIT_REGION(5); - #endif - - #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U) - SAU_INIT_REGION(6); - #endif - - #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U) - SAU_INIT_REGION(7); - #endif - - SAU_CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) | - ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ; - - #if defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U) - - SCB_NSACR = (SCB_NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) | - ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)); - - FPU_FPCCR = (FPU_FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) | - ((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) | - ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) | - ((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk ); - #endif - -} - -#endif /* STM32L5_PARTITION_H */ diff --git a/src/loader.c b/src/loader.c index 502c8924..8bd8026b 100644 --- a/src/loader.c +++ b/src/loader.c @@ -113,6 +113,7 @@ int main(void) #endif wolfBoot_start(); + /* wolfBoot_start should never return. */ wolfBoot_panic(); diff --git a/test-app/app_stm32l5.c b/test-app/app_stm32l5.c index 2aa9fe60..a611f97b 100644 --- a/test-app/app_stm32l5.c +++ b/test-app/app_stm32l5.c @@ -28,6 +28,7 @@ #include "system.h" #include "hal.h" #include "wolfboot/wolfboot.h" +#include "wolfboot/wc_secure.h" #define LED_BOOT_PIN (12) //PG12 - Discovery - Green Led #define LED_USR_PIN (3) //PD3 - Discovery - Red Led @@ -54,9 +55,6 @@ #define PWR_CR2 (*(volatile uint32_t *)(PWR_BASE + 0x04)) #define PWR_CR2_IOSV (1 << 9) -int wcs_get_random(unsigned char *rand, - uint32_t size); - static void boot_led_on(void) { uint32_t reg; @@ -104,7 +102,7 @@ void main(void) uint32_t rand; uint32_t i; wcs_get_random((void*)&rand, 4); - for (i = 0; i < rand; i++) + for (i = 0; i < (rand / 100000000); i++) ; #endif