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Added RT1062 EVKB support and tested on real hardware. Updated documentation.

pull/464/head
David Garske 2024-07-03 14:58:04 -07:00
parent de9a3cd0bf
commit 83359a2b1e
6 changed files with 74 additions and 46 deletions
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5
arch.mk
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@ -434,6 +434,11 @@ ifeq ($(TARGET),imx_rt)
CFLAGS+=-I$(MCUXPRESSO)/boards/evkmimxrt1060/xip/ CFLAGS+=-I$(MCUXPRESSO)/boards/evkmimxrt1060/xip/
endif endif
ifeq ($(MCUXPRESSO_CPU),MIMXRT1062DVL6B)
ARCH_FLASH_OFFSET=0x60000000
CFLAGS+=-I$(MCUXPRESSO)/boards/evkbmimxrt1060/xip/
endif
ifeq ($(MCUXPRESSO_CPU),MIMXRT1061CVJ5B) ifeq ($(MCUXPRESSO_CPU),MIMXRT1061CVJ5B)
ARCH_FLASH_OFFSET=0x60000000 ARCH_FLASH_OFFSET=0x60000000
CFLAGS+=-I$(MCUXPRESSO)/boards/evkmimxrt1060/xip/ CFLAGS+=-I$(MCUXPRESSO)/boards/evkmimxrt1060/xip/

69
docs/Targets.md
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@ -1379,15 +1379,19 @@ wolfBoot support for iMX-RT1060/iMX-RT1050 has been tested using MCUXpresso SDK
DCP support (hardware acceleration for SHA256 operations) can be enabled by using PKA=1 in the configuration file. DCP support (hardware acceleration for SHA256 operations) can be enabled by using PKA=1 in the configuration file.
Firmware can be directly uploaded to the target by copying `factory.bin` to the virtual USB drive associated to the device, or by loading the image directly into flash using a JTAG/SWD debugger.
The RT1050 EVKB board comes wired to use the 64MB HyperFlash. If you'd like to use QSPI there is a rework that can be performed (see AN12183). The default onboard QSPI 8MB ISSI IS25WP064A (`CONFIG_FLASH_IS25WP064A`). To use a 64Mbit Winbond W25Q64JV define `CONFIG_FLASH_W25Q64JV` (16Mbit, 32Mbit, 128Mbit, 256Mbit and 512Mbit versions are also available). These options are also available for the RT1042 and RT1061 target.
You can also get the SDK and CMSIS bundles using these repositories: You can also get the SDK and CMSIS bundles using these repositories:
* https://github.com/nxp-mcuxpresso/mcux-sdk * https://github.com/nxp-mcuxpresso/mcux-sdk
* https://github.com/nxp-mcuxpresso/CMSIS_5 * https://github.com/nxp-mcuxpresso/CMSIS_5
Use MCUXSDK=1 with this option, since the pack paths are different. Use MCUXSDK=1 with this option, since the pack paths are different.
Example:
```
MCUXSDK?=1
MCUXPRESSO?=$(PWD)/../mcux-sdk
MCUXPRESSO_DRIVERS?=$(MCUXPRESSO)/devices/MIMXRT1062
MCUXPRESSO_CMSIS?="$(PWD)/../CMSIS_5/CMSIS"
```
### Custom Device Configuration Data (DCD) ### Custom Device Configuration Data (DCD)
On iMX-RT10xx it is possible to load a custom DCD section from an external On iMX-RT10xx it is possible to load a custom DCD section from an external
@ -1401,58 +1405,61 @@ section, e.g.:
If an external `.dcd_data` section is provided, the option `NXP_CUSTOM_DCD=1` must If an external `.dcd_data` section is provided, the option `NXP_CUSTOM_DCD=1` must
be added to the configuration. be added to the configuration.
### Flashing
### Testing Update Firmware can be directly uploaded to the target by copying `factory.bin` to the virtual USB drive associated to the device, or by loading the image directly into flash using a JTAG/SWD debugger.
First make the update partition, pre-triggered for update The RT1050 EVKB board comes wired to use the 64MB HyperFlash. If you'd like to use QSPI there is a rework that can be performed (see AN12183). The default onboard QSPI 8MB ISSI IS25WP064A (`CONFIG_FLASH_IS25WP064A`). To use a 64Mbit Winbond W25Q64JV define `CONFIG_FLASH_W25Q64JV` (16Mbit, 32Mbit, 128Mbit, 256Mbit and 512Mbit versions are also available). These options are also available for the RT1042 and RT1061 target.
```sh If you have updated the MCULink to use JLink then you can connect to the board with JLinkExe using one of the following commands:
tools/scripts/prepare_update.sh
```
Then connect to the board with JLinkExe, for the rt1040 do:
```sh ```sh
# HyperFlash # HyperFlash
JLinkExe -if swd -speed 5000 -Device "MIMXRT1042xxxxB" JLinkExe -if swd -speed 5000 -Device "MIMXRT1042xxxxB"
# QSPI
JLinkExe -if swd -speed 5000 -Device "MIMXRT1042xxxxB?BankAddr=0x60000000&Loader=QSPI"
```
For the rt1050 do:
```sh
# HyperFlash
JLinkExe -if swd -speed 5000 -Device "MIMXRT1052XXX6A" JLinkExe -if swd -speed 5000 -Device "MIMXRT1052XXX6A"
# QSPI
JLinkExe -if swd -speed 5000 -Device "MIMXRT1052XXX6A?BankAddr=0x60000000&Loader=QSPI"
```
For the rt-1060:
```sh
# HyperFlash
JLinkExe -if swd -speed 5000 -Device "MIMXRT1062XXX6B" JLinkExe -if swd -speed 5000 -Device "MIMXRT1062XXX6B"
# QSPI # QSPI
JLinkExe -if swd -speed 5000 -Device "MIMXRT1042xxxxB?BankAddr=0x60000000&Loader=QSPI"
JLinkExe -if swd -speed 5000 -Device "MIMXRT1052XXX6A?BankAddr=0x60000000&Loader=QSPI"
JLinkExe -if swd -speed 5000 -Device "MIMXRT1062XXX6B?BankAddr=0x60000000&Loader=QSPI" JLinkExe -if swd -speed 5000 -Device "MIMXRT1062XXX6B?BankAddr=0x60000000&Loader=QSPI"
``` ```
Now flash the board: Flash using:
```sh ```sh
loadbin factory.bin 0x60000000 loadbin factory.bin 0x60000000
```
### Testing Update
First make the update partition, pre-triggered for update:
```sh
./tools/scripts/prepare_update.sh
```
Run the "loadbin" commands to flash the update:
```sh
loadbin update.bin 0x60030000 loadbin update.bin 0x60030000
``` ```
Reboot device. Expected output:
```
wolfBoot Test app, version = 1
wolfBoot Test app, version = 8
```
### NXP iMX-RT Debugging JTAG / JLINK ### NXP iMX-RT Debugging JTAG / JLINK
```sh ```sh
# rt-1040 # Start JLink GDB server for your device
JLinkGDBServer -Device MIMXRT1042xxxxB -speed 5000 -if swd -port 3333 JLinkGDBServer -Device MIMXRT1042xxxxB -speed 5000 -if swd -port 3333
# rt-1050
JLinkGDBServer -Device MIMXRT1052xxx6A -speed 5000 -if swd -port 3333 JLinkGDBServer -Device MIMXRT1052xxx6A -speed 5000 -if swd -port 3333
# rt-1060
JLinkGDBServer -Device MIMXRT1062xxx6B -speed 5000 -if swd -port 3333 JLinkGDBServer -Device MIMXRT1062xxx6B -speed 5000 -if swd -port 3333
# From wolfBoot directory
arm-none-eabi-gdb arm-none-eabi-gdb
add-symbol-file test-app/image.elf 0x60010100 add-symbol-file test-app/image.elf 0x60010100
mon reset init mon reset init

15
hal/imx_rt.c
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@ -43,6 +43,10 @@
#include "evkmimxrt1060_flexspi_nor_config.h" #include "evkmimxrt1060_flexspi_nor_config.h"
#define USE_GET_CONFIG #define USE_GET_CONFIG
#endif #endif
#ifdef CPU_MIMXRT1062DVL6B
#include "evkbmimxrt1060_flexspi_nor_config.h"
#define USE_GET_CONFIG
#endif
#ifdef CPU_MIMXRT1061CVJ5B #ifdef CPU_MIMXRT1061CVJ5B
#include "evkmimxrt1060_flexspi_nor_config.h" #include "evkmimxrt1060_flexspi_nor_config.h"
#endif #endif
@ -262,7 +266,7 @@ const flexspi_nor_config_t FLASH_CONFIG_SECTION qspiflash_config = {
/** Flash configuration in the .flash_config section of flash **/ /** Flash configuration in the .flash_config section of flash **/
#ifdef CPU_MIMXRT1062DVL6A #if defined(CPU_MIMXRT1062DVL6A) || defined(CPU_MIMXRT1062DVL6B)
#define CONFIG_FLASH_SIZE (8 * 1024 * 1024) /* 8MBytes */ #define CONFIG_FLASH_SIZE (8 * 1024 * 1024) /* 8MBytes */
#define CONFIG_FLASH_PAGE_SIZE 256UL /* 256Bytes */ #define CONFIG_FLASH_PAGE_SIZE 256UL /* 256Bytes */
#define CONFIG_FLASH_SECTOR_SIZE (4 * 1024) /* 4KBytes */ #define CONFIG_FLASH_SECTOR_SIZE (4 * 1024) /* 4KBytes */
@ -590,7 +594,10 @@ const flexspi_nor_config_t FLASH_CONFIG_SECTION qspiflash_config = {
#ifndef __FLASH_BASE #ifndef __FLASH_BASE
#if defined(CPU_MIMXRT1062DVL6A) || defined(CPU_MIMXRT1061CVJ5B) || defined(CPU_MIMXRT1052DVJ6B) || defined(CPU_MIMXRT1042XJM5B) #if defined(CPU_MIMXRT1062DVL6A) || defined(CPU_MIMXRT1062DVL6B) || \
defined(CPU_MIMXRT1061CVJ5B) || \
defined(CPU_MIMXRT1052DVJ6B) || \
defined(CPU_MIMXRT1042XJM5B)
#define __FLASH_BASE 0x60000000 #define __FLASH_BASE 0x60000000
#elif defined(CPU_MIMXRT1064DVL6A) #elif defined(CPU_MIMXRT1064DVL6A)
#define __FLASH_BASE 0x70000000 #define __FLASH_BASE 0x70000000
@ -709,7 +716,9 @@ static void clock_init(void)
CCM_CBCDR_AHB_PODF(2) | CCM_CBCDR_AHB_PODF(2) |
CCM_CBCDR_IPG_PODF(2); CCM_CBCDR_IPG_PODF(2);
#if defined(CPU_MIMXRT1064DVL6A) || defined(CPU_MIMXRT1062DVL6A) || defined(CPU_MIMXRT1061CVJ5B) #if defined(CPU_MIMXRT1064DVL6A) || \
defined(CPU_MIMXRT1062DVL6A) || defined(CPU_MIMXRT1062DVL6B) || \
defined(CPU_MIMXRT1061CVJ5B)
/* Configure FLEXSPI2 CLOCKS */ /* Configure FLEXSPI2 CLOCKS */
CCM->CBCMR = CCM->CBCMR =
(CCM->CBCMR & (CCM->CBCMR &

5
test-app/Makefile
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@ -295,6 +295,11 @@ ifeq ($(TARGET),imx_rt)
-I$(MCUXPRESSO)/boards/evkmimxrt1060/xip/ -I$(MCUXPRESSO)/boards/evkmimxrt1060/xip/
APP_OBJS+=$(MCUXPRESSO_DRIVERS)/system_MIMXRT1062.o APP_OBJS+=$(MCUXPRESSO_DRIVERS)/system_MIMXRT1062.o
endif endif
ifeq ($(MCUXPRESSO_CPU),MIMXRT1062DVL6B)
CFLAGS+=-I$(MCUXPRESSO_DRIVERS)/project_template/ \
-I$(MCUXPRESSO)/boards/evkbmimxrt1060/xip/
APP_OBJS+=$(MCUXPRESSO_DRIVERS)/system_MIMXRT1062.o
endif
ifeq ($(MCUXPRESSO_CPU),MIMXRT1064DVL6A) ifeq ($(MCUXPRESSO_CPU),MIMXRT1064DVL6A)
CFLAGS+=-I$(MCUXPRESSO_DRIVERS)/project_template/ \ CFLAGS+=-I$(MCUXPRESSO_DRIVERS)/project_template/ \
-I$(MCUXPRESSO)/boards/evkmimxrt1064/xip/ -I$(MCUXPRESSO)/boards/evkmimxrt1064/xip/

6
test-app/app_imx_rt.c
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@ -64,7 +64,8 @@ void init_debug_console(void)
DbgConsole_Init(UART_INSTANCE, UART_BAUDRATE, UART_TYPE, uartClkSrcFreq); DbgConsole_Init(UART_INSTANCE, UART_BAUDRATE, UART_TYPE, uartClkSrcFreq);
} }
#if defined(CPU_MIMXRT1062DVL6A) || defined(CPU_MIMXRT1064DVL6A) #if defined(CPU_MIMXRT1064DVL6A) || \
defined(CPU_MIMXRT1062DVL6A) || defined(CPU_MIMXRT1062DVL6B)
/* Pin settings (same for both 1062 and 1064) */ /* Pin settings (same for both 1062 and 1064) */
void rt1060_init_pins(void) void rt1060_init_pins(void)
{ {
@ -151,7 +152,8 @@ void rt1040_init_pins(void)
void main(void) void main(void)
{ {
imx_rt_init_boot_clock(); imx_rt_init_boot_clock();
#if defined(CPU_MIMXRT1062DVL6A) || defined(CPU_MIMXRT1064DVL6A) #if defined(CPU_MIMXRT1064DVL6A) || \
defined(CPU_MIMXRT1062DVL6A) || defined(MIMXRT1062DVL6B)
rt1060_init_pins(); rt1060_init_pins();
#elif defined(CPU_MIMXRT1052DVJ6B) #elif defined(CPU_MIMXRT1052DVJ6B)
rt1050_init_pins(); rt1050_init_pins();

14
test-app/imx_rt_clock_config.c
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@ -125,13 +125,13 @@ void imx_rt_init_boot_clock(void)
#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)) #if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
/* Disable Flexspi clock gate. */ /* Disable Flexspi clock gate. */
CLOCK_DisableClock(kCLOCK_FlexSpi); CLOCK_DisableClock(kCLOCK_FlexSpi);
#ifdef CPU_MIMXRT1062DVL6A #if defined(CPU_MIMXRT1062DVL6A) || defined(CPU_MIMXRT1062DVL6B)
/* Set FLEXSPI_PODF. */ /* Set FLEXSPI_PODF. */
CLOCK_SetDiv(kCLOCK_FlexspiDiv, 1); CLOCK_SetDiv(kCLOCK_FlexspiDiv, 1);
/* Set Flexspi clock source. */ /* Set Flexspi clock source. */
CLOCK_SetMux(kCLOCK_FlexspiMux, 3); CLOCK_SetMux(kCLOCK_FlexspiMux, 3);
#endif #endif
#ifdef CPU_MIMXRT1062DVL6A #if defined(CPU_MIMXRT1062DVL6A) || defined(CPU_MIMXRT1062DVL6B)
/* Set FLEXSPI_PODF. */ /* Set FLEXSPI_PODF. */
CLOCK_SetDiv(kCLOCK_FlexspiDiv, 2); CLOCK_SetDiv(kCLOCK_FlexspiDiv, 2);
/* Set Flexspi clock source. */ /* Set Flexspi clock source. */
@ -139,7 +139,7 @@ void imx_rt_init_boot_clock(void)
#endif #endif
#endif #endif
#ifdef CPU_MIMXRT1062DVL6A #if defined(CPU_MIMXRT1062DVL6A) || defined(CPU_MIMXRT1062DVL6B)
/* Disable Flexspi2 clock gate. */ /* Disable Flexspi2 clock gate. */
CLOCK_DisableClock(kCLOCK_FlexSpi2); CLOCK_DisableClock(kCLOCK_FlexSpi2);
/* Set FLEXSPI2_PODF. */ /* Set FLEXSPI2_PODF. */
@ -214,12 +214,12 @@ void imx_rt_init_boot_clock(void)
/* Disable CAN clock gate. */ /* Disable CAN clock gate. */
CLOCK_DisableClock(kCLOCK_Can1); CLOCK_DisableClock(kCLOCK_Can1);
CLOCK_DisableClock(kCLOCK_Can2); CLOCK_DisableClock(kCLOCK_Can2);
#ifdef CPU_MIMXRT1062DVL6A #if defined(CPU_MIMXRT1062DVL6A) || defined(CPU_MIMXRT1062DVL6B)
CLOCK_DisableClock(kCLOCK_Can3); CLOCK_DisableClock(kCLOCK_Can3);
#endif #endif
CLOCK_DisableClock(kCLOCK_Can1S); CLOCK_DisableClock(kCLOCK_Can1S);
CLOCK_DisableClock(kCLOCK_Can2S); CLOCK_DisableClock(kCLOCK_Can2S);
#ifdef CPU_MIMXRT1062DVL6A #if defined(CPU_MIMXRT1062DVL6A) || defined(CPU_MIMXRT1062DVL6B)
CLOCK_DisableClock(kCLOCK_Can3S); CLOCK_DisableClock(kCLOCK_Can3S);
#endif #endif
/* Set CAN_CLK_PODF. */ /* Set CAN_CLK_PODF. */
@ -346,7 +346,7 @@ void imx_rt_init_boot_clock(void)
CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_DIV_SELECT(1); CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_DIV_SELECT(1);
/* Enable Enet output. */ /* Enable Enet output. */
CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENABLE_MASK; CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENABLE_MASK;
#ifdef CPU_MIMXRT1062DVL6A #if defined(CPU_MIMXRT1062DVL6A) || defined(CPU_MIMXRT1062DVL6B)
/* Set Enet2 output divider. */ /* Set Enet2 output divider. */
CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT(0); CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT(0);
/* Enable Enet2 output. */ /* Enable Enet2 output. */
@ -400,7 +400,7 @@ void imx_rt_init_boot_clock(void)
IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0); IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0);
/* Set ENET1 Tx clock source. */ /* Set ENET1 Tx clock source. */
IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET1RefClkMode, false); IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET1RefClkMode, false);
#ifdef CPU_MIMXRT1062DVL6A #if defined(CPU_MIMXRT1062DVL6A) || defined(CPU_MIMXRT1062DVL6B)
/* Set ENET2 Tx clock source. */ /* Set ENET2 Tx clock source. */
#if defined(FSL_IOMUXC_DRIVER_VERSION) && (FSL_IOMUXC_DRIVER_VERSION != (MAKE_VERSION(2, 0, 0))) #if defined(FSL_IOMUXC_DRIVER_VERSION) && (FSL_IOMUXC_DRIVER_VERSION != (MAKE_VERSION(2, 0, 0)))
IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET2RefClkMode, false); IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET2RefClkMode, false);