mirror of https://github.com/wolfSSL/wolfBoot.git
Xilinx Zynq fixes and cleanups. Updated Xilinx SDK instructions for EL-1 / Hypervisor support. Updated the `zynq.ld` script to use 0x4000000 and only DDR0 region. Updated the example BIF files to use EL-1. Fix for cast warnings to `ext_flash_*` API's.
David Garske
parent
1d2a3abd9a
commit
85b7c4d52f
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@ -4,6 +4,17 @@ To use this example project:
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1. Copy `.cproject` and `.project` into the wolfBoot root.
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2. From the Xilinx SDK Import wolfBoot using "Import" -> "Existing Projects into Workspace".
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## Xilinx SDK BSP
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This project uses a BSP named `standalone_bsp_0`, which must be configured to use "hypervisor guest" in the BSP configuration settings. This will enable the EL-1 support required with Bl31 (ARM Trusted Firmware). The BSP generates a include/bspconfig.h, which should have these defines set:
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```
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#define EL1_NONSECURE 1
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#define HYP_GUEST 1
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```
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Note: This is a generated file from the BSP configurator tool, which is edited by opening the `system.mss` file.
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## wolfBoot Configuration
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A build settings template for Zynq UltraScale+ can be found here `./config/examples/zynqmp.config`. This file can be copied to wolfBoot root as `.config` for building from the command line. These template settings are also in this `.cproject` as preprocessor macros. These settings are loaded into the `target.h.in` template by the wolfBoot `make`. If not using the built-in make then the following defines will need to be manually created in `target.h`:
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@ -6,6 +6,6 @@ the_ROM_image:
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[destination_cpu=pmu] pmufw.elf
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[destination_device=pl] system.bit
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[destination_cpu=a53-0, exception_level=el-3, trustzone] bl31.elf
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[destination_cpu=a53-0, exception_level=el-2] wolfboot.elf
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[destination_cpu=a53-0, offset=0x800000, partition_owner=uboot] helloworld_v1_signed.bin
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[destination_cpu=a53-0, exception_level=el-1] wolfboot.elf
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[destination_cpu=a53-0, partition_owner=uboot, offset=0x800000] helloworld_v1_signed.bin
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}
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@ -1,4 +1,5 @@
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// Boot BIF example with Xilinx Secure Boot authentication and wolfBoot
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// Note: Using partition_owner=uboot prevents FSBL from loading to RAM
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the_ROM_image:
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{
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// Boot Header Authentication Enable
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@ -11,19 +12,17 @@ the_ROM_image:
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[pskfile] pskf.pem
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[sskfile] sskf.pem
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[bootloader, destination_cpu=a53-0, authentication=rsa] zynqmp_fsbl.elf
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[destination_cpu=pmu, authentication=rsa] pmufw.elf
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[destination_cpu=a53-0, authentication=rsa, bootloader] zynqmp_fsbl.elf
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[destination_cpu=pmu, authentication=rsa] pmufw.elf
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[destination_device=pl, authentication=rsa] system.bit
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[destination_cpu=a53-0, exception_level=el-3, trustzone, authentication=rsa] bl31.elf
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[destination_cpu=a53-0, authentication=rsa, load=0x11800000] system.dtb
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[destination_cpu=a53-0, authentication=rsa, exception_level=el-3, trustzone] bl31.elf
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// Second Stage wolfBoot Bootloader
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[destination_cpu=a53-0, authentication=rsa, exception_level=el-1] wolfboot.elf
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// ARM Device Tree (loaded to RAM at 0x11800000 by wolfBoot)
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[ destination_cpu=a53-0, authentication=rsa, offset=0x007E0000, partition_owner=uboot] system.dtb
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// Second Stage wolfBoot Bootloader (in RAM at 0x0)
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[destination_cpu=a53-0, exception_level=el-2, authentication=rsa] wolfboot.elf
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[destination_cpu=a53-0, authentication=rsa, partition_owner=uboot, offset=0x7B0000] system.dtb
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// Kernel / Application (load to RAM at 0x10000000 by wolfBoot)
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// Using partition_owner=uboot prevents FSBL from loading to RAM
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[destination_cpu=a53-0, offset=0x800000, partition_owner=uboot] kernel.ui
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[destination_cpu=a53-0, partition_owner=uboot, offset=0x800000] kernel_v1_signed.bin
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}
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@ -83,7 +83,7 @@ To associate the update or the swap partition to an external memory, define `PAR
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The following functions are used to access the external memory, and must be defined when `EXT\_FLASH`
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is on:
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`int ext_flash_write(uint32_t address, const uint8_t *data, int len)`
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`int ext_flash_write(uintptr_t address, const uint8_t *data, int len)`
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This function provides an implementation of the flash write function, using the
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external memory's specific interface. `address` is the offset from the beginning of the
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@ -91,7 +91,7 @@ addressable space in the device, `data` is the payload to be stored,
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and `len` is the size of the payload. `ext_flash_write` should return 0 upon success,
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or a negative value in case of failure.
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`int ext_flash_read(uint32_t address, uint8_t *data, int len)`
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`int ext_flash_read(uintptr_t address, uint8_t *data, int len)`
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This function provides an indirect read of the external memory, using the
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driver's specific interface. `address` is the offset from the beginning of the
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@ -99,7 +99,7 @@ addressable space in the device, `data` is a pointer where payload is stored upo
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call, and `len` is the maximum size allowed for the payload. `ext_flash_read` should return 0
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upon success, or a negative value in case of failure.
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`int ext_flash_erase(uint32_t address, int len)`
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`int ext_flash_erase(uintptr_t address, int len)`
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Called by the bootloader to erase part of the external memory.
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Erase operations must be performed via the specific interface of the target driver (e.g. SPI flash).
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13
hal/zynq.c
13
hal/zynq.c
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@ -44,7 +44,7 @@
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#include "xzynq_gqspi.h"
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#endif
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#define CORTEXA53_0_CPU_CLK_FREQ_HZ 1099989014
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#define CORTEXA53_0_CPU_CLK_FREQ_HZ 1099989014
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#define CORTEXA53_0_TIMESTAMP_CLK_FREQ 99998999
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/* Generic Quad-SPI */
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@ -149,7 +149,7 @@
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#define QSPIDMA_DST_CTRL2_DEF 0x081BFFF8UL
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/* QSPIDMA_DST_STS */
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#define QSPIDMA_DST_STS_WTC 0xE000U
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#define QSPIDMA_DST_STS_WTC 0xE000U
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/* QSPIDMA_DST_I_STS */
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#define QSPIDMA_DST_I_STS_ALL_MASK 0xFEU
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@ -185,8 +185,8 @@
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/* Flash Commands */
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#define WRITE_ENABLE_CMD 0x06U
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#define WRITE_DISABLE_CMD 0x04U
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#define WRITE_ENABLE_CMD 0x06U
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#define WRITE_DISABLE_CMD 0x04U
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#define READ_ID_CMD 0x9FU
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#define MULTI_IO_READ_ID_CMD 0xAFU
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#define READ_FSR_CMD 0x70U
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@ -194,16 +194,12 @@
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#define EXIT_QSPI_MODE_CMD 0xF5U
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#define ENTER_4B_ADDR_MODE_CMD 0xB7U
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#define EXIT_4B_ADDR_MODE_CMD 0xE9U
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#define FAST_READ_CMD 0x0BU
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#define QUAD_READ_4B_CMD 0x6CU
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#define PAGE_PROG_CMD 0x02U
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#define QUAD_PAGE_PROG_4B_CMD 0x34U
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#define SEC_ERASE_CMD 0xD8U
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#define SEC_4K_ERASE_CMD 0x20U
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#define RESET_ENABLE_CMD 0x66U
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#define RESET_MEMORY_CMD 0x99U
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@ -282,6 +278,7 @@ static int qspi_transfer(QspiDev_t* pDev,
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return GQSPI_CODE_SUCCESS;
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}
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#else
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static inline int qspi_isr_wait(uint32_t wait_mask, uint32_t wait_val)
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{
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uint32_t timeout = 0;
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28
hal/zynq.ld
28
hal/zynq.ld
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@ -11,11 +11,8 @@ _EL2_STACK_SIZE = DEFINED(_EL2_STACK_SIZE) ? _EL2_STACK_SIZE : 1024;
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/* Define Memories in the system */
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MEMORY
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{
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ddr4_ctrl_C0_DDR4_ADDRESS_BLOCK : ORIGIN = 0x500000000, LENGTH = 0x20000000
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psu_ddr_0_MEM_0 : ORIGIN = 0x0, LENGTH = 0x7FF00000
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psu_ddr_1_MEM_0 : ORIGIN = 0x800000000, LENGTH = 0x80000000
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psu_ocm_ram_0_MEM_0 : ORIGIN = 0xFFFC0000, LENGTH = 0x40000
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psu_qspi_linear_0_MEM_0 : ORIGIN = 0xC0000000, LENGTH = 0x20000000
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psu_ddr_0_MEM_0 : ORIGIN = 0x40000000, LENGTH = 0x100000
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}
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/* Specify the default entry point to the program */
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@ -230,16 +227,6 @@ SECTIONS
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__sdata_end = .;
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} > psu_ddr_0_MEM_0
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.sbss (NOLOAD) : {
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. = ALIGN(64);
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__sbss_start = .;
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*(.sbss)
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*(.sbss.*)
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*(.gnu.linkonce.sb.*)
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. = ALIGN(64);
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__sbss_end = .;
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} > psu_ddr_0_MEM_0
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.tdata : {
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. = ALIGN(64);
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__tdata_start = .;
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@ -258,6 +245,17 @@ SECTIONS
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__tbss_end = .;
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} > psu_ddr_0_MEM_0
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.sbss (NOLOAD) : {
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. = ALIGN(64);
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__sbss_start = .;
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*(.sbss)
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*(.sbss.*)
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*(.gnu.linkonce.sb.*)
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. = ALIGN(64);
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__sbss_end = .;
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} > psu_ddr_0_MEM_0
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.bss (NOLOAD) : {
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. = ALIGN(64);
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__bss_start__ = .;
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@ -154,7 +154,7 @@ static uint8_t *get_sha_block(struct wolfBoot_image *img, uint32_t offset)
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if (offset > img->fw_size)
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return NULL;
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if (PART_IS_EXT(img)) {
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ext_flash_read((unsigned long)(img->fw_base) + offset, ext_hash_block, WOLFBOOT_SHA_BLOCK_SIZE);
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ext_flash_read((uintptr_t)(img->fw_base) + offset, ext_hash_block, WOLFBOOT_SHA_BLOCK_SIZE);
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return ext_hash_block;
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} else
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return (uint8_t *)(img->fw_base + offset);
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@ -345,7 +345,7 @@ uint32_t wolfBoot_get_image_version(uint8_t part)
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if (PARTN_IS_EXT(PART_UPDATE))
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{
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#ifdef EXT_FLASH
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ext_flash_read((uint32_t)WOLFBOOT_PARTITION_UPDATE_ADDRESS, hdr_cpy, IMAGE_HEADER_SIZE);
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ext_flash_read((uintptr_t)WOLFBOOT_PARTITION_UPDATE_ADDRESS, hdr_cpy, IMAGE_HEADER_SIZE);
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hdr_cpy_done = 1;
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image = hdr_cpy;
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#endif
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@ -355,7 +355,7 @@ uint32_t wolfBoot_get_image_version(uint8_t part)
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} else if (part == PART_BOOT) {
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if (PARTN_IS_EXT(PART_BOOT)) {
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#ifdef EXT_FLASH
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ext_flash_read((uint32_t)WOLFBOOT_PARTITION_BOOT_ADDRESS, hdr_cpy, IMAGE_HEADER_SIZE);
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ext_flash_read((uintptr_t)WOLFBOOT_PARTITION_BOOT_ADDRESS, hdr_cpy, IMAGE_HEADER_SIZE);
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hdr_cpy_done = 1;
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image = hdr_cpy;
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#endif
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@ -376,7 +376,7 @@ uint16_t wolfBoot_get_image_type(uint8_t part)
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if (PARTN_IS_EXT(PART_UPDATE))
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{
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#ifdef EXT_FLASH
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ext_flash_read((uint32_t)WOLFBOOT_PARTITION_UPDATE_ADDRESS, hdr_cpy, IMAGE_HEADER_SIZE);
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ext_flash_read((uintptr_t)WOLFBOOT_PARTITION_UPDATE_ADDRESS, hdr_cpy, IMAGE_HEADER_SIZE);
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hdr_cpy_done = 1;
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image = hdr_cpy;
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#endif
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@ -386,7 +386,7 @@ uint16_t wolfBoot_get_image_type(uint8_t part)
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} else if (part == PART_BOOT) {
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if (PARTN_IS_EXT(PART_BOOT)) {
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#ifdef EXT_FLASH
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ext_flash_read((uint32_t)WOLFBOOT_PARTITION_BOOT_ADDRESS, hdr_cpy, IMAGE_HEADER_SIZE);
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ext_flash_read((uintptr_t)WOLFBOOT_PARTITION_BOOT_ADDRESS, hdr_cpy, IMAGE_HEADER_SIZE);
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hdr_cpy_done = 1;
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image = hdr_cpy;
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#endif
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@ -52,7 +52,7 @@ static int wolfBoot_copy_sector(struct wolfBoot_image *src, struct wolfBoot_imag
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wb_flash_erase(dst, dst_sector_offset, WOLFBOOT_SECTOR_SIZE);
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while (pos < WOLFBOOT_SECTOR_SIZE) {
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if (src_sector_offset + pos < (src->fw_size + IMAGE_HEADER_SIZE + FLASHBUFFER_SIZE)) {
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ext_flash_read((uint32_t)(src->hdr) + src_sector_offset + pos, (void *)buffer, FLASHBUFFER_SIZE);
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ext_flash_read((uintptr_t)(src->hdr) + src_sector_offset + pos, (void *)buffer, FLASHBUFFER_SIZE);
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wb_flash_write(dst, dst_sector_offset + pos, buffer, FLASHBUFFER_SIZE);
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}
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pos += FLASHBUFFER_SIZE;
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@ -56,7 +56,7 @@ static void RAMFUNCTION wolfBoot_self_update(struct wolfBoot_image *src)
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if (PART_IS_EXT(src)) {
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uint8_t buffer[FLASHBUFFER_SIZE];
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if (src_offset + pos < (src->fw_size + IMAGE_HEADER_SIZE + FLASHBUFFER_SIZE)) {
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ext_flash_read((uint32_t)(src->hdr) + src_offset + pos, (void *)buffer, FLASHBUFFER_SIZE);
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ext_flash_read((uintptr_t)(src->hdr) + src_offset + pos, (void *)buffer, FLASHBUFFER_SIZE);
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hal_flash_write(pos + (uint32_t)&_start_text, buffer, FLASHBUFFER_SIZE);
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}
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pos += FLASHBUFFER_SIZE;
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@ -122,7 +122,7 @@ static int wolfBoot_copy_sector(struct wolfBoot_image *src, struct wolfBoot_imag
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wb_flash_erase(dst, dst_sector_offset, WOLFBOOT_SECTOR_SIZE);
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while (pos < WOLFBOOT_SECTOR_SIZE) {
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if (src_sector_offset + pos < (src->fw_size + IMAGE_HEADER_SIZE + FLASHBUFFER_SIZE)) {
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ext_flash_read((uint32_t)(src->hdr) + src_sector_offset + pos, (void *)buffer, FLASHBUFFER_SIZE);
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ext_flash_read((uintptr_t)(src->hdr) + src_sector_offset + pos, (void *)buffer, FLASHBUFFER_SIZE);
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wb_flash_write(dst, dst_sector_offset + pos, buffer, FLASHBUFFER_SIZE);
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}
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pos += FLASHBUFFER_SIZE;
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