mirror of https://github.com/wolfSSL/wolfBoot.git
[SAMA5D3] Nand flash driver
Daniele Lacamera
parent
bbd4e2b1c3
commit
888d538760
2
.gdbinit
2
.gdbinit
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@ -1,5 +1,5 @@
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tar rem:3333
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file wolfboot.elf
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tar rem:3333
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add-symbol-file test-app/image.elf
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foc c
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3
arch.mk
3
arch.mk
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@ -178,7 +178,8 @@ ifeq ($(ARCH),ARM)
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ifeq ($(TARGET),sama5d3)
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CORTEX_A5=1
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UPDATE_OBJS:=src/update_ram.o
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CFLAGS+=-DWOLFBOOT_DUALBOOT
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CFLAGS+=-DWOLFBOOT_DUALBOOT -DEXT_FLASH -DNAND_FLASH
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#CFLAGS+=-DWOLFBOOT_USE_STDLIBC
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endif
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## Cortex CPU
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@ -0,0 +1,23 @@
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ARCH?=ARM
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TARGET?=sama5d3
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SIGN?=ECC256
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HASH?=SHA256
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DEBUG?=1
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VTOR?=1
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CORTEX_M0?=0
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NO_ASM?=0
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EXT_FLASH?=1
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NAND_FLASH?=1
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SPI_FLASH?=0
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V?=0
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SPMATH?=1
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WOLFBOOT_PARTITION_SIZE?=0x1000000
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WOLFBOOT_NO_PARTITIONS=0
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WOLFBOOT_SECTOR_SIZE?=0x1000
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WOLFBOOT_LOAD_ADDRESS=0x380000
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WOLFBOOT_LOAD_DTS_ADDRESS=0x3C0000
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WOLFBOOT_PARTITION_BOOT_ADDRESS=0x40000
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WOLFBOOT_PARTITION_UPDATE_ADDRESS=0x80000
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WOLFBOOT_PARTITION_SWAP_ADDRESS=0x0
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NO_XIP=1
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IMAGE_HEADER_SIZE=2048
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402
hal/sama5d3.c
402
hal/sama5d3.c
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@ -27,21 +27,403 @@
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# error "wolfBoot atsama5d3 HAL: wrong architecture selected. Please compile with ARCH=ARM."
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#endif
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#define TEST_ENCRYPT
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/* Fixed addresses */
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extern void *kernel_addr, *update_addr, *dts_addr;
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void* hal_get_primary_address(void)
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#if defined(EXT_FLASH) && defined(NAND_FLASH)
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/* Constant for local buffers */
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#define NAND_FLASH_PAGE_SIZE 0x800 /* 2KB */
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#define NAND_FLASH_OOB_SIZE 0x40 /* 64B */
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/* Address space mapping for atsama5d3 */
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#define AT91C_BASE_DDRCS 0x20000000
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#define AT91C_BASE_CS1 0x40000000
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#define AT91C_BASE_CS2 0x50000000
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#define AT91C_BASE_CS3 0x60000000
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#define AT91C_BASE_NFC_CMD 0x70000000
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/* NAND flash is mapped to CS3 */
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#define NAND_BASE AT91C_BASE_CS3
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#define NAND_MASK_ALE (1 << 21)
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#define NAND_MASK_CLE (1 << 22)
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#define NAND_CMD (*((volatile uint8_t *)(NAND_BASE | NAND_MASK_CLE)))
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#define NAND_ADDR (*((volatile uint8_t *)(NAND_BASE | NAND_MASK_ALE)))
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#define NAND_DATA (*((volatile uint8_t *)(NAND_BASE)))
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#define NAND_DATAW (*((volatile uint32_t *)(NAND_BASE)))
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/* Command set */
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#define NAND_CMD_STATUS 0x70
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#define NAND_CMD_READ1 0x00
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#define NAND_CMD_READ2 0x30
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#define NAND_CMD_READID 0x90
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#define NAND_CMD_RESET 0xFF
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#define NAND_CMD_ERASE1 0x60
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#define NAND_CMD_ERASE2 0xD0
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#define NAND_CMD_WRITE1 0x80
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#define NAND_CMD_WRITE2 0x10
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/* Small block */
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#define NAND_CMD_READ_A0 0x00
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#define NAND_CMD_READ_A1 0x01
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#define NAND_CMD_READ_C 0x50
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#define NAND_CMD_WRITE_A 0x00
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#define NAND_CMD_WRITE_C 0x50
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/* ONFI */
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#define NAND_CMD_READ_ONFI 0xEC
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/* Features set/get */
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#define NAND_CMD_GET_FEATURES 0xEE
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#define NAND_CMD_SET_FEATURES 0xEF
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/* ONFI parameters and definitions */
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#define ONFI_PARAMS_SIZE 256
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#define PARAMS_POS_REVISION 4
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#define PARAMS_REVISION_1_0 (0x1 << 1)
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#define PARAMS_REVISION_2_0 (0x1 << 2)
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#define PARAMS_REVISION_2_1 (0x1 << 3)
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#define PARAMS_POS_FEATURES 6
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#define PARAMS_FEATURE_BUSWIDTH (0x1 << 0)
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#define PARAMS_FEATURE_EXTENDED_PARAM (0x1 << 7)
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#define PARAMS_POS_OPT_CMD 8
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#define PARAMS_OPT_CMD_SET_GET_FEATURES (0x1 << 2)
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#define PARAMS_POS_EXT_PARAM_PAGE_LEN 12
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#define PARAMS_POS_PARAMETER_PAGE 14
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#define PARAMS_POS_PAGESIZE 80
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#define PARAMS_POS_OOBSIZE 84
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#define PARAMS_POS_BLOCKSIZE 92
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#define PARAMS_POS_NBBLOCKS 96
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#define PARAMS_POS_ECC_BITS 112
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#define PARAMS_POS_TIMING_MODE 129
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#define PARAMS_TIMING_MODE_0 (1 << 0)
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#define PARAMS_TIMING_MODE_1 (1 << 1)
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#define PARAMS_TIMING_MODE_2 (1 << 2)
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#define PARAMS_TIMING_MODE_3 (1 << 3)
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#define PARAMS_TIMING_MODE_4 (1 << 4)
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#define PARAMS_TIMING_MODE_5 (1 << 5)
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#define PARAMS_POS_CRC 254
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#define ONFI_CRC_BASE 0x4F4E
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#define ONFI_MAX_SECTIONS 8
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#define ONFI_SECTION_TYPE_0 0
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#define ONFI_SECTION_TYPE_1 1
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#define ONFI_SECTION_TYPE_2 2
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/* Read access modes */
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#define NAND_MODE_DATAPAGE 1
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#define NAND_MODE_INFO 2
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#define NAND_MODE_DATABLOCK 3
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/*
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#define LOOKUP_TABLE_ALPHA_OFFSET 0x14000
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#define LOOKUP_TABLE_INDEX_OFFSET 0x10000
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#define LOOKUP_TABLE_ALPHA_OFFSET_1024 0x20000
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#define LOOKUP_TABLE_INDEX_OFFSET_1024 0x18000
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*/
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#define nand_flash_read ext_flash_read
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#define nand_flash_write ext_flash_write
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#define nand_flash_erase ext_flash_erase
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#define nand_flash_unlock ext_flash_unlock
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#define nand_flash_lock ext_flash_lock
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#define MAX_ECC_BYTES 8
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/* Static variables to hold nand info */
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static uint8_t nand_manif_id;
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static uint8_t nand_dev_id;
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static char nand_onfi_id[4];
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struct nand_flash {
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uint16_t revision;
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uint16_t features;
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uint16_t ext_page_len;
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uint16_t parameter_page;
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uint32_t page_size;
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uint32_t block_size;
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uint32_t block_count;
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uint32_t pages_per_block;
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uint32_t pages_per_device;
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uint32_t total_size;
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uint16_t bad_block_pos;
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uint16_t ecc_bytes;
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uint16_t eccpos[MAX_ECC_BYTES];
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uint16_t eccwordsize;
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uint32_t bus_width;
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uint32_t oob_size;
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} nand_flash = { 0 };
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static void nand_wait_ready(void)
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{
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return (void*)&kernel_addr;
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NAND_CMD = NAND_CMD_STATUS;
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while (!(NAND_DATA & 0x40));
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}
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void* hal_get_update_address(void)
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static void nand_read_id(uint8_t *manif_id, uint8_t *dev_id)
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{
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return (void*)&update_addr;
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NAND_CMD = NAND_CMD_READID;
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NAND_ADDR = 0x00;
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*manif_id = NAND_DATA;
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*dev_id = NAND_DATA;
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}
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static void nand_reset(void)
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{
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NAND_CMD = NAND_CMD_RESET;
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nand_wait_ready();
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}
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static void write_column_address(uint32_t col_address)
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{
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NAND_ADDR = col_address & 0xFF;
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NAND_ADDR = (col_address >> 8) & 0xFF;
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NAND_ADDR = (col_address >> 16) & 0xFF;
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}
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static void write_row_address(uint32_t row_address)
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{
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NAND_ADDR = row_address & 0xFF;
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NAND_ADDR = (row_address >> 8) & 0xFF;
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NAND_ADDR = (row_address >> 16) & 0xFF;
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NAND_ADDR = (row_address >> 24) & 0xFF;
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}
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static void nand_read_info(void)
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{
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uint8_t onfi_data[ONFI_PARAMS_SIZE];
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uint32_t i;
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nand_reset();
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nand_read_id(&nand_manif_id, &nand_dev_id);
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NAND_CMD = NAND_CMD_READID;
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NAND_ADDR = 0x20;
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nand_onfi_id[0] = NAND_DATA;
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nand_onfi_id[1] = NAND_DATA;
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nand_onfi_id[2] = NAND_DATA;
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nand_onfi_id[3] = NAND_DATA;
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if (memcmp(nand_onfi_id, "ONFI", 4) != 0) {
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/* Fail: no ONFI support */
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asm("bkpt 0");
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return;
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}
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memset(&nand_flash, 0, sizeof(nand_flash));
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memset(nand_flash.eccpos, 0xFF, sizeof(nand_flash.eccpos));
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NAND_CMD = NAND_CMD_READ_ONFI;
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NAND_ADDR = 0x00;
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nand_wait_ready();
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NAND_CMD = NAND_CMD_READ1;
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for (i = 0; i < ONFI_PARAMS_SIZE; i++) {
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onfi_data[i] = NAND_DATA;
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}
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/* Store ONFI parameters in nand_flash struct */
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nand_flash.page_size = *(uint16_t *)(onfi_data + PARAMS_POS_PAGESIZE);
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nand_flash.pages_per_block = *(uint16_t *)(onfi_data + PARAMS_POS_BLOCKSIZE);
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nand_flash.block_size = nand_flash.page_size * nand_flash.pages_per_block;
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nand_flash.block_count = *(uint16_t *)(onfi_data + PARAMS_POS_NBBLOCKS);
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nand_flash.total_size = nand_flash.block_count * nand_flash.block_size;
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nand_flash.ecc_bytes = *(uint16_t *)(onfi_data + PARAMS_POS_ECC_BITS);
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nand_flash.bad_block_pos = (*(uint16_t *)(onfi_data + PARAMS_POS_FEATURES)) & 1;
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nand_flash.ext_page_len = *(uint16_t *)(onfi_data + PARAMS_POS_EXT_PARAM_PAGE_LEN);
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nand_flash.parameter_page = *(uint16_t *)(onfi_data + PARAMS_POS_PARAMETER_PAGE);
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nand_flash.pages_per_block = nand_flash.block_size / nand_flash.page_size;
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nand_flash.pages_per_device = nand_flash.pages_per_block * nand_flash.block_count;
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nand_flash.oob_size = *(uint16_t *)(onfi_data + PARAMS_POS_OOBSIZE);
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nand_flash.revision = *(uint16_t *)(onfi_data + PARAMS_POS_REVISION);
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nand_flash.features = *(uint16_t *)(onfi_data + PARAMS_POS_FEATURES);
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nand_flash.bus_width = (onfi_data[PARAMS_POS_FEATURES] & PARAMS_FEATURE_BUSWIDTH) ? 16 : 8;
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if (nand_flash.ecc_bytes <= MAX_ECC_BYTES) {
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for (int i = 0; i < nand_flash.ecc_bytes; i++) {
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nand_flash.eccpos[i] = *(uint16_t *)(onfi_data + PARAMS_POS_ECC_BITS + i * 2);
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}
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}
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if (nand_flash.page_size != NAND_FLASH_PAGE_SIZE) {
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/* Fail: unsupported page size */
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asm("bkpt 0");
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}
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if (nand_flash.oob_size != NAND_FLASH_OOB_SIZE) {
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/* Fail: unsupported oob size */
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asm("bkpt 0");
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}
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}
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static void set_col_addr(uint32_t col_address)
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{
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uint32_t page_size = nand_flash.page_size;
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while (page_size > 0) {
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NAND_ADDR = col_address & 0xFF;
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col_address >>= 8;
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page_size >>= 8;
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}
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}
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static void set_row_addr(uint32_t row_address)
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{
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uint32_t pages_per_device = nand_flash.pages_per_device;
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while (pages_per_device > 0) {
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NAND_ADDR = row_address & 0xFF;
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row_address >>= 8;
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pages_per_device >>= 8;
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}
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}
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static int nand_device_read(uint32_t row_address, uint8_t *data, int mode)
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{
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uint32_t col_address = 0x00;
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uint32_t tot_len = 0;
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uint32_t page_size = nand_flash.page_size;
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uint32_t pages_per_device = nand_flash.pages_per_device;
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uint32_t i;
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if (mode == NAND_MODE_DATAPAGE) {
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tot_len = nand_flash.page_size;
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} else if (mode == NAND_MODE_INFO) {
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tot_len = nand_flash.oob_size;
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col_address = nand_flash.page_size;
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} else if (mode == NAND_MODE_DATABLOCK) {
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tot_len = nand_flash.block_size;
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} else {
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/* Fail: unknown mode */
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return -1;
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}
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NAND_CMD = NAND_CMD_READ1;
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set_col_addr(col_address);
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set_row_addr(row_address);
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NAND_CMD = NAND_CMD_READ2;
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nand_wait_ready();
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NAND_CMD = NAND_CMD_READ1;
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for (i = 0; i < tot_len; i++) {
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data[i] = NAND_DATA;
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}
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return 0;
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}
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static int nand_read_page(uint32_t block, uint32_t page, uint8_t *data)
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{
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uint32_t row_address = block * nand_flash.pages_per_block + page;
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return nand_device_read(row_address, data, NAND_MODE_DATAPAGE);
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}
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static int nand_check_bad_block(uint32_t block)
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{
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uint32_t row_address = block * nand_flash.pages_per_block;
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uint8_t oob[NAND_FLASH_OOB_SIZE];
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uint32_t page;
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for (page = 0; page < 2; page++) {
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nand_device_read(row_address + page, oob, NAND_MODE_INFO);
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if (oob[0] != 0xFF) {
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return -1;
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}
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}
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return 0;
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}
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static uint8_t buffer_page[NAND_FLASH_PAGE_SIZE];
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int ext_flash_read(uintptr_t address, uint8_t *data, int len)
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{
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uint32_t block = address / nand_flash.block_size; /* The block where the address falls in */
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uint32_t page = address / nand_flash.page_size; /* The page where the address falls in */
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uint32_t start_page_in_block = page % nand_flash.pages_per_block; /* The start page within this block */
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uint32_t in_block_offset = address % nand_flash.block_size; /* The offset of the address within the block */
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uint32_t remaining = nand_flash.block_size - in_block_offset; /* How many bytes remaining to read in the first block */
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uint32_t len_to_read = len;
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uint8_t *buffer = data;
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uint32_t i;
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int copy = 0;
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int ret;
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if (len < (int)nand_flash.page_size) {
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buffer = buffer_page;
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copy = 1;
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len_to_read = nand_flash.page_size;
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}
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while (len_to_read > 0) {
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uint32_t sz = len_to_read;
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uint32_t pages_to_read;
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if (sz > remaining)
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sz = remaining;
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do {
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ret = nand_check_bad_block(block);
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if (ret < 0) {
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/* Block is bad, skip it */
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block++;
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}
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} while (ret < 0);
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/* Amount of pages to be read from this block */
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pages_to_read = (sz + nand_flash.page_size - 1) / nand_flash.page_size;
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if (pages_to_read * nand_flash.page_size > remaining)
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pages_to_read--;
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/* Read (remaining) pages off a block */
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for (i = 0; i < pages_to_read; i++) {
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nand_read_page(block, start_page_in_block + i, buffer);
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len_to_read -= sz;
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buffer += sz;
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}
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/* The block is over, move to the next one */
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block++;
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start_page_in_block = 0;
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remaining = nand_flash.block_size;
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}
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if (copy) {
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uint32_t *dst = (uint32_t *)data;
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uint32_t *src = (uint32_t *)buffer_page;
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for (i = 0; i < (len / sizeof(uint32_t)); i++) {
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dst[i] = src[i];
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}
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}
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return len;
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}
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int ext_flash_write(uintptr_t address, const uint8_t *data, int len)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
int ext_flash_erase(uintptr_t address, int len)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* SAMA5D3 NAND flash does not have an enable pin */
|
||||
void ext_flash_unlock(void)
|
||||
{
|
||||
}
|
||||
|
||||
void ext_flash_lock(void)
|
||||
{
|
||||
}
|
||||
#endif
|
||||
|
||||
void* hal_get_dts_address(void)
|
||||
{
|
||||
return (void*)&dts_addr;
|
||||
|
|
@ -63,10 +445,10 @@ void zynq_init(uint32_t cpu_clock)
|
|||
}
|
||||
|
||||
|
||||
|
||||
/* public HAL functions */
|
||||
void hal_init(void)
|
||||
{
|
||||
nand_read_info();
|
||||
}
|
||||
|
||||
void hal_prepare_boot(void)
|
||||
|
|
@ -74,7 +456,7 @@ void hal_prepare_boot(void)
|
|||
}
|
||||
|
||||
|
||||
int RAMFUNCTION hal_flash_write(uintptr_t address, const uint8_t *data, int len)
|
||||
int RAMFUNCTION hal_flash_write(uint32_t address, const uint8_t *data, int len)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -88,7 +470,9 @@ void RAMFUNCTION hal_flash_lock(void)
|
|||
}
|
||||
|
||||
|
||||
int RAMFUNCTION hal_flash_erase(uintptr_t address, int len)
|
||||
int RAMFUNCTION hal_flash_erase(uint32_t address, int len)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -3,7 +3,7 @@ OUTPUT_ARCH(arm)
|
|||
|
||||
MEMORY
|
||||
{
|
||||
DDR_MEM(rwx): ORIGIN = 0x00300000, LENGTH = 0x000100000
|
||||
DDR_MEM(rwx): ORIGIN = 0x00300000, LENGTH = 0x0007F000
|
||||
}
|
||||
|
||||
ENTRY(reset_vector_entry)
|
||||
|
|
|
|||
|
|
@ -196,7 +196,7 @@ ifeq ($(SIGN),ED448)
|
|||
ifeq ($(WOLFBOOT_SMALL_STACK),1)
|
||||
STACK_USAGE?=1024
|
||||
else
|
||||
STACK_USAGE?=4376
|
||||
STACK_USAGE?=4578
|
||||
endif
|
||||
endif
|
||||
|
||||
|
|
|
|||
|
|
@ -3,7 +3,7 @@ OUTPUT_ARCH(arm)
|
|||
|
||||
MEMORY
|
||||
{
|
||||
DDR_MEM(rwx): ORIGIN = 0x00300000, LENGTH = 0x000100000
|
||||
DDR_MEM(rwx): ORIGIN = 0x00340000, LENGTH = 0x000100000
|
||||
}
|
||||
|
||||
ENTRY(reset_vector_entry)
|
||||
|
|
|
|||
Loading…
Reference in New Issue