From 8c1b3713d06c7a7e301804542ffc97603c0e0ec5 Mon Sep 17 00:00:00 2001
From: Elms <jeff@wolfssl.com>
Date: Tue, 1 Jun 2021 22:32:51 -0700
Subject: [PATCH] TMS570LC43xx: update `do_boot` and exception handling

---
 IDE/CCS/TMS570LC43xx/README.md | 18 +++++++++++++--
 IDE/CCS/TMS570LC43xx/target.h  |  8 +++----
 src/boot_arm.c                 | 41 +++++++++++++++++++++++++---------
 3 files changed, 50 insertions(+), 17 deletions(-)

diff --git a/IDE/CCS/TMS570LC43xx/README.md b/IDE/CCS/TMS570LC43xx/README.md
index f6db2ab7..a832c90d 100644
--- a/IDE/CCS/TMS570LC43xx/README.md
+++ b/IDE/CCS/TMS570LC43xx/README.md
@@ -1,8 +1,8 @@
 # TMS750LC43xx
 
-#Build
+# Build
 
-# build from command line
+## Build from command line
 
 ```
 make CCS_ROOT=/c/ti/ccs1031/ccs/tools/compiler/ti-cgt-arm_20.2.4.LTS F021_DIR=/c/ti/Hercules/F021\ Flash\ API/02.01.01
@@ -65,3 +65,17 @@ c:\ti\ccs1031\ccs\ccs_base\scripting\examples\uniflash\cmdLine\uniflash.bat -ccx
 
 [dss reference](http://software-dl.ti.com/ccs/esd/documents/users_guide/sdto_dss_handbook.html)
 
+
+# Details
+
+ * R5 vector table can only be be at 0 or 0xFFFF0000
+   * A possible strategy is to have simple handlers that check
+     if a RAM overload is available. This requires shared state
+     between a bootloader and application.
+
+# Implemenation notes
+ * ASM must be self contained. See SPNU151V - ARM Optimizing C/C++ Compiler v20.2.0.LTS January 1998–Revised February 2020
+
+> The __asm statement does not provide any way to refer to local
+> variables. If your assembly code needs to refer to local variables,
+> you will need to write the entire function in assembly code.
diff --git a/IDE/CCS/TMS570LC43xx/target.h b/IDE/CCS/TMS570LC43xx/target.h
index 38366cf8..a4290f18 100644
--- a/IDE/CCS/TMS570LC43xx/target.h
+++ b/IDE/CCS/TMS570LC43xx/target.h
@@ -28,10 +28,10 @@
 #define H_TARGETS_TARGET_
 
 #define WOLFBOOT_SECTOR_SIZE                 0x1000
-#define WOLFBOOT_PARTITION_BOOT_ADDRESS      0x00020000
-#define WOLFBOOT_PARTITION_SIZE              0x20000
-#define WOLFBOOT_PARTITION_UPDATE_ADDRESS    0x00040000
-#define WOLFBOOT_PARTITION_SWAP_ADDRESS      0x00060000
+#define WOLFBOOT_PARTITION_BOOT_ADDRESS      0x020000
+#define WOLFBOOT_PARTITION_SIZE              0x0e0000
+#define WOLFBOOT_PARTITION_UPDATE_ADDRESS    0x100000
+#define WOLFBOOT_PARTITION_SWAP_ADDRESS      0x1e0000
 
 /* Load address in RAM for staged OS (update_ram only) */
 #define WOLFBOOT_DTS_BOOT_ADDRESS
diff --git a/src/boot_arm.c b/src/boot_arm.c
index a96bfb8e..58d10e74 100644
--- a/src/boot_arm.c
+++ b/src/boot_arm.c
@@ -202,6 +202,17 @@ void isr_reset(void) {
     main();
 }
 
+// forward to app handler
+#define ISR_FORWARDER(name, addr_low) \
+  void name(void) { asm volatile("  mov r1, #" #addr_low ";\n  movt r1, #0x0002;\n  bx r1\n"); }
+
+ISR_FORWARDER(isr_swi, 0x0108)
+ISR_FORWARDER(isr_abort_prefetch, 0x010c)
+ISR_FORWARDER(isr_abort_data, 0x0110)
+ISR_FORWARDER(isr_reserved, 0x0114)
+ISR_FORWARDER(isr_irq, 0x0118)
+ISR_FORWARDER(isr_fiq, 0x011c)
+
 void isr_fault(void)
 {
     /* Panic. */
@@ -239,22 +250,13 @@ void isr_empty(void)
 static void  *app_entry;
 static uint32_t app_end_stack;
 
-#if defined(CORTEX_R5)
-void do_boot_r5(void* app_entry, uint32_t app_end_stack);
-
-asm volatile("do_boot_r5:\n"
-             "  mov     sp, a2\n"
-             "  mov     pc, a1\n");
-#endif
 
 void RAMFUNCTION do_boot(const uint32_t *app_offset)
 {
 #if defined(CORTEX_R5)
   /* limitations with TI arm compiler requires assembly */
-  app_end_stack = (*((uint32_t *)(app_offset)));
-  app_entry = (void *)(*((uint32_t *)(app_offset + 1)));
-
-  do_boot_r5(app_entry, app_end_stack);
+    asm volatile("do_boot_r5:\n"
+                 "  mov     pc, r0\n");
 
 #elif defined(CORTEX_M33) /* Armv8 boot procedure */
 
@@ -308,6 +310,22 @@ typedef void(*NMIHANDLER)(void);
 #   define isr_NMI isr_empty
 #endif
 
+#ifdef CORTEX_R5
+//__attribute__ ((section(".isr_vector")))
+asm volatile (
+"  .sect \".isr_vector\"\n"
+"resetEntry:\n"
+"  b   isr_reset\n"        // Reset
+"  b   isr_fault\n"        // Undefined
+"  b   isr_swi  \n"        // Software interrupt
+"  b   isr_abort_prefetch\n"        // Abort (Prefetch)
+"  b   isr_abort_data\n"        // Abort (Data)
+"  b   isr_reserved\n"        // Reserved
+"  b   isr_irq\n"  // IRQ
+"  b   isr_fiq\n"  // FIQ
+              );
+
+#else
 __attribute__ ((section(".isr_vector")))
 void (* const IV[])(void) =
 {
@@ -394,6 +412,7 @@ void (* const IV[])(void) =
     isr_empty,
 #endif
 };
+#endif
 
 #ifdef RAM_CODE