mirror of https://github.com/wolfSSL/wolfBoot.git
PCI: add initial support
It support basic enumeration (only bus 0), and reading/writing to config space register.pull/327/head
Marco Oliverio
parent
1e754ca8f5
commit
8ce80d6a65
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@ -0,0 +1,73 @@
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/* pci.h
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*
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* Copyright (C) 2023 wolfSSL Inc.
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*
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* This file is part of wolfBoot.
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*
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* wolfBoot is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* wolfBoot is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
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*/
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#ifndef PCI_H
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#define PCI_H
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#include <stdint.h>
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#define PCI_VENDOR_ID_OFFSET 0x00
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#define PCI_DEVICE_ID_OFFSET 0x02
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#define PCI_COMMAND_OFFSET 0x04
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/* Programming interface, Rev. ID and class code */
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#define PCI_RID_CC_OFFSET 0x08
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#define PCI_HEADER_TYPE_OFFSET 0x0E
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#define PCI_BAR0_OFFSET (0x10)
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#define PCI_BAR5_OFFSET 0x24
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#define PCI_BAR5_MASK (~0x3)
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#define PCI_INTR_OFFSET 0x3C
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#define PCI_HEADER_TYPE_MULTIFUNC_MASK 0x80
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#define PCI_HEADER_TYPE_TYPE_MASK 0x7F
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#define PCI_HEADER_TYPE_DEVICE 0x0
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#define PCI_HEADER_TYPE_BRIDGE 0x1
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#define PCI_CLASS_MASS_STORAGE 0x01
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#define PCI_SUBCLASS_SATA 0x06
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#define PCI_INTERFACE_AHCI 0x01
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/* Shifts & masks for CONFIG_ADDRESS register */
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#define PCI_CONFIG_ADDRESS_ENABLE_BIT_SHIFT 31
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#define PCI_CONFIG_ADDRESS_BUS_SHIFT 16
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#define PCI_CONFIG_ADDRESS_DEVICE_SHIFT 11
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#define PCI_CONFIG_ADDRESS_FUNCTION_SHIFT 8
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#define PCI_CONFIG_ADDRESS_OFFSET_MASK 0xFF
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/* COMMAND bits */
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#define PCI_COMMAND_INT_DIS (1 << 10)
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#define PCI_COMMAND_FAST_B2B_EN (1 << 9)
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#define PCI_COMMAND_SERR_EN (1 << 8)
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#define PCI_COMMAND_PE_RESP (1 << 6)
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#define PCI_COMMAND_VGASNOOP (1 << 5)
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#define PCI_COMMAND_MW_INV_EN (1 << 4)
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#define PCI_COMMAND_SPECIAL_CYCLE (1 << 3)
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#define PCI_COMMAND_BUS_MASTER (1 << 2)
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#define PCI_COMMAND_MEM_SPACE (1 << 1)
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#define PCI_COMMAND_IO_SPACE (1 << 0)
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uint32_t pch_read32(uint8_t port_id, uint16_t offset);
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void pch_write32(uint8_t port_id, uint16_t offset, uint32_t val);
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uint32_t pci_config_read32(uint8_t bus, uint8_t dev, uint8_t fun, uint8_t off);
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void pci_config_write32(uint8_t bus, uint8_t dev, uint8_t fun, uint8_t off,
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uint32_t value);
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uint16_t pci_config_read16(uint8_t bus, uint8_t dev, uint8_t fun, uint8_t off);
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void pci_config_write16(uint8_t bus, uint8_t dev, uint8_t fun, uint8_t off,
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uint16_t value);
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int pci_enum_do();
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#endif /* PCI_H */
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@ -0,0 +1,500 @@
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/* pci.c
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*
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* Copyright (C) 2023 wolfSSL Inc.
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*
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* This file is part of wolfBoot.
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*
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* wolfBoot is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* wolfBoot is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
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*/
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#include <stdint.h>
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#include <pci.h>
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#include <printf.h>
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#include <x86/common.h>
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#ifdef DEBUG_PCI
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#define PCI_DEBUG_PRINTF(...) wolfBoot_printf(__VA_ARGS__)
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#else
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#define PCI_DEBUG_PRINTF(...) do {} while(0)
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#endif /* DEBUG_PCI */
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/* TODO: recover from BAR and set after FSP-T */
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#ifdef PCH_HAS_PCR
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#ifndef PCH_PCR_BASE
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#error "define PCH_PCR_BASE"
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#endif
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#endif /* PCH_HAS_PCR */
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#ifdef PCI_USE_ECAM
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#ifndef PCI_ECAM_BASE
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#error "define PCI_ECAM_BASE"
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#endif
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#endif /* PCI_USE_ECAM */
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#define PCI_ADDR_16BIT_ALIGNED_MASK (0x1)
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#define PCI_ADDR_32BIT_ALIGNED_MASK (0x3)
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#define PCI_DATA_LO16_MASK (0xffff)
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#define PCI_DATA_HI16_MASK (0xffff0000)
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#define PCI_DATA_HI16_SHIFT (16)
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#ifndef PCI_MMIO32_BASE
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#define PCI_MMIO32_BASE 0x80000000
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#endif /* PCI_MMIO32_BASE */
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#ifndef PCI_IO32_BASE
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#define PCI_IO32_BASE 0x2000
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#endif /* PCI_IO32_BASE */
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#define PCI_ENUM_MAX_DEV 32
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#define PCI_ENUM_MAX_FUN 8
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#define PCI_ENUM_MAX_BARS 6
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#define PCI_ENUM_MMIND_MASK (0x1)
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#define PCI_ENUM_TYPE_MASK (0x1 << 1 | 0x1 << 2)
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#define PCI_ENUM_TYPE_SHIFT 1
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#define PCI_ENUM_TYPE_64bit (0x1 << 1)
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#define PCI_ENUM_TYPE_32bit (0x1)
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#define PCI_ENUM_MM_BAR_MASK ~(0xf)
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#define PCI_ENUM_IO_BAR_MASK ~(0x3)
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#ifdef PCH_HAS_PCR
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static uint32_t pch_make_address(uint8_t port_id, uint16_t offset)
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{
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return (PCH_PCR_BASE + (port_id << 16 | offset));
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}
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uint32_t pch_read32(uint8_t port_id, uint16_t offset)
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{
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return mmio_read32(pch_make_address(port_id, offset));
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}
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void pch_write32(uint8_t port_id, uint16_t offset, uint32_t val)
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{
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mmio_write32(pch_make_address(port_id, offset), val);
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}
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#endif /* PCH_HAS_PCR */
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static uint32_t pci_align32_address(uint32_t addr, int *aligned)
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{
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*aligned = !(addr & PCI_ADDR_32BIT_ALIGNED_MASK);
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return (addr & ~(PCI_ADDR_32BIT_ALIGNED_MASK));
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}
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#ifdef PCI_USE_ECAM
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static uint32_t pci_config_ecam_make_address(uint8_t bus, uint8_t dev,
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uint8_t func, uint8_t off)
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{
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return (PCI_ECAM_BASE +
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((bus&0xff) << 20) |
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((dev&0x1f) << 15) |
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((func&0x07) << 12) |
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(off & 0xfff));
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}
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static uint32_t pci_ecam_config_read32(uint8_t bus, uint8_t dev, uint8_t fun,
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uint8_t off)
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{
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return mmio_read32(pci_config_ecam_make_address(bus, dev, fun, off));
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}
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static void pci_ecam_config_write32(uint8_t bus, uint8_t dev, uint8_t fun,
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uint8_t off, uint32_t value)
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{
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mmio_write32(pci_config_ecam_make_address(bus, dev, fun, off), value);
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}
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static uint16_t pci_ecam_config_read16(uint8_t bus, uint8_t dev, uint8_t fun,
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uint8_t off)
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{
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uint32_t addr;
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uint32_t data;
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int aligned32;
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addr = pci_config_ecam_make_address(bus, dev, fun, off);
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addr = pci_align32_address(addr, &aligned32);
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data = mmio_read32(addr);
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if (aligned32)
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data = data & PCI_DATA_LO16_MASK;
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else
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data = data >> PCI_DATA_HI16_SHIFT;
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return (uint16_t)data;
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}
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static void pci_ecam_config_write16(uint8_t bus, uint8_t dev, uint8_t fun,
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uint8_t off, uint16_t value)
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{
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uint32_t addr;
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int aligned32;
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uint32_t reg;
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addr = pci_config_ecam_make_address(bus, dev, fun, off);
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addr = pci_align32_address(addr, &aligned32);
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reg = mmio_read32(addr);
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if (aligned32)
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reg = (reg & PCI_DATA_HI16_MASK) | value;
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else
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reg = (reg & PCI_DATA_LO16_MASK) | (value << PCI_DATA_HI16_SHIFT);
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mmio_write32(addr, reg);
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}
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#else
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#define PCI_CONFIG_ADDR_PORT 0xcf8
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#define PCI_CONFIG_DATA_PORT 0xcfc
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/* Shifts & masks for CONFIG_ADDRESS register */
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#define PCI_CONFIG_ADDRESS_ENABLE_BIT_SHIFT 31
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#define PCI_CONFIG_ADDRESS_BUS_SHIFT 16
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#define PCI_CONFIG_ADDRESS_DEVICE_SHIFT 11
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#define PCI_CONFIG_ADDRESS_FUNCTION_SHIFT 8
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#define PCI_CONFIG_ADDRESS_OFFSET_MASK 0xFF
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#define PCI_IO_CONFIG_ADDR(bus, dev, fn, off) \
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(uint32_t)( \
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(1 << PCI_CONFIG_ADDRESS_ENABLE_BIT_SHIFT) | \
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(bus << PCI_CONFIG_ADDRESS_BUS_SHIFT) | \
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(dev << PCI_CONFIG_ADDRESS_DEVICE_SHIFT) | \
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(fn << PCI_CONFIG_ADDRESS_FUNCTION_SHIFT) | \
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(off & PCI_CONFIG_ADDRESS_OFFSET_MASK))
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static uint32_t pci_io_config_read32(uint32_t bus, uint32_t dev, uint32_t func,
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uint32_t off)
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{
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uint32_t address = PCI_IO_CONFIG_ADDR(bus, dev, func, off);
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uint32_t data = 0xffffffff;
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io_write32((uint16_t)PCI_CONFIG_ADDR_PORT, address);
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data = io_read32(PCI_CONFIG_DATA_PORT);
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return data;
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}
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static void pci_io_config_write32(uint32_t bus, uint32_t dev, uint32_t func,
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uint32_t off, uint32_t val)
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{
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uint32_t dst_addr = PCI_IO_CONFIG_ADDR(bus, dev, func, off);
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io_write32(PCI_CONFIG_ADDR_PORT, dst_addr);
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io_write32(PCI_CONFIG_DATA_PORT, val);
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}
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static uint16_t pci_io_config_read16(uint32_t bus, uint32_t dev, uint32_t func,
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uint32_t off)
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{
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uint32_t address = PCI_IO_CONFIG_ADDR(bus, dev, func, off);
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uint32_t data = 0xffff;
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int aligned32;
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/* off must be 16 bit aligned */
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if ((address & PCI_ADDR_16BIT_ALIGNED_MASK) != 0)
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return data;
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address = pci_align32_address(address, &aligned32);
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data = pci_io_config_read32(bus, dev, func, address);
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if (!aligned32)
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data >>= PCI_DATA_HI16_SHIFT;
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else
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data &= PCI_DATA_LO16_MASK;
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return (uint16_t)data;
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}
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static void pci_io_config_write16(uint32_t bus, uint32_t dev, uint32_t func,
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uint32_t off, uint16_t val)
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{
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uint32_t dst_addr = PCI_IO_CONFIG_ADDR(bus, dev, func, off);
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uint32_t reg;
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int aligned32;
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/* off must be 16 bit aligned */
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if ((dst_addr & PCI_ADDR_16BIT_ALIGNED_MASK) != 0)
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return;
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dst_addr = pci_align32_address(dst_addr, &aligned32);
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reg = pci_io_config_read32(bus, dev, func, dst_addr);
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if (aligned32) {
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reg &= PCI_DATA_HI16_MASK;
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reg |= val;
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} else {
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reg &= PCI_DATA_LO16_MASK;
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reg |= (val << PCI_DATA_HI16_SHIFT);
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}
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pci_io_config_write32(bus, dev, func, dst_addr, reg);
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}
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#endif /* PCI_USE_ECAM */
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uint32_t pci_config_read32(uint8_t bus, uint8_t dev, uint8_t fun, uint8_t off)
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{
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#ifdef PCI_USE_ECAM
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return pci_ecam_config_read32(bus, dev, fun, off);
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#else
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return pci_io_config_read32(bus, dev, fun, off);
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#endif /* PCI_HAS_ECAM */
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}
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void pci_config_write32(uint8_t bus,
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uint8_t dev, uint8_t fun, uint8_t off, uint32_t value)
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{
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#ifdef PCI_USE_ECAM
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pci_ecam_config_write32(bus, dev, fun, off, value);
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#else
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pci_io_config_write32(bus, dev, fun, off, value);
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#endif /* PCI_HAS_ECAM */
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}
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uint16_t pci_config_read16(uint8_t bus, uint8_t dev, uint8_t fun, uint8_t off)
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{
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#ifdef PCI_USE_ECAM
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return pci_ecam_config_read16(bus, dev, fun, off);
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#else
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return pci_io_config_read16(bus, dev, fun, off);
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#endif /* PCI_HAS_ECAM */
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}
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void pci_config_write16(uint8_t bus,
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uint8_t dev, uint8_t fun, uint8_t off, uint16_t value)
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{
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#ifdef PCI_USE_ECAM
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pci_ecam_config_write16(bus, dev, fun, off, value);
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#else
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pci_io_config_write16(bus, dev, fun, off, value);
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#endif /* PCI_HAS_ECAM */
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}
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static int pci_enum_is_64bit(uint32_t value)
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{
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uint8_t type = (value & PCI_ENUM_TYPE_MASK) >> PCI_ENUM_TYPE_SHIFT;
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return type == PCI_ENUM_TYPE_64bit;
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}
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static int pci_enum_is_mmio(uint32_t value)
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{
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return (value & PCI_ENUM_MMIND_MASK) == 0;
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}
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static int pci_enum_next_aligned32(uint32_t address, uint32_t *next,
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uint32_t align)
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{
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uintptr_t addr;
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addr = (uintptr_t)address;
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align = align-1;
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addr = (addr + align) & (~align);
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if (addr > 0xffffffff)
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return -1;
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if (addr < (uintptr_t)address)
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return -1;
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*next = (uint32_t)addr;
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return 0;
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}
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static int pci_pre_enum_cb(uint8_t bus, uint8_t dev, uint8_t fun)
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{
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#ifdef WOLFBOOT_TGL
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if (bus != 0)
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return 0;
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if (dev == 0x1e) {
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return 1;
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}
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/* PMC BARs shouldn't be programmed as per FSP integration guide */
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if (dev == 31 && fun == 2)
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return 1;
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#endif /* WOLFBOOT_TGL */
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return 0;
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}
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static int pci_post_enum_cb(uint8_t bus, uint8_t dev, uint8_t fun)
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{
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(void)bus;
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(void)dev;
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(void)fun;
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return 0;
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}
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static int pci_program_bar(uint8_t bus, uint8_t dev, uint8_t fun,
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uint8_t bar_idx,
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uint32_t *mm_base_ptr,
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uint32_t *io_base_ptr,
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uint8_t *is_64bit)
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{
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uint32_t bar_align, bar_value;
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uint32_t orig_bar, orig_bar2;
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uint32_t length, align;
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uint8_t bar_off;
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uint32_t *base;
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uint32_t reg;
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int is_mmio;
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int ret = 0;
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*is_64bit = 0;
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if (bar_idx >= PCI_ENUM_MAX_BARS)
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return -1;
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bar_off = PCI_BAR0_OFFSET + bar_idx * 4;
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orig_bar = pci_config_read32(bus, dev, fun, bar_off);
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pci_config_write32(bus, dev, fun, bar_off, 0xffffffff);
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bar_value = pci_config_read32(bus, dev,fun, bar_off);
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PCI_DEBUG_PRINTF("bar value: 0x%x\r\n", bar_value);
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if (bar_value == 0) {
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PCI_DEBUG_PRINTF("PCI enum: %x:%x.%x bar: %d val: %x - skipping\r\n",
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bus, dev, fun, bar_idx, bar_value);
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goto restore_bar;
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}
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is_mmio = pci_enum_is_mmio(bar_value);
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if (is_mmio) {
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bar_align = bar_value & PCI_ENUM_MM_BAR_MASK;
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base = mm_base_ptr;
|
||||
if (pci_enum_is_64bit((uint32_t)bar_value)) {
|
||||
PCI_DEBUG_PRINTF("bar is 64bit\r\n");
|
||||
orig_bar2 = pci_config_read32(bus, dev, fun, bar_off + 4);
|
||||
pci_config_write32(bus, dev, fun, bar_off + 4, 0xffffffff);
|
||||
reg = pci_config_read32(bus, dev, fun, bar_off + 4);
|
||||
PCI_DEBUG_PRINTF("bar high 32bit: %d\r\n", reg);
|
||||
if (reg != 0xffffffff) {
|
||||
PCI_DEBUG_PRINTF("Too big BAR, skipping\r\n");
|
||||
pci_config_write32(bus, dev, fun, bar_off + 4, orig_bar2);
|
||||
goto restore_bar;
|
||||
}
|
||||
*is_64bit = 1;
|
||||
}
|
||||
} else {
|
||||
bar_align = bar_value & PCI_ENUM_IO_BAR_MASK;
|
||||
/* when io has high 16 bits to zero, cosider them all ones (ref
|
||||
* spec.) */
|
||||
if ((bar_align & PCI_DATA_HI16_MASK) == 0)
|
||||
bar_align |= PCI_DATA_HI16_MASK;
|
||||
base = io_base_ptr;
|
||||
}
|
||||
|
||||
PCI_DEBUG_PRINTF("PCI enum: %s %x:%x.%x bar: %d val: %x (%s)\r\n",
|
||||
(is_mmio ? "mm" : "io"), bus, dev, fun, bar_idx,
|
||||
(uint32_t)bar_value, *is_64bit ? "64bit" : "");
|
||||
align = length = (~bar_align) + 1;
|
||||
/* force pci address to be on page boundary */
|
||||
if (align < 0x1000)
|
||||
align = 0x1000;
|
||||
|
||||
/* check max length */
|
||||
ret = pci_enum_next_aligned32(*base, &bar_value, align);
|
||||
if (ret != 0)
|
||||
goto restore_bar;
|
||||
|
||||
pci_config_write32(bus, dev, fun, bar_off, bar_value);
|
||||
if (*is_64bit)
|
||||
pci_config_write32(bus, dev, fun, bar_off + 4, 0x0);
|
||||
*base = bar_value + length;
|
||||
PCI_DEBUG_PRINTF("PCI enum: %s bus: %x:%x.%x bar: %d [%x,%x] (%x %s)\r\n",
|
||||
(is_mmio ? "mm" : "io"), bus, dev, fun, bar_idx, bar_value,
|
||||
bar_value + length, length, (*is_64bit) ? "64bit" : "");
|
||||
|
||||
return 0;
|
||||
|
||||
restore_bar:
|
||||
pci_config_write32(bus, dev, fun, bar_idx, orig_bar);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void pci_dump_id(uint8_t bus, uint8_t dev, uint8_t fun)
|
||||
{
|
||||
uint16_t vid, did;
|
||||
|
||||
vid = pci_config_read16(bus, dev, fun, PCI_VENDOR_ID_OFFSET);
|
||||
did = pci_config_read16(bus, dev, fun, PCI_DEVICE_ID_OFFSET);
|
||||
|
||||
PCI_DEBUG_PRINTF("PCI enum: dev: %x:%x.%x vid: %x did: %x\r\n",
|
||||
bus, dev, fun, (int)vid, (int)did);
|
||||
}
|
||||
|
||||
static int pci_program_bars(uint8_t bus, uint8_t dev, uint8_t fun,
|
||||
uint32_t *mm_base_ptr, uint32_t *io_base_ptr)
|
||||
{
|
||||
uint32_t orig_cmd;
|
||||
uint8_t is64bit;
|
||||
int _bar_idx;
|
||||
int ret;
|
||||
|
||||
orig_cmd = pci_config_read16(bus, dev, fun, PCI_COMMAND_OFFSET);
|
||||
pci_config_write16(bus, dev, fun, PCI_COMMAND_OFFSET, 0);
|
||||
|
||||
for (_bar_idx = 0; _bar_idx < PCI_ENUM_MAX_BARS; _bar_idx++) {
|
||||
ret = pci_program_bar(bus, dev, fun, _bar_idx, mm_base_ptr,
|
||||
io_base_ptr, &is64bit);
|
||||
if (ret != 0)
|
||||
break;
|
||||
|
||||
/* 64bit BAR uses two consecutive BAR registers */
|
||||
if (is64bit)
|
||||
_bar_idx++;
|
||||
}
|
||||
|
||||
pci_config_write16(bus, dev, fun, PCI_COMMAND_OFFSET, orig_cmd);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static uint32_t pci_enum_bus(uint8_t bus, uint32_t *pci_base, uint32_t *io_base)
|
||||
{
|
||||
uint16_t vendor_id, device_id, header_type;
|
||||
uint32_t vd_code, reg;
|
||||
uint32_t dev, fun;
|
||||
int ret;
|
||||
|
||||
for (dev = 0; dev < PCI_ENUM_MAX_DEV; dev++) {
|
||||
|
||||
vd_code = pci_config_read32(bus, dev, 0, 0x0);
|
||||
if (vd_code == 0xFFFFFFFF) {
|
||||
/* No device here. */
|
||||
continue;
|
||||
}
|
||||
|
||||
for (fun = 0; fun < PCI_ENUM_MAX_FUN; fun++) {
|
||||
if (pci_pre_enum_cb(bus, dev, fun))
|
||||
continue;
|
||||
|
||||
vd_code = pci_config_read32(bus, dev, fun, PCI_VENDOR_ID_OFFSET);
|
||||
if (vd_code == 0xFFFFFFFF) {
|
||||
/* No device here, try next function*/
|
||||
continue;
|
||||
}
|
||||
header_type = pci_config_read16(bus, dev, fun,
|
||||
PCI_HEADER_TYPE_OFFSET);
|
||||
pci_dump_id(bus, dev, fun);
|
||||
if ((header_type & PCI_HEADER_TYPE_TYPE_MASK) != 0) {
|
||||
PCI_DEBUG_PRINTF("not a general device: %, skipping\r\n",
|
||||
header_type);
|
||||
continue;
|
||||
}
|
||||
pci_program_bars(bus, dev, fun, pci_base, io_base);
|
||||
pci_post_enum_cb(bus, dev, fun);
|
||||
/* just one function */
|
||||
if (!(header_type & PCI_HEADER_TYPE_MULTIFUNC_MASK))
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int pci_enum_do()
|
||||
{
|
||||
uint32_t pci_base = PCI_MMIO32_BASE;
|
||||
uint32_t io_base = PCI_IO32_BASE;
|
||||
/* bus 0 only supported */
|
||||
return pci_enum_bus(0, &pci_base, &io_base);
|
||||
}
|
||||
Loading…
Reference in New Issue