mirror of https://github.com/wolfSSL/wolfBoot.git
Fixes for QSPI read. Adds alternate byte support. Cleanup of simple QSPI read/write.
David Garske
parent
c3cf21a81f
commit
8d7d4d4f74
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@ -194,69 +194,61 @@ static void RAMFUNCTION spi_reset(void)
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}
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#ifdef QSPI_FLASH
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int qspi_transfer(
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const uint8_t cmd, uint32_t addr, uint32_t addrSz,
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const uint8_t* txData, uint32_t txSz,
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uint8_t* rxData, uint32_t rxSz, uint32_t dummySz,
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uint32_t mode)
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int qspi_transfer(uint8_t fmode, const uint8_t cmd,
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uint32_t addr, uint32_t addrSz, uint32_t addrMode,
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uint32_t alt, uint32_t altSz, uint32_t altMode,
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uint32_t dummySz,
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uint8_t* data, uint32_t dataSz, uint32_t dataMode)
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{
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uint32_t fmode = 0, amode = 0;
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uint32_t adsz = 0, dsz = 0;
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uint8_t* dptr = NULL;
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uint32_t adsz = 0, absz = 0;
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if (txData != NULL && txSz > 0) {
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fmode = 0; /* indirect write */
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dsz = txSz;
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dptr = (uint8_t*)txData;
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if (addrSz > 0) {
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adsz = addrSz-1;
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}
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else if (rxData != NULL && rxSz > 0) {
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fmode = 1; /* indirect read */
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dsz = rxSz;
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dptr = rxData;
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}
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else {
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mode = 0; /* no data */
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if (altSz > 0) {
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absz = altSz-1;
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}
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/* Enable the QSPI peripheral */
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QUADSPI_CR |= QUADSPI_CR_EN;
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if (dsz > 0) {
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QUADSPI_DLR = dsz-1;
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}
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if (addrSz > 0) {
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amode = 1;
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adsz = addrSz-1;
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if (dataSz > 0) {
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QUADSPI_DLR = dataSz-1;
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}
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/* Configure QSPI: CCR register with all communications parameters */
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/* mode 1=1SPI, 2=2SPI, 3=4SPI */
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QUADSPI_CCR = (
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QUADSPI_CCR_FMODE(fmode) | /* Functional Mode */
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QUADSPI_CCR_IMODE(1) | /* Instruction Mode */
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QUADSPI_CCR_ADMODE(amode) | /* Address Mode */
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QUADSPI_CCR_ADSIZE(adsz) | /* Address Size */
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QUADSPI_CCR_ABMODE(0) | /* Alternate byte (none) */
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QUADSPI_CCR_DMODE(mode) | /* Data Mode */
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QUADSPI_CCR_DCYC(dummySz) | /* Dummy Cycles (between instruction and read) */
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cmd /* Instruction / Command byte */
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QUADSPI_CCR_FMODE(fmode) | /* Functional Mode */
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QUADSPI_CCR_IMODE(1) | /* Instruction Mode - always single SPI */
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QUADSPI_CCR_ADMODE(addrMode) | /* Address Mode */
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QUADSPI_CCR_ADSIZE(adsz) | /* Address Size */
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QUADSPI_CCR_ABMODE(altMode) | /* Alternate byte mode */
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QUADSPI_CCR_ABSIZE(absz ) | /* Alternate byte size */
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QUADSPI_CCR_DMODE(dataMode) | /* Data Mode */
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QUADSPI_CCR_DCYC(dummySz) | /* Dummy Cycles (between instruction and read) */
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cmd /* Instruction / Command byte */
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);
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/* Set optional alternate bytes */
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if (altSz > 0) {
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QUADSPI_ABR = alt;
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}
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/* Set command address 4 or 3 byte */
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QUADSPI_AR = addr;
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while (dsz > 0U) {
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while (dataSz > 0U) {
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if (fmode == 0) {
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while ((QUADSPI_SR & QUADSPI_SR_FTF) == 0);
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QUADSPI_DR = *dptr;
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QUADSPI_DR = *data;
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}
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else {
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while ((QUADSPI_SR & (QUADSPI_SR_FTF | QUADSPI_SR_TCF)) == 0);
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*dptr = QUADSPI_DR;
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*data = QUADSPI_DR;
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}
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dsz--;
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dptr++;
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dataSz--;
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data++;
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}
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/* wait for transfer complete */
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@ -61,16 +61,21 @@ uint8_t spi_read(void);
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#ifdef QSPI_FLASH
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/* these are used in macro logic, so must be defines */
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#define QSPI_ADDR_MODE_SPI 1
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#define QSPI_ADDR_MODE_DSPI 2
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#define QSPI_ADDR_MODE_QSPI 3
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#define QSPI_MODE_WRITE 0
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#define QSPI_MODE_READ 1
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int qspi_transfer(
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const uint8_t cmd, uint32_t addr, uint32_t addrSz,
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const uint8_t* txData, uint32_t txSz,
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uint8_t* rxData, uint32_t rxSz, uint32_t dummySz,
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uint32_t mode);
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/* these are used in macro logic, so must be defines */
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#define QSPI_DATA_MODE_NONE 0
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#define QSPI_DATA_MODE_SPI 1
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#define QSPI_DATA_MODE_DSPI 2
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#define QSPI_DATA_MODE_QSPI 3
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int qspi_transfer(uint8_t fmode, const uint8_t cmd,
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uint32_t addr, uint32_t addrSz, uint32_t addrMode,
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uint32_t alt, uint32_t altSz, uint32_t altMode,
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uint32_t dummySz,
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uint8_t* data, uint32_t dataSz, uint32_t dataMode
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);
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#endif /* QSPI_FLASH */
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#endif /* SPI_FLASH || QSPI_FLASH */
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123
src/qspi_flash.c
123
src/qspi_flash.c
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@ -52,9 +52,10 @@
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#endif
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#define FLASH_NUM_SECTORS (FLASH_DEVICE_SIZE/FLASH_SECTOR_SIZE)
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/* QSPI Configuration - Use single/dual/quad mode for data transfers */
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#ifndef QSPI_ADDR_MODE
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#define QSPI_ADDR_MODE QSPI_ADDR_MODE_SPI
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#ifndef QSPI_DATA_MODE
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#define QSPI_DATA_MODE QSPI_DATA_MODE_SPI
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#endif
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#ifndef QSPI_ADDR_SZ
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#define QSPI_ADDR_SZ 3
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@ -63,7 +64,7 @@
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#define QSPI_DUMMY_READ 8 /* Number of dummy clock cycles for reads */
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#endif
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#ifndef QSPI_FLASH_READY_TRIES
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#define QSPI_FLASH_READY_TRIES 1000
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#define QSPI_FLASH_READY_TRIES 5000
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#endif
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@ -84,7 +85,7 @@
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#define FAST_READ_CMD 0x0BU
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#define DUAL_READ_CMD 0x3BU
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#define QUAD_READ_CMD 0x6BU
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#define QUAD_READ_CMD 0xEBU
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#define FAST_READ_4B_CMD 0x0CU
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#define DUAL_READ_4B_CMD 0x3CU
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#define QUAD_READ_4B_CMD 0x6CU
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@ -108,29 +109,37 @@
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#define FLASH_SR2_QE 0x02 /* 1=Quad Enable (QE) */
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/* Read Command */
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#if QSPI_ADDR_MODE == QSPI_ADDR_MODE_QSPI && QSPI_ADDR_SZ == 4
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#if QSPI_DATA_MODE == QSPI_DATA_MODE_QSPI && QSPI_ADDR_SZ == 4
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#define FLASH_READ_CMD QUAD_READ_4B_CMD
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#elif QSPI_ADDR_MODE == QSPI_ADDR_MODE_DSPI && QSPI_ADDR_SZ == 4
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#elif QSPI_DATA_MODE == QSPI_DATA_MODE_DSPI && QSPI_ADDR_SZ == 4
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#define FLASH_READ_CMD DUAL_READ_4B_CMD
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#elif QSPI_ADDR_SZ == 4
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#define FLASH_READ_CMD FAST_READ_4B_CMD
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#elif QSPI_ADDR_MODE == QSPI_ADDR_MODE_QSPI
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#elif QSPI_DATA_MODE == QSPI_DATA_MODE_QSPI
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#define FLASH_READ_CMD QUAD_READ_CMD
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#elif QSPI_ADDR_MODE == QSPI_ADDR_MODE_DSPI
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#undef QSPI_DUMMY_READ
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#define QSPI_DUMMY_READ 4
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#define QSPI_ADDR_MODE QSPI_DATA_MODE_QSPI
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#elif QSPI_DATA_MODE == QSPI_DATA_MODE_DSPI
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#define FLASH_READ_CMD DUAL_READ_CMD
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#else
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#define FLASH_READ_CMD FAST_READ_CMD
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#endif
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/* Write Command */
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#if QSPI_ADDR_MODE == QSPI_ADDR_MODE_QSPI
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#if QSPI_DATA_MODE == QSPI_DATA_MODE_QSPI
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#define FLASH_WRITE_CMD QUAD_PROG_CMD
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#elif QSPI_ADDR_MODE == QSPI_ADDR_MODE_DSPI
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#elif QSPI_DATA_MODE == QSPI_DATA_MODE_DSPI
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#define FLASH_WRITE_CMD DUAL_PROG_CMD
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#else
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#define FLASH_WRITE_CMD PAGE_PROG_CMD
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#endif
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/* default to single SPI mode for address */
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#ifndef QSPI_ADDR_MODE
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#define QSPI_ADDR_MODE QSPI_DATA_MODE_SPI
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#endif
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/* forward declarations */
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static int qspi_wait_ready(void);
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@ -139,6 +148,21 @@ static int qspi_status(uint8_t* status);
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static int test_flash(void);
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#endif
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static inline int qspi_command_simple(uint8_t fmode, uint8_t cmd,
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uint8_t* data, uint32_t dataSz)
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{
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uint32_t dmode = QSPI_DATA_MODE_NONE;
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if (dataSz > 0) {
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dmode = QSPI_DATA_MODE_SPI;
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}
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return qspi_transfer(fmode, cmd,
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0, 0, QSPI_DATA_MODE_NONE, /* Address */
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0, 0, QSPI_DATA_MODE_NONE, /* Alternate Bytes */
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0, /* Dummy Cycles */
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data, dataSz, dmode /* Data */
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);
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}
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static int qspi_flash_read_id(uint8_t* id, uint32_t idSz)
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{
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int ret;
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@ -146,12 +170,11 @@ static int qspi_flash_read_id(uint8_t* id, uint32_t idSz)
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uint32_t status = 0;
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memset(data, 0, sizeof(data));
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ret = qspi_transfer(READ_ID_CMD, 0, 0, NULL, 0, data, 3, 0,
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QSPI_ADDR_MODE_SPI);
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qspi_status((uint8_t*)&status);
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ret = qspi_command_simple(QSPI_MODE_READ, READ_ID_CMD, data, 3);
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#ifdef DEBUG_QSPI
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wolfBoot_printf("Flash ID (ret %d): 0x%x, status %x\n",
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ret, *((uint32_t*)data), status);
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wolfBoot_printf("Flash ID (ret %d): 0x%x\n",
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ret, *((uint32_t*)data));
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#endif
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/* optionally return id data */
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@ -171,8 +194,7 @@ static int qspi_write_enable(void)
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uint8_t status = 0;
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/* send write enable */
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ret = qspi_transfer(WRITE_ENABLE_CMD, 0, 0, NULL, 0, NULL, 0, 0,
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QSPI_ADDR_MODE_SPI);
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ret = qspi_command_simple(QSPI_MODE_WRITE, WRITE_ENABLE_CMD, NULL, 0);
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#if defined(DEBUG_QSPI) && DEBUG_QSPI > 1
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wolfBoot_printf("Write Enable: Ret %d\n", ret);
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#endif
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@ -203,8 +225,7 @@ static int qspi_write_enable(void)
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static int qspi_write_disable(void)
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{
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int ret = qspi_transfer(WRITE_DISABLE_CMD, 0, 0, NULL, 0, NULL, 0, 0,
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QSPI_ADDR_MODE_SPI);
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int ret = qspi_command_simple(QSPI_MODE_WRITE, WRITE_DISABLE_CMD, NULL, 0);
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#if defined(DEBUG_QSPI) && DEBUG_QSPI > 1
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wolfBoot_printf("Write Disable: Ret %d\n", ret);
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#endif
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@ -220,8 +241,7 @@ static int qspi_status(uint8_t* status)
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#endif
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memset(data, 0, sizeof(data));
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ret = qspi_transfer(READ_SR_CMD, 0, 0, NULL, 0, data, 1, 0,
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QSPI_ADDR_MODE_SPI);
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ret = qspi_command_simple(QSPI_MODE_READ, READ_SR_CMD, data, 1);
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#if defined(DEBUG_QSPI) && DEBUG_QSPI > 1
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if (status == NULL || last_status != data[0]) {
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wolfBoot_printf("Status (ret %d): %02x -> %02x\n",
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@ -255,25 +275,24 @@ static int qspi_wait_ready(void)
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return -1;
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}
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#if QSPI_ADDR_MODE == QSPI_ADDR_MODE_QSPI
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#if QSPI_DATA_MODE == QSPI_DATA_MODE_QSPI
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static int qspi_quad_enable(void)
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{
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int ret;
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uint8_t data[4]; /* size multiple of uint32_t */
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memset(data, 0, sizeof(data));
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ret = qspi_transfer(READ_SR2_CMD, 0, 0, NULL, 0, data, 1, 0,
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QSPI_ADDR_MODE_SPI);
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ret = qspi_command_simple(QSPI_MODE_READ, READ_SR2_CMD, data, 1);
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#ifdef DEBUG_QSPI
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wolfBoot_printf("Status Reg 2: Ret %d, 0x%x\n", ret, data[0]);
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wolfBoot_printf("Status Reg 2: Ret %d, 0x%x (Quad Enabled: %s)\n",
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ret, data[0], (data[0] & FLASH_SR2_QE) ? "Yes" : "No");
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#endif
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if (ret == 0 && (data[0] & FLASH_SR2_QE) == 0) {
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ret = qspi_write_enable();
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if (ret == 0) {
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memset(data, 0, sizeof(data));
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data[0] |= FLASH_SR2_QE;
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ret = qspi_transfer(WRITE_SR2_CMD, 0, 0, data, 1, NULL, 0, 0,
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QSPI_ADDR_MODE_SPI);
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ret = qspi_command_simple(QSPI_MODE_WRITE, WRITE_SR2_CMD, data, 1);
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#ifdef DEBUG_QSPI
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wolfBoot_printf("Setting Quad Enable: Ret %d, SR2 0x%x\n",
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ret, data[0]);
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@ -292,8 +311,7 @@ static int qspi_enter_4byte_addr(void)
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{
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int ret = qspi_write_enable();
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if (ret == 0) {
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ret = qspi_transfer(ENTER_4B_ADDR_MODE_CMD, 0, 0,
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NULL, 0, NULL, 0, 0, QSPI_ADDR_MODE_SPI);
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ret = qspi_command_simple(QSPI_MODE_WRITE, ENTER_4B_ADDR_MODE_CMD, NULL, 0);
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#ifdef DEBUG_QSPI
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wolfBoot_printf("Enter 4-byte address mode: Ret %d\n", ret);
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#endif
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@ -308,8 +326,7 @@ static int qspi_exit_4byte_addr(void)
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{
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int ret = qspi_write_enable();
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if (ret == 0) {
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ret = qspi_transfer(EXIT_4B_ADDR_MODE_CMD, 0, 0,
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NULL, 0, NULL, 0, 0, QSPI_ADDR_MODE_SPI);
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ret = qspi_command_simple(QSPI_MODE_WRITE, EXIT_4B_ADDR_MODE_CMD, NULL, 0);
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#ifdef DEBUG_QSPI
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wolfBoot_printf("Enter 4-byte address mode: Ret %d\n", ret);
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#endif
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@ -328,7 +345,7 @@ uint16_t spi_flash_probe(void)
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spi_init(0,0);
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qspi_flash_read_id(NULL, 0);
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#if QSPI_ADDR_MODE == QSPI_ADDR_MODE_QSPI
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#if QSPI_DATA_MODE == QSPI_DATA_MODE_QSPI
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qspi_quad_enable();
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#endif
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#if QSPI_ADDR_SZ == 4
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@ -351,8 +368,12 @@ int spi_flash_sector_erase(uint32_t address)
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ret = qspi_write_enable();
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if (ret == 0) {
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/* ------ Erase Flash ------ */
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ret = qspi_transfer(SEC_ERASE_CMD, address, QSPI_ADDR_SZ,
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NULL, 0, NULL, 0, 0, QSPI_ADDR_MODE_SPI);
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ret = qspi_transfer(QSPI_MODE_WRITE, SEC_ERASE_CMD,
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address, QSPI_ADDR_SZ, QSPI_DATA_MODE_SPI, /* Address */
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0, 0, QSPI_DATA_MODE_NONE, /* Alternate Bytes */
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0, /* Dummy */
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NULL, 0, QSPI_DATA_MODE_NONE /* Data */
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);
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#ifdef DEBUG_QSPI
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wolfBoot_printf("Flash Erase: Ret %d, Address 0x%x\n", ret, address);
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#endif
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@ -367,6 +388,15 @@ int spi_flash_sector_erase(uint32_t address)
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int spi_flash_read(uint32_t address, void *data, int len)
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{
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int ret;
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#if QSPI_DATA_MODE == QSPI_DATA_MODE_QSPI
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const uint32_t altByte = 0xF0; /* enable continuous read */
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uint32_t altSz = 1;
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uint32_t altMode = QSPI_ADDR_MODE;
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#else
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const uint32_t altByte = 0x00;
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uint32_t altSz = 0;
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uint32_t altMode = QSPI_DATA_MODE_NONE;
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#endif
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if (address > FLASH_DEVICE_SIZE) {
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#ifdef DEBUG_QSPI
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@ -377,8 +407,13 @@ int spi_flash_read(uint32_t address, void *data, int len)
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}
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/* ------ Read Flash ------ */
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ret = qspi_transfer(FLASH_READ_CMD, address, QSPI_ADDR_SZ,
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NULL, 0, data, len, QSPI_DUMMY_READ, QSPI_ADDR_MODE);
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ret = qspi_transfer(QSPI_MODE_READ, FLASH_READ_CMD,
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address, QSPI_ADDR_SZ, QSPI_ADDR_MODE, /* Address */
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altByte, altSz, altMode, /* Alternate Bytes */
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QSPI_DUMMY_READ, /* Dummy */
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data, len, QSPI_DATA_MODE /* Data */
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);
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#ifdef DEBUG_QSPI
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wolfBoot_printf("Flash Read: Ret %d, Address 0x%x, Len %d, Cmd 0x%x\n",
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ret, address, len, FLASH_READ_CMD);
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@ -405,11 +440,15 @@ int spi_flash_write(uint32_t address, const void *data, int len)
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addr = address + (page * FLASH_PAGE_SIZE);
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/* ------ Write Flash (page at a time) ------ */
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ret = qspi_transfer(FLASH_WRITE_CMD, addr, QSPI_ADDR_SZ,
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(const uint8_t*)(data + (page * FLASH_PAGE_SIZE)), xferSz,
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NULL, 0, 0, QSPI_ADDR_MODE);
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ret = qspi_transfer(QSPI_MODE_WRITE, FLASH_WRITE_CMD,
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||||
addr, QSPI_ADDR_SZ, QSPI_DATA_MODE_SPI, /* Address */
|
||||
0, 0, QSPI_DATA_MODE_NONE, /* Alternate Bytes */
|
||||
0, /* Dummy */
|
||||
(uint8_t*)(data + (page * FLASH_PAGE_SIZE)),
|
||||
xferSz, QSPI_DATA_MODE /* Data */
|
||||
);
|
||||
#ifdef DEBUG_QSPI
|
||||
wolfBoot_printf("Flash Write: Ret %d, Address 0x%x, Len %d, Cmd 0x%x\n",
|
||||
wolfBoot_printf("Flash Write: Ret %d, Addr 0x%x, Len %d, Cmd 0x%x\n",
|
||||
ret, addr, xferSz, FLASH_WRITE_CMD);
|
||||
#endif
|
||||
if (ret != 0)
|
||||
|
|
@ -441,7 +480,9 @@ void spi_flash_release(void)
|
|||
|
||||
|
||||
#ifdef TEST_FLASH
|
||||
#define TEST_ADDRESS (2 * 1024 * 1024) /* 2MB */
|
||||
/* Start Address for test - 2MB */
|
||||
#define TEST_ADDRESS (2 * 1024 * 1024)
|
||||
|
||||
static int test_flash(void)
|
||||
{
|
||||
int ret;
|
||||
|
|
|
|||
Loading…
Reference in New Issue