Fixes for stm32u5, added workflow test

.github/workflows/trustzone-emulator-tests.yml

@@ -1,11 +1,11 @@
-name: emu-test-stm32h5
+name: trustzone-emulator-tests
 
 on:
   push:
   pull_request:
 
 jobs:
-  emu-test-stm32h5:
+  trustzone-emulator-tests:
     runs-on: ubuntu-latest
     container:
       image: ghcr.io/danielinux/m33mu-ci:testing
@@ -26,3 +26,14 @@ jobs:
         working-directory: test-app/emu-test-apps
         run: |
           SCENARIOS=C ./test.sh
+
+      - name: Clean and build stm32u5 (TZ + wolfcrypt)
+        run: |
+          make clean distclean
+          cp config/examples/stm32u5-wolfcrypt-tz.config .config
+          make wolfboot.bin
+
+      - name: Run emu test (stm32u5)
+        working-directory: test-app/emu-test-apps
+        run: |
+          TARGET=stm32u5 ./test.sh

hal/stm32_tz.c

@@ -29,7 +29,7 @@
     #include "hal/stm32u5.h"
 #endif
 
-#ifdef TARGET_stm32h5
+#if defined(TARGET_stm32h5)
     #include "hal/stm32h5.h"
 #endif
 
@@ -225,6 +225,38 @@ void hal_gtzc_init(void)
     }
 }
 
+#elif defined(TARGET_stm32u5)
+
+#define GTZC_MPCBB1_S_BASE        (0x50032C00)
+#define GTZC_MPCBB1_S_VCTR_BASE   (GTZC_MPCBB1_S_BASE + 0x100)
+
+#define GTZC_MPCBB2_S_BASE        (0x50033000)
+#define GTZC_MPCBB2_S_VCTR_BASE   (GTZC_MPCBB2_S_BASE + 0x100)
+
+#define SET_GTZC_MPCBBx_S_VCTR(bank,n,val) \
+    (*((volatile uint32_t *)(GTZC_MPCBB##bank##_S_VCTR_BASE ) + n ))= val
+
+void hal_gtzc_init(void)
+{
+   int i;
+   /* One bit in the bitmask: 512B (STM32U5) */
+
+   /* Configure SRAM1 lower 128 KB as secure (0x20000000 - 0x2001FFFF). */
+   for (i = 0; i < 8; i++) {
+       SET_GTZC_MPCBBx_S_VCTR(1, i, 0xFFFFFFFF);
+   }
+
+   /* Configure SRAM1 upper 128 KB as non-secure (0x20020000 - 0x2003FFFF). */
+   for (i = 8; i < 16; i++) {
+       SET_GTZC_MPCBBx_S_VCTR(1, i, 0x0);
+   }
+
+   /* Configure SRAM2 as non-secure (0x20030000 - 0x2003FFFF). */
+   for (i = 0; i < 4; i++) {
+       SET_GTZC_MPCBBx_S_VCTR(2, i, 0x0);
+   }
+}
+
 #else
 
 #define GTZC_MPCBB1_S_BASE        (0x50032C00)

hal/stm32u5.c

@@ -489,6 +489,35 @@ static void led_unsecure()
 #endif
 }
 
+#if TZ_SECURE()
+#define TZSC1_BASE 0x50032400u
+#define TZSC_SECCFGR1 (*(volatile uint32_t *)(TZSC1_BASE + 0x10u))
+#define TZSC_SECCFGR1_USART3SEC (1u << 10)
+
+static void periph_unsecure(void)
+{
+    volatile uint32_t reg;
+
+    /* Enable clock for GPIO D (USART3 pins PD8/PD9) */
+    RCC_AHB2ENR1_CLOCK_ER |= GPIOD_AHB2ENR1_CLOCK_ER;
+
+    /* Enable clock for USART3 */
+    RCC_APB1LENR |= (1u << 18);
+
+    /* Unsecure USART3 pins (PD8 TX, PD9 RX) */
+    GPIOD_SECCFGR &= ~(1u << 8);
+    GPIOD_SECCFGR &= ~(1u << 9);
+
+    /* Unsecure USART3 peripheral in GTZC TZSC */
+    reg = TZSC_SECCFGR1;
+    if (reg & TZSC_SECCFGR1_USART3SEC) {
+        reg &= ~TZSC_SECCFGR1_USART3SEC;
+        DMB();
+        TZSC_SECCFGR1 = reg;
+    }
+}
+#endif
+
 #if defined(DUALBANK_SWAP) && defined(__WOLFBOOT)
 static uint8_t bootloader_copy_mem[BOOTLOADER_SIZE];
 static void RAMFUNCTION fork_bootloader(void)
@@ -530,6 +559,7 @@ void hal_prepare_boot(void)
     clock_pll_off();
 #endif
 #if TZ_SECURE()
+    periph_unsecure();
     led_unsecure();
 #endif
 }

hal/stm32u5.h

@@ -119,6 +119,8 @@
 
 #define RCC_AHB3ENR             (*(volatile uint32_t *)(RCC_BASE + 0x94)) /* RM0456 - Table 108 */
 #define RCC_AHB3ENR_GTZC2EN     (1 << 12)
+
+#define RCC_APB1LENR            (*(volatile uint32_t *)(RCC_BASE + 0x9C)) /* RM0456 - Table 108 */
 #define RCC_AHB3ENR_PWREN       (1 << 2)
 
 #define RCC_ICSCR1             (*(volatile uint32_t *)(RCC_BASE + 0x08))
@@ -249,10 +251,12 @@
 
 /* GPIO*/
 #define GPIOC_BASE 0x52020800
+#define GPIOD_BASE 0x52020C00
 #define GPIOG_BASE 0x52021800
 #define GPIOH_BASE 0x52021C00
 
 #define GPIOC_SECCFGR (*(volatile uint32_t *)(GPIOC_BASE + 0x30))
+#define GPIOD_SECCFGR (*(volatile uint32_t *)(GPIOD_BASE + 0x30))
 #define GPIOG_SECCFGR (*(volatile uint32_t *)(GPIOG_BASE + 0x30))
 #define GPIOH_SECCFGR (*(volatile uint32_t *)(GPIOH_BASE + 0x30))
 
@@ -266,6 +270,7 @@
 
 #define RCC_AHB2ENR1_CLOCK_ER (*(volatile uint32_t *)(RCC_BASE + 0x8C ))
 #define GPIOC_AHB2ENR1_CLOCK_ER (1 << 2)
+#define GPIOD_AHB2ENR1_CLOCK_ER (1 << 3)
 #define GPIOG_AHB2ENR1_CLOCK_ER (1 << 6)
 #define GPIOH_AHB2ENR1_CLOCK_ER (1 << 7)
 #define TRNG_AHB2_CLOCK_ER      (1 << 18)

test-app/emu-test-apps/stm32u585/Makefile

@@ -1,13 +1,14 @@
 CC=arm-none-eabi-gcc
 OBJCOPY ?= arm-none-eabi-objcopy
 
-CFLAGS := -mcpu=cortex-m33 -mthumb -mcmse -Os -ffreestanding -fdata-sections -ffunction-sections -g -ggdb
+CFLAGS := -mcpu=cortex-m33 -mthumb -Os -ffreestanding -fdata-sections -ffunction-sections -g -ggdb
 CFLAGS += -I. -I../common -I../../../include -DEMU_STM32
 CFLAGS += -DIMAGE_HEADER_SIZE=$(IMAGE_HEADER_SIZE)
 LDFLAGS := -nostdlib -T target.ld -Wl,-gc-sections
 LDLIBS := -Wl,--start-group -lc -lm -lgcc -lnosys -Wl,--end-group
 NSC_OBJ :=
 ifeq ($(TZEN),1)
+  CFLAGS += -DNONSECURE_APP
   CFLAGS += -DWOLFCRYPT_SECURE_MODE
   NSC_OBJ := ../../../src/wc_secure_calls.o
 endif

test-app/emu-test-apps/stm32u585/target.ld

@@ -1,64 +1,61 @@
-/* Minimal linker script for STM32U585 memory map */
 MEMORY
 {
-    FLASH (rx)  : ORIGIN = 0x08000100, LENGTH = 0x001FFF00
-    RAM   (rwx) : ORIGIN = 0x20000000, LENGTH = 0x000C0000
+    FLASH (rx) : ORIGIN = 0x8040100, LENGTH = 0x1f700
+    RAM (rwx) : ORIGIN = 0x20020000, LENGTH = 128K
 }
 
-_estack = ORIGIN(RAM) + LENGTH(RAM);
-_sidata = LOADADDR(.data);
-
 SECTIONS
 {
-    .isr_vector :
-    {
-        KEEP(*(.isr_vector))
-    } > FLASH
-
     .text :
     {
+        _start_text = .;
+        . = ALIGN(8);
+        KEEP(*(.isr_vector))
+        . = ALIGN(8);
+        *(.init)
+        *(.fini)
         *(.text*)
         *(.rodata*)
-        *(.ARM.extab* .gnu.linkonce.armextab.*)
-        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
-        *(.glue_7)
-        *(.glue_7t)
-        *(.eh_frame)
+        . = ALIGN(8);
+        _end_text = .;
     } > FLASH
 
-    .preinit_array :
+    .edidx :
     {
-        __preinit_array_start = .;
-        KEEP(*(.preinit_array*))
-        __preinit_array_end = .;
+        . = ALIGN(4);
+        *(.ARM.exidx*)
     } > FLASH
 
-    .init_array :
-    {
-        __init_array_start = .;
-        KEEP(*(.init_array*))
-        __init_array_end = .;
-    } > FLASH
+    _stored_data = .;
 
-    .fini_array :
+    .data : AT (_stored_data)
     {
-        __fini_array_start = .;
-        KEEP(*(.fini_array*))
-        __fini_array_end = .;
-    } > FLASH
+        _start_data = .;
+        KEEP(*(.data*))
+        . = ALIGN(8);
+        KEEP(*(.ramcode))
+        . = ALIGN(8);
+        _end_data = .;
+    } > RAM
 
-    .data :
+    .bss :
     {
-        _sdata = .;
-        *(.data*)
-        _edata = .;
-    } > RAM AT > FLASH
-
-    .bss (NOLOAD) :
-    {
-        _sbss = .;
+        _start_bss = .;
         *(.bss*)
         *(COMMON)
-        _ebss = .;
+        . = ALIGN(8);
+        _end_bss = .;
+        _end = .;
     } > RAM
 }
+
+PROVIDE(_start_heap = _end);
+PROVIDE(_end_stack  = ORIGIN(RAM) + LENGTH(RAM));
+
+/* Emu app startup expects these symbols. */
+_estack = _end_stack;
+_sidata = _stored_data;
+_sdata = _start_data;
+_edata = _end_data;
+_sbss = _start_bss;
+_ebss = _end_bss;