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More fixes for aarch64 platforms.

pull/525/head
David Garske 2024-11-13 16:05:17 -08:00 committed by Daniele Lacamera
parent d6ca1e1a88
commit a07f3783b6
4 changed files with 16 additions and 8 deletions
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6
hal/nxp_ls1028a.c
View File

@ -1,4 +1,4 @@
/* ls1028a.c /* nxp_ls1028a.c
* *
* Copyright (C) 2024 wolfSSL Inc. * Copyright (C) 2024 wolfSSL Inc.
* *
@ -25,6 +25,8 @@
#include "image.h" #include "image.h"
#include "printf.h" #include "printf.h"
#ifdef TARGET_nxp_ls1028a
#ifndef ARCH_AARCH64 #ifndef ARCH_AARCH64
# error "wolfBoot ls1028a HAL: wrong architecture selected. Please compile with ARCH=AARCH64." # error "wolfBoot ls1028a HAL: wrong architecture selected. Please compile with ARCH=AARCH64."
#endif #endif
@ -877,3 +879,5 @@ void hal_init(void)
wolfBoot_printf("MMU init done\n"); wolfBoot_printf("MMU init done\n");
#endif #endif
} }
#endif /* TARGET_nxp_ls1028a */

2
hal/nxp_ls1028a.h
View File

@ -158,6 +158,8 @@
#define MMUTCB_COUNT (64) #define MMUTCB_COUNT (64)
#define MMUTCB_BASE(_n) (MMUTCB0_BASE + ((_n) % MMUTCB_COUNT) * MMUTCB_STRIDE) #define MMUTCB_BASE(_n) (MMUTCB0_BASE + ((_n) % MMUTCB_COUNT) * MMUTCB_STRIDE)
#define GICD_BASE (0x06000000ul) /* GIC-500 GICD */ #define GICD_BASE (0x06000000ul) /* GIC-500 GICD */
#define GICR_BASE (0x06100000ul)
#define GICC_BASE (0x01402000ul)
#define GITS_BASE (0x06020000ul) /* GIC-500 GITS Control */ #define GITS_BASE (0x06020000ul) /* GIC-500 GITS Control */
#define GITST_BASE (0x06030000ul) /* GIC-500 GITS Translation */ #define GITST_BASE (0x06030000ul) /* GIC-500 GITS Translation */
#define CPU0RD_BASE (0x06040000ul) /* CPU0 control, Locality Perif Int*/ #define CPU0RD_BASE (0x06040000ul) /* CPU0 control, Locality Perif Int*/

2
src/boot_aarch64.c
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@ -52,7 +52,7 @@ void boot_entry_C(void)
/* Copy data section from flash to RAM if necessary */ /* Copy data section from flash to RAM if necessary */
src = (unsigned int*)&_stored_data; src = (unsigned int*)&_stored_data;
dst = (unsigned int*)&_start_data; dst = (unsigned int*)&_start_data;
if(src!=dst) { if (src != dst) {
while (dst < (unsigned int *)&_end_data) { while (dst < (unsigned int *)&_end_data) {
*dst = *src; *dst = *src;
dst++; dst++;

14
src/boot_aarch64_start.S
View File

@ -65,13 +65,17 @@
/* GICv2 Register Offsets */ /* GICv2 Register Offsets */
#ifndef GICD_BASE
#define GICD_BASE 0xF9010000 #define GICD_BASE 0xF9010000
#endif
#define GICD_CTLR 0x0000 #define GICD_CTLR 0x0000
#define GICD_TYPER 0x0004 #define GICD_TYPER 0x0004
#define GICD_SGIR 0x0F00 #define GICD_SGIR 0x0F00
#define GICD_IGROUPRn 0x0080 #define GICD_IGROUPRn 0x0080
#ifndef GICC_BASE
#define GICC_BASE 0xF9020000 #define GICC_BASE 0xF9020000
#endif
#define GICC_PMR 0x0004 #define GICC_PMR 0x0004
.equ TZPCDECPROT0_SET_BASE, 0x02200804 .equ TZPCDECPROT0_SET_BASE, 0x02200804
@ -120,7 +124,7 @@ _vector_table:
8: mov sp, x1 // set stack pointer 8: mov sp, x1 // set stack pointer
#ifdef CPU_A72 #ifdef CORTEX_A72
bl init_A72 bl init_A72
#endif #endif
bl boot_entry_C // boot_entry_C never returns bl boot_entry_C // boot_entry_C never returns
@ -154,6 +158,7 @@ gicv2_init_secure:
ret ret
#ifdef CORTEX_A72
.global invalidate_ivac .global invalidate_ivac
invalidate_ivac: invalidate_ivac:
ldr x0, =_OCRAM_ADDRESS ldr x0, =_OCRAM_ADDRESS
@ -208,7 +213,6 @@ switch_el3_to_el2:
.global cortex_a72_erratta .global cortex_a72_erratta
cortex_a72_erratta: cortex_a72_erratta:
/* Initalization code for NXP LS1028a (A72) */ /* Initalization code for NXP LS1028a (A72) */
.global init_A72 .global init_A72
init_A72: init_A72:
@ -280,7 +284,6 @@ init_stack:
bl invalidate_ivac bl invalidate_ivac
b boot_entry_C b boot_entry_C
#ifdef TARGET_nxp_ls1028a
.global mmu_enable .global mmu_enable
mmu_enable: mmu_enable:
tlbi alle3 /* Invalidate table entries */ tlbi alle3 /* Invalidate table entries */
@ -318,7 +321,6 @@ mmu_enable:
dsb sy dsb sy
isb isb
ret ret
#endif
/* Exception Vector Table EL3 */ /* Exception Vector Table EL3 */
.balign 0x800 .balign 0x800
@ -390,7 +392,6 @@ PUT_64BIT_WORD \attr_hi, ((\PA) & 0xc0000000) | \attr_lo | 0x1
PUT_64BIT_WORD \attr_hi, ((\PA) & 0xffe00000) | \attr_lo | 0x1 PUT_64BIT_WORD \attr_hi, ((\PA) & 0xffe00000) | \attr_lo | 0x1
.endm .endm
#ifdef TARGET_nxp_ls1028a
/* Note: In EL3/2 has direct physical to virutal mapping */ /* Note: In EL3/2 has direct physical to virutal mapping */
.align 12 .align 12
.global ttb0_base .global ttb0_base
@ -407,4 +408,5 @@ level1_pagetable:
BLOCK_2MB (ADDR << 20), 0, 0x74c BLOCK_2MB (ADDR << 20), 0, 0x74c
.set ADDR, ADDR + 2 .set ADDR, ADDR + 2
.endr .endr
#endif
#endif /* CORTEX_A72 */