diff --git a/arch.mk b/arch.mk index 16f2c346..4ec0f97a 100644 --- a/arch.mk +++ b/arch.mk @@ -83,6 +83,17 @@ ifeq ($(ARCH),ARM) CORTEX_M0=1 SPI_TARGET=stm32 endif + + ifeq ($(TARGET),stm32c0) + CORTEX_M0=1 + ARCH_FLASH_OFFSET=0x08000000 + + # Enable this feature for secure memory support + # Makes the flash sectors for the bootloader unacessible from the application + # Requires using the STM32CubeProgrammer to set FLASH_SECR -> SEC_SIZE pages + CFLAGS+=-DFLASH_SECURABLE_MEMORY_SUPPORT + endif + ifeq ($(TARGET),stm32g0) CORTEX_M0=1 ARCH_FLASH_OFFSET=0x08000000 diff --git a/config/examples/stm32c0.config b/config/examples/stm32c0.config new file mode 100644 index 00000000..da041b21 --- /dev/null +++ b/config/examples/stm32c0.config @@ -0,0 +1,34 @@ +ARCH?=ARM +TARGET?=stm32c0 +SIGN?=ED25519 +#Using SHA384 with ED25519 saves about 2kB without SHA256 code +HASH?=SHA384 +DEBUG?=0 +VTOR?=1 +CORTEX_M0?=1 +NO_ASM?=0 +EXT_FLASH?=0 +SPI_FLASH?=0 +ALLOW_DOWNGRADE?=0 +NVM_FLASH_WRITEONCE?=1 +WOLFBOOT_VERSION?=0 +V?=0 +SPMATH?=1 +RAM_CODE?=1 +DUALBANK_SWAP?=0 +#Max APP size is 4kB +WOLFBOOT_PARTITION_SIZE?=0x2000 +WOLFBOOT_SECTOR_SIZE?=0x800 +#Max WOLFBOOT size is 14kB. Currently only 10kB +WOLFBOOT_PARTITION_BOOT_ADDRESS?=0x08003800 +WOLFBOOT_PARTITION_UPDATE_ADDRESS?=0x08005800 +WOLFBOOT_PARTITION_SWAP_ADDRESS?=0x08007800 + +#For a debug/not size optimized layout: +#DEBUG?=1 +#WOLFBOOT_PARTITION_SIZE?=0x1000 +#WOLFBOOT_SECTOR_SIZE?=0x800 +#WOLFBOOT_PARTITION_BOOT_ADDRESS?=0x08005800 +#WOLFBOOT_PARTITION_UPDATE_ADDRESS?=0x08006800 +#WOLFBOOT_PARTITION_SWAP_ADDRESS?=0x08007800 + diff --git a/docs/HAL.md b/docs/HAL.md index 2c84e90c..6a55292c 100644 --- a/docs/HAL.md +++ b/docs/HAL.md @@ -19,7 +19,7 @@ and RAM boundaries. ## Supported platforms The following platforms are supported in the current version: - - STM32F4, STM32L5, STM32L0, STM32F7, STM32H7, STM32G0 + - STM32F4, STM32L5, STM32L0, STM32F7, STM32H7, STM32G0, STM32C0 - nRF52 - Atmel samR21 - TI cc26x2 diff --git a/docs/Targets.md b/docs/Targets.md index 6a0b0e5d..45e22a8c 100644 --- a/docs/Targets.md +++ b/docs/Targets.md @@ -21,6 +21,7 @@ This README describes configuration of supported targets. * [STM32L4](#stm32l4) * [STM32L5](#stm32l5) * [STM32G0](#stm32g0) +* [STM32C0](#stm32c0) * [STM32H7](#stm32h7) * [STM32U5](#stm32u5) * [STM32WB55](#stm32wb55) @@ -424,6 +425,82 @@ add-symbol-file test-app/image.elf 0x08008100 mon reset init ``` +## STM32C0 + +Supports STM32C0x0/STM32C0x1. + +Example and instructions are for the STM Nucleo-C031C6 dev board using the +STM32Cube + +Example 32KB partitioning on STM32-G070: + +- Sector size: 2KB +- Wolfboot partition size: 14KB +- Application partition size: 8 KB +- Swap size 2KB + +```C +#define WOLFBOOT_SECTOR_SIZE 0x800 /* 2 KB */ +#define WOLFBOOT_PARTITION_BOOT_ADDRESS 0x08004000 /* offset 16kB to 24kB */ +#define WOLFBOOT_PARTITION_SIZE 0x2000 /* 8 KB */ +#define WOLFBOOT_PARTITION_UPDATE_ADDRESS 0x08006000 /* offset 24kB to 32kB */ +#define WOLFBOOT_PARTITION_SWAP_ADDRESS 0x08003800 /* offset 14kB to 16kB */ +``` + +### Building STM32C0 +xxx +Reference configuration (see [/config/examples/stm32g0.config](/config/examples/stm32g0.config)). +You can copy this to wolfBoot root as `.config`: `cp ./config/examples/stm32g0.config .config`. +To build you can use `make`. + +The TARGET for this is `stm32g0`: `make TARGET=stm32g0`. +The option `CORTEX_M0` is automatically selected for this target. +The option `NVM_FLASH_WRITEONCE=1` is mandatory on this target, since the IAP driver does not support +multiple writes after each erase operation. + +This target also supports secure memory protection on the bootloader region +using the `FLASH_CR:SEC_PROT` and `FLASH_SECT:SEC_SIZE` registers. This is the +number of 2KB pages to block access to from the 0x8000000 base address. + +``` +STM32_Programmer_CLI -c port=swd mode=hotplug -ob SEC_SIZE=0x10 +``` + +For RAMFUNCTION support (required for SEC_PROT) make sure `RAM_CODE=1`. + +### STM32C0 Programming +xxx +Compile requirements: `make TARGET=stm32g0 NVM_FLASH_WRITEONCE=1` + +The output is a single `factory.bin` that includes `wolfboot.bin` and `test-app/image_v1_signed.bin` combined together. +This should be programmed to the flash start address `0x08000000`. + +Flash using the STM32CubeProgrammer CLI: + +``` +STM32_Programmer_CLI -c port=swd -d factory.bin 0x08000000 +``` + +### STM32C0 Debugging +xxx +Use `make DEBUG=1` and program firmware again. + +Start GDB server on port 3333: + +``` +ST-LINK_gdbserver -d -e -r 1 -p 3333 +OR +st-util -p 3333 +``` + +wolfBoot has a .gdbinit to configure GDB + +``` +arm-none-eabi-gdb +add-symbol-file test-app/image.elf 0x08008100 +mon reset init +``` + ## STM32WB55 diff --git a/hal/stm32c0.c b/hal/stm32c0.c new file mode 100644 index 00000000..50706fff --- /dev/null +++ b/hal/stm32c0.c @@ -0,0 +1,373 @@ +/* stm32c0.c + * + * Copyright (C) 2023 wolfSSL Inc. + * + * This file is part of wolfBoot. + * + * wolfBoot is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * wolfBoot is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA + */ + +#include +#include + +#ifndef NVM_FLASH_WRITEONCE +# error "wolfBoot STM32C0 HAL: no WRITEONCE support detected. Please define NVM_FLASH_WRITEONCE" +#endif + +/* XXX Debug only! */ +#define NO_FLASH_SEC_SIZE_CHECK 1 + +/* STM32 C0 register configuration */ + +/* Assembly helpers */ +#define DMB() __asm__ volatile ("dmb") +#define ISB() __asm__ volatile ("isb") +#define DSB() __asm__ volatile ("dsb") + + +/*** RCC ***/ +#define RCC_BASE (0x40021000) +#define RCC_CR (*(volatile uint32_t *)(RCC_BASE + 0x00)) /* RM0444 - 5.4.1 */ +#define RCC_CFGR (*(volatile uint32_t *)(RCC_BASE + 0x08)) /* RM0444 - 5.4.3 */ +#define APB1_CLOCK_ER (*(volatile uint32_t *)(RCC_BASE + 0x3C)) +#define APB2_CLOCK_ER (*(volatile uint32_t *)(RCC_BASE + 0x40)) + + +#define RCC_CR_HSIRDY (1 << 10) +#define RCC_CR_HSION (1 << 8) + +#define RCC_CR_HSIDIV_SHIFT 11 +#define RCC_CR_HSIDIV_MASK 0x7 +#define RCC_CR_HSIDIV_1 (0ul << RCC_CR_HSIDIV_SHIFT) +#define RCC_CR_HSIDIV_2 (1ul << RCC_CR_HSIDIV_SHIFT) +#define RCC_CR_HSIDIV_4 (2ul << RCC_CR_HSIDIV_SHIFT) +#define RCC_CR_HSIDIV_8 (3ul << RCC_CR_HSIDIV_SHIFT) +#define RCC_CR_HSIDIV_16 (4ul << RCC_CR_HSIDIV_SHIFT) +#define RCC_CR_HSIDIV_32 (5ul << RCC_CR_HSIDIV_SHIFT) +#define RCC_CR_HSIDIV_64 (6ul << RCC_CR_HSIDIV_SHIFT) +#define RCC_CR_HSIDIV_128 (7ul << RCC_CR_HSIDIV_SHIFT) + + +#define RCC_CFGR_SW_HSISYS 0x0 +#define RCC_CFGR_SW_PLL 0x2 +#define RCC_PLLCFGR_PLLR_EN (1 << 28) /* RM0444 - 5.4.3 */ + +#define RCC_PLLCFGR_PLLSRC_HSI16 2 + + +/*** APB PRESCALER ***/ +#define RCC_PRESCALER_DIV_NONE 0 + +/*** FLASH ***/ +#define PWR_APB1_CLOCK_ER_VAL (1 << 28) +#define SYSCFG_APB2_CLOCK_ER_VAL (1 << 0) /* RM0444 - 5.4.15 - RCC_APBENR2 - SYSCFGEN */ + +#define FLASH_BASE (0x40022000) /*FLASH_R_BASE = 0x40000000UL + 0x00020000UL + 0x00002000UL */ +#define FLASH_ACR (*(volatile uint32_t *)(FLASH_BASE + 0x00)) /* RM0490 - 3.7.1 - FLASH_ACR */ +#define FLASH_KEY (*(volatile uint32_t *)(FLASH_BASE + 0x08)) /* RM0490 - 3.7.2 - FLASH_KEYR */ +#define FLASH_OPTKEY (*(volatile uint32_t *)(FLASH_BASE + 0x0C)) /* RM0490 - 3.7.3 - FLASH_OPTKEYR */ +#define FLASH_SR (*(volatile uint32_t *)(FLASH_BASE + 0x10)) /* RM0490 - 3.7.4 - FLASH_SR */ +#define FLASH_CR (*(volatile uint32_t *)(FLASH_BASE + 0x14)) /* RM0490 - 3.7.5 - FLASH_CR */ +#define FLASH_SECR (*(volatile uint32_t *)(FLASH_BASE + 0x80)) /* RM0490 - 3.7.13 - FLASH_SECR */ + +#define FLASHMEM_ADDRESS_SPACE (0x08000000) +#define FLASH_PAGE_SIZE (0x800) /* 2KB */ +#define FLASH_PAGE_SIZE_SHIFT 11 /* (1 << FLASH_PAGE_SIZE_SHIFT) == FLASH_PAGE_SIZE*/ + +/* Register values */ + +#define FLASH_ACR_LAT_SHIFT 0 /* RM0490 - 3.7.1 -FLASH_ACT */ +#define FLASH_ACR_LAT_MASK 0x01 /* RM0490 - 3.7.1 -FLASH_ACT */ + +#define FLASH_SR_BSY1 (1 << 16) /* RM0490 - 3.7.4 - FLASH_SR */ +#define FLASH_SR_SIZERR (1 << 6) /* RM0490 - 3.7.4 - FLASH_SR */ +#define FLASH_SR_PGAERR (1 << 5) /* RM0490 - 3.7.4 - FLASH_SR */ +#define FLASH_SR_WRPERR (1 << 4) /* RM0490 - 3.7.4 - FLASH_SR */ +#define FLASH_SR_PROGERR (1 << 3) /* RM0490 - 3.7.4 - FLASH_SR */ +#define FLASH_SR_EOP (1 << 0) /* RM0490 - 3.7.4 - FLASH_SR */ + +#define FLASH_CR_LOCK (1 << 31) /* RM0490 - 3.7.5 - FLASH_CR */ +#define FLASH_CR_STRT (1 << 16) /* RM0490 - 3.7.5 - FLASH_CR */ + +#define FLASH_CR_PER (1 << 1) /* RM0490 - 3.7.5 - FLASH_CR */ +#define FLASH_CR_PG (1 << 0) /* RM0490 - 3.7.5 - FLASH_CR */ +#define FLASH_CR_SEC_PROT (1 << 28) /* RM0490 - 3.7.5 - FLASH_CR */ + +#define FLASH_CR_PNB_SHIFT 3 /* RM0490 - 3.7.5 - FLASH_CR - PNB bits 8:3 */ +#define FLASH_CR_PNB_MASK 0x3f /* RM0490 - 3.7.5 - FLASH_CR - PNB bits 8:3 - 6 bits */ + +#define FLASH_SECR_SEC_SIZE_POS (0U) +#define FLASH_SECR_SEC_SIZE_MASK (0xFF) + +#define FLASH_KEY1 (0x45670123) +#define FLASH_KEY2 (0xCDEF89AB) + +#define FLASH_OPTKEY1 (0x08192A3B) +#define FLASH_OPTKEY2 (0x4C5D6E7F) + + +static void RAMFUNCTION flash_set_waitstates(unsigned int waitstates) +{ + uint32_t reg, mask_val, set_val; + reg = FLASH_ACR; + mask_val = FLASH_ACR_LAT_MASK << FLASH_ACR_LAT_SHIFT; + set_val = (waitstates << FLASH_ACR_LAT_SHIFT) & mask_val; + if ((reg & mask_val) != set_val) + FLASH_ACR = (reg & ~mask_val) | set_val; +} + +static RAMFUNCTION void flash_wait_complete(void) +{ + while ((FLASH_SR & FLASH_SR_BSY1) == FLASH_SR_BSY1) + ; +} + +static void RAMFUNCTION flash_clear_errors(void) +{ + /* Consider only writing here as there is no reason to read first (rc_w1), + * unless other error bits are set*/ + /* FLASH_SR = (FLASH_SR_SIZERR | FLASH_SR_PGAERR | FLASH_SR_WRPERR | + FLASH_SR_PROGERR); */ + FLASH_SR |= (FLASH_SR_SIZERR | FLASH_SR_PGAERR | FLASH_SR_WRPERR | + FLASH_SR_PROGERR); +} + +int RAMFUNCTION hal_flash_write(uint32_t address, const uint8_t *data, int len) +{ + int i = 0; + uint32_t *src, *dst; + flash_clear_errors(); + FLASH_CR |= FLASH_CR_PG; + + while (i < len) { + flash_clear_errors(); + if ((len - i > 3) && ((((address + i) & 0x07) == 0) && + ((((uint32_t)data) + i) & 0x07) == 0)) { + src = (uint32_t *)data; + dst = (uint32_t *)(address + FLASHMEM_ADDRESS_SPACE); + flash_wait_complete(); + dst[i >> 2] = src[i >> 2]; + dst[(i >> 2) + 1] = src[(i >> 2) + 1]; + flash_wait_complete(); + i+=8; + } else { + uint32_t val[2]; + uint8_t *vbytes = (uint8_t *)(val); + int off = (address + i) - (((address + i) >> 3) << 3); + uint32_t base_addr = address & (~0x07); /* aligned to 64 bit */ + int u32_idx = (i >> 2); + dst = (uint32_t *)(base_addr); + val[0] = dst[u32_idx]; + val[1] = dst[u32_idx + 1]; + while ((off < 8) && (i < len)) + vbytes[off++] = data[i++]; + dst[u32_idx] = val[0]; + dst[u32_idx + 1] = val[1]; + flash_wait_complete(); + } + } + if ((FLASH_SR & FLASH_SR_EOP) == FLASH_SR_EOP) + FLASH_SR |= FLASH_SR_EOP; + FLASH_CR &= ~FLASH_CR_PG; + return 0; +} + +void RAMFUNCTION hal_flash_unlock(void) +{ + flash_wait_complete(); + if ((FLASH_CR & FLASH_CR_LOCK) != 0) { + FLASH_KEY = FLASH_KEY1; + DMB(); + FLASH_KEY = FLASH_KEY2; + DMB(); + while ((FLASH_CR & FLASH_CR_LOCK) != 0) + ; + } +} + +void RAMFUNCTION hal_flash_lock(void) +{ + flash_wait_complete(); + if ((FLASH_CR & FLASH_CR_LOCK) == 0) + FLASH_CR |= FLASH_CR_LOCK; +} + + +int RAMFUNCTION hal_flash_erase(uint32_t address, int len) +{ + int start = -1, end = -1; + uint32_t end_address; + uint32_t p; + if (len == 0) + return -1; + end_address = address + len - 1; + for (p = address; p < end_address; p += FLASH_PAGE_SIZE) { + uint32_t reg = FLASH_CR & (~(FLASH_CR_PNB_MASK << FLASH_CR_PNB_SHIFT)); + FLASH_CR = reg | ((p >> FLASH_PAGE_SIZE_SHIFT) << FLASH_CR_PNB_SHIFT) | FLASH_CR_PER; + DMB(); + FLASH_CR |= FLASH_CR_STRT; + flash_wait_complete(); + FLASH_CR &= ~FLASH_CR_PER; + } + return 0; +} + +static void clock_pll_off(void) +{ + uint32_t reg32; + + /* Select HSISYS as SYSCLK source. */ + reg32 = RCC_CFGR; + reg32 &= ~((1 << 1) | (1 << 0)); + RCC_CFGR = (reg32 | RCC_CFGR_SW_HSISYS); + DMB(); +#if 0 + /* Turn off PLL */ + RCC_CR &= ~RCC_CR_PLLON; + DMB(); +#endif +} + +/* This implementation will setup HSI RC 48 MHz as System Clock Source, set + * flash wait state to 2, and set all peripherals to 16MHz (div4) + * + * */ +static void clock_pll_on(int powersave) +{ + uint32_t reg32; + uint32_t cpu_freq, plln, pllm, pllq, pllp, pllr, hpre, ppre, flash_waitstates; + + /* Enable Power controller */ + APB1_CLOCK_ER |= PWR_APB1_CLOCK_ER_VAL; + + /* Select clock parameters (CPU Speed = 48MHz) */ + cpu_freq = 48000000; + pllm = 4; + plln = 80; + pllp = 10; + pllq = 5; + pllr = 5; + hpre = RCC_PRESCALER_DIV_NONE; + ppre = RCC_PRESCALER_DIV_NONE; + flash_waitstates = 1; + + flash_set_waitstates(flash_waitstates); + + /* Enable internal high-speed oscillator. */ + RCC_CR |= RCC_CR_HSION; + DMB(); + while ((RCC_CR & RCC_CR_HSIRDY) == 0) {}; + + /* Select HSISYS as SYSCLK source. */ + reg32 = RCC_CFGR; + reg32 &= ~((1 << 1) | (1 << 0)); + RCC_CFGR = (reg32 | RCC_CFGR_SW_HSISYS); + DMB(); + + #if 0 + /* Disable PLL */ + RCC_CR &= ~RCC_CR_PLLON; + + /* Set prescalers for AHB, ADC, ABP1, ABP2. */ + reg32 = RCC_CFGR; + reg32 &= ~(0xF0); /* don't change bits [0-3] that were previously set */ + RCC_CFGR = (reg32 | (hpre << 8)); /* RM0444 - 5.4.3 - RCC_CFGR */ + DMB(); + reg32 = RCC_CFGR; + reg32 &= ~(0x1C00); /* don't change bits [0-14] */ + RCC_CFGR = (reg32 | (ppre << 12)); /* RM0444 - 5.4.3 - RCC_CFGR */ + DMB(); + + /* Set PLL config */ + reg32 = RCC_PLLCFGR; + reg32 |= RCC_PLLCFGR_PLLSRC_HSI16; + reg32 |= ((pllm - 1) << 4); + reg32 |= plln << 8; + reg32 |= ((pllp - 1) << 17); + reg32 |= ((pllr - 1) << 29); + RCC_PLLCFGR = reg32; + + DMB(); + /* Enable PLL oscillator and wait for it to stabilize. */ + RCC_PLLCFGR |= RCC_PLLCFGR_PLLR_EN; + RCC_CR |= RCC_CR_PLLON; + DMB(); + while ((RCC_CR & RCC_CR_PLLRDY) == 0) {}; + + /* Select PLL as SYSCLK source. */ + reg32 = RCC_CFGR; + reg32 &= ~((1 << 1) | (1 << 0)); + RCC_CFGR = (reg32 | RCC_CFGR_SW_PLL); + DMB(); + + /* Wait for PLL clock to be selected. */ + while ((RCC_CFGR & ((1 << 1) | (1 << 0))) != RCC_CFGR_SW_PLL) {}; +#endif + /* SYSCFG, COMP and VREFBUF clock enable */ + APB2_CLOCK_ER |= SYSCFG_APB2_CLOCK_ER_VAL; +} + +void hal_init(void) +{ + clock_pll_on(0); +} + +#ifdef FLASH_SECURABLE_MEMORY_SUPPORT +static void RAMFUNCTION do_secure_boot(void) +{ + uint32_t sec_size = (FLASH_SECR & FLASH_SECR_SEC_SIZE_MASK); + + /* The "SEC_SIZE" is the number of pages (2KB) to extend from base 0x8000000 + * and it is programmed using the STM32CubeProgrammer option bytes. + * Example: STM32_Programmer_CLI -c port=swd mode=hotplug -ob SEC_SIZE= */ +#ifndef NO_FLASH_SEC_SIZE_CHECK + /* Make sure at least the first sector is protected and the size is not + * larger than boot partition */ + if (sec_size <= 1 || + sec_size > (WOLFBOOT_PARTITION_BOOT_ADDRESS / WOLFBOOT_SECTOR_SIZE)) { + /* panic: invalid sector size */ + while(1) + ; + } +#endif + + /* TODO: Add checks for WRP, RDP and BootLock. Add warning to help lock down + * target in production */ + + /* unlock flash to access FLASH_CR write */ + hal_flash_unlock(); + + ISB(); + + /* Activate secure user memory */ + /* secure code to make sure SEC_PROT gets set (based on reference code) */ + do { + FLASH_CR |= FLASH_CR_SEC_PROT; + } while ((FLASH_CR & FLASH_CR_SEC_PROT) == 0); + + DSB(); +} +#endif + +void RAMFUNCTION hal_prepare_boot(void) +{ +#ifdef SPI_FLASH + spi_flash_release(); +#endif + clock_pll_off(); +#ifdef FLASH_SECURABLE_MEMORY_SUPPORT + do_secure_boot(); +#endif +} diff --git a/hal/stm32c0.ld b/hal/stm32c0.ld new file mode 100644 index 00000000..1e0ffc93 --- /dev/null +++ b/hal/stm32c0.ld @@ -0,0 +1,50 @@ +MEMORY +{ + FLASH (rx) : ORIGIN = 0x08000000, LENGTH = @BOOTLOADER_PARTITION_SIZE@ + RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00002FFF +} + +SECTIONS +{ + .text : + { + _start_text = .; + KEEP(*(.isr_vector)) + *(.text*) + *(.rodata*) + . = ALIGN(4); + _end_text = .; + } > FLASH + + .edidx : + { + . = ALIGN(4); + *(.ARM.exidx*) + } > FLASH + + _stored_data = .; + .data : AT (_stored_data) + { + _start_data = .; + KEEP(*(.data*)) + . = ALIGN(4); + KEEP(*(.ramcode)) + . = ALIGN(4); + _end_data = .; + } > RAM + + .bss (NOLOAD) : + { + _start_bss = .; + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + _end_bss = .; + __bss_end__ = .; + _end = .; + } > RAM + . = ALIGN(4); +} + +END_STACK = ORIGIN(RAM) + LENGTH(RAM); diff --git a/test-app/ARM-stm32c0.ld b/test-app/ARM-stm32c0.ld new file mode 100644 index 00000000..4645b8ea --- /dev/null +++ b/test-app/ARM-stm32c0.ld @@ -0,0 +1,50 @@ +MEMORY +{ + FLASH (rx) : ORIGIN = @WOLFBOOT_TEST_APP_ADDRESS@, LENGTH = @WOLFBOOT_TEST_APP_SIZE@ + RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 12K /* Run in lowmem */ +} + +SECTIONS +{ + .text : + { + _start_text = .; + KEEP(*(.isr_vector)) + *(.init) + *(.fini) + *(.text*) + KEEP(*(.rodata*)) + . = ALIGN(4); + _end_text = .; + } > FLASH + + _stored_data = .; + + .data : AT (_stored_data) + { + _start_data = .; + KEEP(*(.data*)) + . = ALIGN(4); + KEEP(*(.ramcode)) + . = ALIGN(4); + _end_data = .; + } > RAM + + .bss : + { + _start_bss = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + _end_bss = .; + _end = .; + } > RAM +} + +_wolfboot_partition_boot_address = @WOLFBOOT_PARTITION_BOOT_ADDRESS@; +_wolfboot_partition_size = @WOLFBOOT_PARTITION_SIZE@; +_wolfboot_partition_update_address = @WOLFBOOT_PARTITION_UPDATE_ADDRESS@; +_wolfboot_partition_swap_address = @WOLFBOOT_PARTITION_SWAP_ADDRESS@; + +PROVIDE(_start_heap = _end); +PROVIDE(_end_stack = ORIGIN(RAM) + LENGTH(RAM)); diff --git a/test-app/Makefile b/test-app/Makefile index eda4fd61..08aa1db1 100644 --- a/test-app/Makefile +++ b/test-app/Makefile @@ -119,6 +119,10 @@ ifeq ($(TARGET),stm32h7) LSCRIPT_TEMPLATE=ARM-stm32h7.ld endif +ifeq ($(TARGET),stm32c0) + LSCRIPT_TEMPLATE=ARM-stm32c0.ld +endif + ifeq ($(TARGET),stm32l4) APP_OBJS+=$(STM32CUBE)/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.o APP_OBJS+=$(STM32CUBE)/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.o diff --git a/test-app/app_stm32c0.c b/test-app/app_stm32c0.c new file mode 100644 index 00000000..97fcfce6 --- /dev/null +++ b/test-app/app_stm32c0.c @@ -0,0 +1,39 @@ +/* main.c + * + * Test bare-metal boot-led-on application + * + * Copyright (C) 2023 wolfSSL Inc. + * + * This file is part of wolfBoot. + * + * wolfBoot is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * wolfBoot is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA + */ + +#include +#include +#include +#include "led.h" +#include "wolfboot/wolfboot.h" + +#ifdef PLATFORM_stm32c0 + +void main(void) { + boot_led_on(); + /* Wait for reboot */ + while(1) + ; +} +#endif /* PLATFORM_stm32c0 */ + diff --git a/test-app/led.c b/test-app/led.c index 875a782a..f149dedf 100644 --- a/test-app/led.c +++ b/test-app/led.c @@ -146,6 +146,43 @@ void boot_led_on(void) #endif /** PLATFORM_stm32g0 **/ +#ifdef PLATFORM_stm32c0 +#include +#include "wolfboot/wolfboot.h" + + +/*GPIOA5 on Nucleo C031C6*/ +#define RCC_IOPENR (*(volatile uint32_t *)(0x40021034)) // 40021034 +#define RCC_IOPENR_GPIOAEN (1 << 0) + +#define GPIOA_BASE 0x50000000 +#define GPIOA_MODE (*(volatile uint32_t *)(GPIOA_BASE + 0x00)) +#define GPIOA_OTYPE (*(volatile uint32_t *)(GPIOA_BASE + 0x04)) +#define GPIOA_OSPD (*(volatile uint32_t *)(GPIOA_BASE + 0x08)) +#define GPIOA_PUPD (*(volatile uint32_t *)(GPIOA_BASE + 0x0c)) +#define GPIOA_ODR (*(volatile uint32_t *)(GPIOA_BASE + 0x14)) +#define GPIOA_BSRR (*(volatile uint32_t *)(GPIOA_BASE + 0x18)) +#define GPIOA_AFL (*(volatile uint32_t *)(GPIOA_BASE + 0x20)) +#define GPIOA_AFH (*(volatile uint32_t *)(GPIOA_BASE + 0x24)) +#define LED_PIN (5) +#define LED_BOOT_PIN (5) +#define GPIO_OSPEED_100MHZ (0x03) + +void boot_led_on(void) +{ + uint32_t reg; + uint32_t pin = LED_BOOT_PIN; + RCC_IOPENR |= RCC_IOPENR_GPIOAEN; + reg = GPIOA_MODE & ~(0x03 << (pin * 2)); + GPIOA_MODE = reg | (1 << (pin * 2)); // general purpose output mode + reg = GPIOA_PUPD & ~(0x03 << (pin * 2)); + GPIOA_PUPD = reg | (1 << (pin * 2)); // pull-up + GPIOA_BSRR |= (1 << pin); // set pin +} + +#endif /** PLATFORM_stm32c0 **/ + + #ifdef PLATFORM_stm32wb #define LED_BOOT_PIN (0) #define RCC_AHB2_CLOCK_ER (*(volatile uint32_t *)(0x5800004C))