From a63e1d96382d502c3ad324db6c7f32f7dfd61c49 Mon Sep 17 00:00:00 2001
From: Elms <jeff@wolfssl.com>
Date: Thu, 3 Jun 2021 21:38:06 -0700
Subject: [PATCH] docs: Add NXP T2080 PPC to documentation

---
 docs/Targets.md      | 16 ++++++++++++++--
 src/boot_ppc_start.S | 45 ++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 59 insertions(+), 2 deletions(-)

diff --git a/docs/Targets.md b/docs/Targets.md
index 91257a62..89f1c2d5 100644
--- a/docs/Targets.md
+++ b/docs/Targets.md
@@ -9,6 +9,7 @@ This README describes configuration of supported targets.
 * [NXP LPC54xxx](#nxp-lpc54xxx)
 * [NXP iMX-RT](#nxp-imx-rt)
 * [NXP Kinetis](#nxp-kinetis)
+* [NXP T2080 PPC](#nxp-t2080-ppc)
 * [SiFive HiFive1 RISC-V](#sifive-hifive1-risc-v)
 * [STM32F4](#stm32f4)
 * [STM32F7](#stm32f7)
@@ -19,7 +20,6 @@ This README describes configuration of supported targets.
 * [STM32WB55](#stm32wb55)
 * [Xilinx Zynq UltraScale](#xilinx-zynq-ultrascale)
 
-
 ## STM32F4
 
 Example 512KB partitioning on STM32-F407
@@ -765,7 +765,7 @@ Hardware acceleration is enable by default using psoc6 crypto hw support.
 
 To compile with hardware acceleration disabled, use the option
 
-``` PSOC6_CRYPTO=0 ```
+`PSOC6_CRYPTO=0`
 
 in your wolfBoot configuration.
 
@@ -862,3 +862,15 @@ WOLFBOOT_PARTITION_BOOT_ADDRESS?=0xA000
 WOLFBOOT_PARTITION_UPDATE_ADDRESS?=0x84000
 WOLFBOOT_PARTITION_SWAP_ADDRESS?=0xff000
 ```
+
+## NXP T2080 PPC
+
+The T2080 is a PPC e6500 based processor.
+
+Example configuration for this target is provided in [/config/examples/t2080.config](/config/examples/t2080.config).
+
+### Building wolfBoot
+
+wolfBoot can be built with gcc powerpc tools. For example, `apt
+install gcc-powerpc-linux-gnu`. Then make will use the correct tools
+to compile.
diff --git a/src/boot_ppc_start.S b/src/boot_ppc_start.S
index c1e12f91..eaf33d01 100644
--- a/src/boot_ppc_start.S
+++ b/src/boot_ppc_start.S
@@ -1,3 +1,48 @@
+/*
+# References
+CRM - e6500 Core Reference Manual, Rev 0
+EREF - EREF: A Programmer’s Reference Manual for Freescale Power Architecture Processors, Rev. 1 (EIS 2.1)
+T2080RM - QorIQ T2080 Reference Manual, Rev. 3, 11/2016
+MPC8544ERM - https://www.nxp.com/docs/en/reference-manual/MPC8544ERM.pdf
+
+## Early boot
+
+CRM chapter 11
+ * Save DBSR reset reason - probably not worth it. MRR in CRM 2.14.9
+ * Print CIR for info (alias to SVR)
+ * L1, LRAT, MMU capabilities?
+ * display PIR and PVR for as cores start?
+ * Registers to set
+   * BUCSR - branch control
+   * L1CSR0, L1CSR1, L1CSR2 - L1 Cache
+   * PWRMGTCR0 - power management
+   * HID0 - error management
+
+ * Timer state - Not required
+ * L2 - "Note that enabling either L1 cache without first enabling the L2 cache is not supported."
+     * flash invalidate
+     * enable
+ * L1
+   * flash clear
+   * enable
+
+
+* Set up CCSR TLB
+* Set up L1 TLB and stack
+
+## Address space considerations
+
+### 7.5.2.1 Address Space (AS) Value
+Address spaces require different TLB entries
+
+### CCSR
+T2080RM - -CCSR needs to not be overlapped with flash space
+4.3.1.1 Updating CCSRBARs
+
+Also see MPC8544ERM
+
+*/
+
 .section .boot, "ax"
 .global _reset