mirror of https://github.com/wolfSSL/wolfBoot.git
Add LS1028A eSDHC SD card disk boot support
David Garske
Daniele Lacamera
parent
8eafe1ef76
commit
a8c8c19fe8
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@ -274,6 +274,14 @@ jobs:
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config-file: ./config/examples/nxp-ls1028a-tpm.config
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make-args: CROSS_COMPILE=aarch64-linux-gnu-
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# SD card disk boot via the Freescale eSDHC driver (hal/nxp_esdhc.o)
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nxp_ls1028a_sdcard_test:
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uses: ./.github/workflows/test-build.yml
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with:
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arch: aarch64
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config-file: ./config/examples/nxp-ls1028a-sdcard.config
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make-args: CROSS_COMPILE=aarch64-linux-gnu-
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nxp_mcxa_test:
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uses: ./.github/workflows/test-build-mcux-sdk-manifests.yml
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with:
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20
arch.mk
20
arch.mk
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@ -181,6 +181,18 @@ ifeq ($(ARCH),AARCH64)
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CFLAGS+=-fno-builtin-printf
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endif
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# SD card disk boot uses the Freescale eSDHC driver, not the Cadence
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# SDHCI one (the shared AARCH64 block below wires update_disk.o).
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# hal/nxp_esdhc.c is SD card only, so DISK_EMMC has no driver here:
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# reject it rather than silently link the wrong controller driver.
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ifeq ($(DISK_EMMC),1)
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$(error DISK_EMMC is not supported on nxp_ls1028a (hal/nxp_esdhc.c is SD card only))
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endif
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ifeq ($(DISK_SDCARD),1)
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override DISK_DRIVER=esdhc
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OBJS+=hal/nxp_esdhc.o
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endif
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SPI_TARGET=nxp
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endif
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@ -1598,10 +1610,16 @@ ifneq ($(filter nxp_t1024 nxp_t1040,$(TARGET)),)
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# Disk boot from SD card (eSDHC controller, driver hal/nxp_esdhc.c).
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# src/gpt.o is already linked for all PPC targets above. The driver is
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# kept out of the size-constrained stage1 loader.
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ifneq ($(filter 1,$(DISK_SDCARD) $(DISK_EMMC)),)
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# hal/nxp_esdhc.c drives SD cards only: it has no eMMC (CMD1/EXT_CSD)
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# initialization, so DISK_EMMC has no driver on this arch.
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ifeq ($(DISK_EMMC),1)
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$(error DISK_EMMC is not supported on PPC (hal/nxp_esdhc.c is SD card only))
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endif
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ifeq ($(DISK_SDCARD),1)
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CFLAGS+=-D"WOLFBOOT_UPDATE_DISK" -D"MAX_DISKS=1"
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UPDATE_OBJS:=src/update_disk.o
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OBJS+=src/disk.o
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override DISK_DRIVER=esdhc
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ifneq ($(STAGE1),1)
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OBJS+=hal/nxp_esdhc.o
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endif
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@ -0,0 +1,88 @@
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# NXP LS1028A with SD card disk boot
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#
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# Same as nxp-ls1028a.config, but the signed application image is loaded
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# from the SD card slot (eSDHC1 at 0x02140000) instead of XSPI NOR. The
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# card is GPT (or MBR) partitioned; the signed image sits at offset 0 of
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# the first two partitions (BOOT_PART_A / BOOT_PART_B, 0-based indexes
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# into the partition table - same card layout as the T1040 eSDHC target).
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# wolfBoot picks the slot with the higher version, verifies it and boots
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# it from DDR (src/update_disk.c).
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ARCH=AARCH64
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TARGET=nxp_ls1028a
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SIGN?=ECC256
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HASH?=SHA256
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DEBUG?=0
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DEBUG_UART?=1
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VTOR?=0
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CORTEX_M0?=0
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NO_ASM?=0
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EXT_FLASH?=1
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SPI_FLASH?=0
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## Force app to be copied into ram
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NO_XIP?=1
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UART_FLASH?=0
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ALLOW_DOWNGRADE?=0
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NVM_FLASH_WRITEONCE?=0
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WOLFBOOT_VERSION?=0
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V?=0
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NO_MPU?=0
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SPMATH?=1
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RAM_CODE?=0
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DUALBANK_SWAP?=0
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PKA?=0
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ELF?=1
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# SD card disk boot (Freescale eSDHC driver, hal/nxp_esdhc.c)
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DISK_SDCARD=1
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# Upper bound for the unauthenticated image size read from disk
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WOLFBOOT_RAMBOOT_MAX_SIZE?=0x1000000
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# Boot slots: partition table indexes (0-based) and read chunk size
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CFLAGS_EXTRA+=-DBOOT_PART_A=0 -DBOOT_PART_B=1
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CFLAGS_EXTRA+=-DDISK_BLOCK_SIZE=0x8000
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# do_boot keeps the MMU and caches on (ENETC coherency) and cleans from the
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# entry point before the jump. Pin the clean length to the RAMBOOT window so
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# it covers the area images are loaded into regardless of what
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# WOLFBOOT_PARTITION_SIZE is set to. Note this cleans one span from the
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# entry point: an ELF or FIT payload that relocates a segment outside this
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# window would need its own cache maintenance.
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CFLAGS_EXTRA+=-DWOLFBOOT_MMU_FLUSH_APP_SIZE=0x1000000
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# eSDHC bring-up trace on the DUART console
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#CFLAGS_EXTRA+=-DDEBUG_ESDHC
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# NOR Base Address
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ARCH_FLASH_OFFSET?=0x20000000
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# Flash Sector Size (128 KB)
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WOLFBOOT_SECTOR_SIZE=0x20000
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# wolfBoot start address
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WOLFBOOT_ORIGIN=0x20020000
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# wolfBoot partition size
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BOOTLOADER_PARTITION_SIZE=0x20000
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# Application Partition size. Matches the 16MB SD card slots; the sign
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# tool bounds the image against this even though disk boot does not use
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# the NOR partitions.
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WOLFBOOT_PARTITION_SIZE?=0x1000000
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# Location in Flash for Application Partition (unused for disk boot,
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# kept for target.h consistency)
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WOLFBOOT_PARTITION_BOOT_ADDRESS?=0x20100000
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# Load the image to DDR, not the default OCRAM: OCRAM also holds
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# wolfBoot's own .data/.bss/.stack and cannot hold a disk-sized image.
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WOLFBOOT_LOAD_ADDRESS?=0x80100000
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# Location in Flash for Update Partition
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WOLFBOOT_PARTITION_UPDATE_ADDRESS?=0x21100000
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# Location of temporary sector used during updates
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WOLFBOOT_PARTITION_SWAP_ADDRESS?=0x22100000
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# DTS (Device Tree). The load address must sit above
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# WOLFBOOT_LOAD_ADDRESS + WOLFBOOT_RAMBOOT_MAX_SIZE.
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WOLFBOOT_LOAD_DTS_ADDRESS?=0x82000000
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WOLFBOOT_DTS_BOOT_ADDRESS?=0x20F00000
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WOLFBOOT_DTS_UPDATE_ADDRESS?=0x20F00000
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@ -3698,6 +3698,11 @@ The LS1028A is a AARCH64 armv8-a Cortex-A72 processor. Support has been tested w
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Example configurations for this target are provided in:
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* NXP LS1028A: [/config/examples/nxp-ls1028a.config](/config/examples/nxp-ls1028a.config).
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* NXP LS1028A with TPM: [/config/examples/nxp-ls1028a-tpm.config](/config/examples/nxp-ls1028a-tpm.config).
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* NXP LS1028A with SD card boot: [/config/examples/nxp-ls1028a-sdcard.config](/config/examples/nxp-ls1028a-sdcard.config).
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### LS1028A SD Card Boot (eSDHC)
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The LS1028A can load the signed application image from the SD card slot (eSDHC1) using the same Freescale eSDHC driver as the T1040 (`hal/nxp_esdhc.c`, built as its own object). The card layout is identical to the T1040 SD target: GPT (or MBR) partitioned, with the signed image at offset 0 of the first two partitions (`BOOT_PART_A`/`BOOT_PART_B`, 0-based). wolfBoot reads both headers, picks the higher version, loads it to DDR (`WOLFBOOT_LOAD_ADDRESS=0x80100000`), verifies the signature and boots it. The driver reprograms the eSDHC source clock (HWA2) at init, because the NOR-boot RCW leaves it on a source too fast for card identification. Define `DEBUG_ESDHC` (see the config) for controller bring-up trace on the DUART console. Validated on the LS1028ARDB booting a signed image from SD.
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### Building wolfBoot for NXP LS1028A
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131
hal/nxp_esdhc.c
131
hal/nxp_esdhc.c
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@ -19,7 +19,8 @@
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
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*/
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/* Freescale/NXP eSDHC block driver for QorIQ (T1040, T1024, T2080).
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/* Freescale/NXP eSDHC block driver for QorIQ PPC (T1040, T1024, T2080)
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* and Layerscape (LS1028A).
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*
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* Provides the four entry points src/disk.c expects (disk_init, disk_read,
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* disk_write, disk_close) so the disk boot path, and therefore DISK_FS, can
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@ -30,9 +31,9 @@
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* one XFERTYP register, combines block size and count into BLKATTR, and has
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* a watermark register with no standard-SDHCI equivalent.
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*
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* Compiled as its own object (arch.mk adds hal/nxp_esdhc.o when
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* DISK_SDCARD or DISK_EMMC is set); the clock helpers it needs are
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* exported by nxp_ppc.h.
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* Compiled as its own object (the target's arch.mk block adds
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* hal/nxp_esdhc.o and sets DISK_DRIVER=esdhc when DISK_SDCARD is set);
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* per-target base address, clocks and byte order are selected below.
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*
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* Transfers use PIO through DATPORT rather than DMA. On e5500 with the MMU
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* enabled a DMA descriptor would need cache maintenance on the destination,
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@ -47,7 +48,38 @@
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#include "disk.h"
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#include "printf.h"
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/* Per-target selection. The eSDHC block is the same IP on big-endian QorIQ
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* PPC and little-endian Layerscape; the register file follows the
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* integration, so a native 32-bit access reads it correctly on both. Only
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* the base address, source clock and DATPORT byte order move per target. */
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#if defined(TARGET_nxp_ls1028a)
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#include "nxp_ls1028a.h"
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/* eSDHC1 is the SD card slot; eSDHC2 is eMMC, not supported by this driver. */
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#define ESDHC_CTRL_BASE ESDHC_BASE(0)
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#define ESDHC_EMODE_SEL ESDHC_PROCTL_EMODE_LE
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#ifndef ESDHC_REF_CLK
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#define ESDHC_REF_CLK 400000000UL
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#endif
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/* The block is clocked by hardware-accelerator mux HWA2 (the device tree
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* binds mmc@2140000 to QORIQ_CLK_HWACCEL index 1). The NOR-boot RCW leaves
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* it on CGA_PLL2 (1.2 GHz), which overruns the card during identification;
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* CLKSEL=7 selects CGA_PLL1/3. Set at runtime so SD works whichever RCW
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* booted us. hwaccel[idx] = clockgen + 0x20*idx + 0x10, eSDHC is idx 1. */
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#define LS1028A_HWA2CSR (CGUCGA_BASE + 0x30)
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#define HWA_CLKSEL_MASK 0x78000000U
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#define HWA_CLKSEL_SHIFT 27
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#define HWA_CLKSEL_ESDHC 7U
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#else
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/* QorIQ PPC T-series: big-endian core and registers. */
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#include "nxp_ppc.h"
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#define ESDHC_CTRL_BASE (CCSRBAR + 0x114000)
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#define ESDHC_EMODE_SEL ESDHC_PROCTL_EMODE_BE
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#endif /* target selection */
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#ifdef DEBUG_ESDHC
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#define ESDHC_DBG(_f_, ...) wolfBoot_printf(_f_, ##__VA_ARGS__)
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@ -55,18 +87,7 @@
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#define ESDHC_DBG(_f_, ...) do{}while(0)
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#endif
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/* ---------------------------------------------------------------------
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* Register map. CCSRBAR comes from nxp_ppc.h for the selected target.
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*
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* The block presents its registers big-endian and the e5500 is big-endian,
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* so a native 32-bit access reads them correctly with no swapping. The one
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* exception is DATPORT, whose byte order is selected by PROCTL[EMODE] and is
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* configured below.
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* --------------------------------------------------------------------- */
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#ifndef ESDHC_BASE
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#define ESDHC_BASE (CCSRBAR + 0x114000)
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#endif
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#define ESDHC_REG(off) ((volatile uint32_t*)(ESDHC_BASE + (off)))
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#define ESDHC_REG(off) ((volatile uint32_t*)(ESDHC_CTRL_BASE + (off)))
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#define ESDHC_DSADDR 0x00
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#define ESDHC_BLKATTR 0x04
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@ -117,11 +138,11 @@
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#define ESDHC_PROCTL_DTW_1BIT (0U << 1)
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#define ESDHC_PROCTL_DTW_4BIT (1U << 1)
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#define ESDHC_PROCTL_DTW_MASK (3U << 1)
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/* EMODE selects the byte order of DATPORT. Big-endian mode delivers bytes
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* in media order when the word is stored natively by this big-endian core.
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* Verified on T1040D4RDB silicon: little-endian mode read every aligned
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* 4-byte group byte-reversed (MBR signature came back AA55). */
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/* EMODE sets DATPORT byte order; ESDHC_EMODE_SEL picks the mode giving
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* media order for a native word store. Silicon-verified: BE on the T1040
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* (LE there returned every aligned 4-byte group reversed). */
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#define ESDHC_PROCTL_EMODE_BE (0U << 4)
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#define ESDHC_PROCTL_EMODE_LE (2U << 4)
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#define ESDHC_PROCTL_EMODE_MASK (3U << 4)
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/* SYSCTL */
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@ -186,6 +207,27 @@ static int g_esdhc_ready;
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* 37500000 Hz (600 MHz / 16).
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* --------------------------------------------------------------------- */
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#if defined(TARGET_nxp_ls1028a)
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/* ARM generic timer; hal_init() enables the system counter first. */
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static uint64_t esdhc_timebase(void)
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{
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uint64_t cnt;
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__asm__ __volatile__("isb; mrs %0, cntpct_el0" : "=r"(cnt));
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return cnt;
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}
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static uint32_t esdhc_read_tb_hz(void)
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{
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uint64_t frq;
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__asm__ __volatile__("mrs %0, cntfrq_el0" : "=r"(frq));
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return (uint32_t)frq;
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}
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#else
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static uint64_t esdhc_timebase(void)
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{
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uint32_t hi, lo, hi2;
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@ -201,6 +243,13 @@ static uint64_t esdhc_timebase(void)
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return ((uint64_t)hi << 32) | (uint64_t)lo;
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}
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static uint32_t esdhc_read_tb_hz(void)
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{
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return TIMEBASE_HZ;
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}
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#endif /* target timebase */
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/* Timebase frequency, cached by disk_init(). TIMEBASE_HZ reads clock
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* registers and divides on every use; the value cannot change at runtime,
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* and disk_init() rejects a zero reading before any other driver path can
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@ -311,7 +360,11 @@ static int esdhc_send_cmd(uint32_t idx, uint32_t arg, uint32_t xfertyp,
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/* Set the SD clock. The divider is SDCLKFS (base 2 prescaler) times DVS. */
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static void esdhc_set_clock(uint32_t target_hz)
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{
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#if defined(TARGET_nxp_ls1028a)
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uint32_t base = ESDHC_REF_CLK;
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#else
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uint32_t base = hal_get_bus_clk();
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#endif
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uint32_t pre = 2, div = 1, sysctl;
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if (target_hz == 0U) {
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@ -341,8 +394,9 @@ static void esdhc_set_clock(uint32_t target_hz)
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ESDHC_SYSCTL_SDCLKEN;
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esdhc_udelay(100);
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ESDHC_DBG("esdhc: clock %u Hz (pre %u, div %u)\r\n",
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(base / pre) / div, pre, div);
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ESDHC_DBG("esdhc: clock %u Hz (pre %u, div %u) SYSCTL %x PROCTL %x\r\n",
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(base / pre) / div, pre, div,
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*ESDHC_REG(ESDHC_SYSCTL), *ESDHC_REG(ESDHC_PROCTL));
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}
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@ -376,7 +430,7 @@ static int esdhc_host_init(void)
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/* 1-bit bus for identification, and set the data-port byte order. */
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proctl = *ESDHC_REG(ESDHC_PROCTL);
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proctl &= ~(ESDHC_PROCTL_DTW_MASK | ESDHC_PROCTL_EMODE_MASK);
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proctl |= ESDHC_PROCTL_DTW_1BIT | ESDHC_PROCTL_EMODE_BE;
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proctl |= ESDHC_PROCTL_DTW_1BIT | ESDHC_EMODE_SEL;
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*ESDHC_REG(ESDHC_PROCTL) = proctl;
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esdhc_set_clock(400000U);
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@ -403,6 +457,7 @@ static int esdhc_send_acmd(uint32_t idx, uint32_t arg, uint32_t xfertyp,
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ESDHC_XFERTYP_RSPTYP_48 | ESDHC_XFERTYP_CICEN | ESDHC_XFERTYP_CCCEN,
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NULL);
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if (ret != 0) {
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ESDHC_DBG("esdhc: CMD55 (for ACMD%u) failed\r\n", idx);
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return ret;
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}
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return esdhc_send_cmd(idx, arg, xfertyp, resp);
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@ -442,8 +497,10 @@ static int esdhc_card_init(void)
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return -1;
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}
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v2 = 1;
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ESDHC_DBG("esdhc: CMD8 ok resp %x\r\n", resp[0]);
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}
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else {
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ESDHC_DBG("esdhc: CMD8 no response (v1 or signalling)\r\n");
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/* CMD8 leaves the command line in error state on a v1 card. */
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*ESDHC_REG(ESDHC_SYSCTL) = *ESDHC_REG(ESDHC_SYSCTL) |
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ESDHC_SYSCTL_RSTC;
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@ -529,10 +586,12 @@ static int esdhc_card_init(void)
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/* Drain one block from the data port.
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*
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* PROCTL[EMODE] is set to big-endian above, so a native 32-bit read of
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* DATPORT returns the four media bytes already in order and they can be
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* stored as-is. Silicon-verified: little-endian mode returned every
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* aligned 4-byte group byte-reversed. */
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* ESDHC_EMODE_SEL (set per target above) makes a native 32-bit read of
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* DATPORT return the four media bytes already in order, so they are
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* stored as-is. The correct mode differs by integration and both are
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* silicon-verified: big-endian on the big-endian T1040, where
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* little-endian returned every aligned 4-byte group reversed, and
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* little-endian on the little-endian LS1028A. */
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static int esdhc_read_block(uint8_t *buf)
|
||||
{
|
||||
uint32_t i, word;
|
||||
|
|
@ -662,6 +721,19 @@ static int esdhc_read_blocks(uint64_t lba, uint32_t count, uint8_t *buf)
|
|||
* disk.c interface
|
||||
* --------------------------------------------------------------------- */
|
||||
|
||||
#if defined(TARGET_nxp_ls1028a)
|
||||
/* Route a usable source clock to the eSDHC block (see HWA2CSR above). */
|
||||
static void esdhc_clock_src_init(void)
|
||||
{
|
||||
volatile uint32_t *hwa2 = (volatile uint32_t*)LS1028A_HWA2CSR;
|
||||
uint32_t val = (*hwa2 & ~HWA_CLKSEL_MASK) |
|
||||
(HWA_CLKSEL_ESDHC << HWA_CLKSEL_SHIFT);
|
||||
|
||||
*hwa2 = val;
|
||||
ESDHC_DBG("esdhc: HWA2CSR %x\r\n", *hwa2);
|
||||
}
|
||||
#endif
|
||||
|
||||
int disk_init(int drv)
|
||||
{
|
||||
if (drv != 0) {
|
||||
|
|
@ -673,7 +745,10 @@ int disk_init(int drv)
|
|||
/* Cache the timebase frequency for every delay and timeout below. A
|
||||
* zero reading means no timeout in this driver could ever expire, so
|
||||
* fail here and let the caller panic instead of spinning forever. */
|
||||
g_esdhc_tb_hz = TIMEBASE_HZ;
|
||||
#if defined(TARGET_nxp_ls1028a)
|
||||
esdhc_clock_src_init();
|
||||
#endif
|
||||
g_esdhc_tb_hz = esdhc_read_tb_hz();
|
||||
if (g_esdhc_tb_hz == 0U) {
|
||||
return -1;
|
||||
}
|
||||
|
|
|
|||
12
options.mk
12
options.mk
|
|
@ -801,12 +801,14 @@ ifeq ($(DISK_EMMC),1)
|
|||
CFLAGS+=-D"DISK_EMMC=1"
|
||||
endif
|
||||
|
||||
# Add SDHCI driver if SD card or eMMC is enabled (only add once).
|
||||
# PPC targets provide their own eSDHC driver (hal/nxp_esdhc.o, added in
|
||||
# arch.mk), so the Cadence SDHCI driver must not be linked there (its
|
||||
# disk_* entry points would collide).
|
||||
# Add the SD/eMMC block driver if SD card or eMMC is enabled (only once).
|
||||
# DISK_DRIVER selects which one: the Cadence SDHCI driver (src/sdhci.c,
|
||||
# the default) or the Freescale eSDHC driver (hal/nxp_esdhc.o, added by
|
||||
# the target's arch.mk block, which also sets DISK_DRIVER=esdhc). Exactly
|
||||
# one may link: both define the disk_* entry points.
|
||||
DISK_DRIVER?=cadence
|
||||
ifneq ($(filter 1,$(DISK_SDCARD) $(DISK_EMMC)),)
|
||||
ifneq ($(ARCH),PPC)
|
||||
ifeq ($(DISK_DRIVER),cadence)
|
||||
OBJS+= src/sdhci.o
|
||||
endif
|
||||
endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue