mirror of https://github.com/wolfSSL/wolfBoot.git
NXP T1024 wolfBoot support:
* Added DDR4 w/ECC. * Added L2 and L2 CPC SRAM support * Added platform SRAM 160KB support * Added support for core timers (timebase) and platform clock. * Added IFC driver with erase/write * Added stage 1 loader to relocate wolfBoot to DDR * Added CPLD, QUICC, FMAN and MP drivers * Added eSPI driver for TPM. * Added hal_early_init instead of calling ddr_init directly. * Fixes for device tree (DTB) loading with update_ram and PPC boot. * Fixes for relocating CCSRBAR to upper. * Fixes for interrupt offsets.pull/375/head
David Garske
Daniele Lacamera
parent
bef9d8c32f
commit
b3e2fb9ddd
|
|
@ -76,6 +76,12 @@ jobs:
|
|||
arch: ppc
|
||||
config-file: ./config/examples/nxp-p1021.config
|
||||
|
||||
nxp_t1024_test:
|
||||
uses: ./.github/workflows/test-build.yml
|
||||
with:
|
||||
arch: ppc
|
||||
config-file: ./config/examples/nxp-t1024.config
|
||||
|
||||
nxp_t2080_68ppc2_test:
|
||||
uses: ./.github/workflows/test-build.yml
|
||||
with:
|
||||
|
|
|
|||
3
Makefile
3
Makefile
|
|
@ -106,6 +106,9 @@ endif
|
|||
ifeq ($(TARGET),nxp_p1021)
|
||||
MAIN_TARGET:=factory_wstage1.bin
|
||||
endif
|
||||
ifeq ($(TARGET),nxp_t1024)
|
||||
MAIN_TARGET:=factory_wstage1.bin
|
||||
endif
|
||||
|
||||
ASFLAGS:=$(CFLAGS)
|
||||
BOOTLOADER_PARTITION_SIZE?=$$(( $(WOLFBOOT_PARTITION_BOOT_ADDRESS) - $(ARCH_FLASH_OFFSET)))
|
||||
|
|
|
|||
25
arch.mk
25
arch.mk
|
|
@ -412,9 +412,30 @@ ifeq ($(ARCH),ARM_BE)
|
|||
endif
|
||||
endif
|
||||
|
||||
ifeq ($(TARGET),nxp_t1024)
|
||||
# Power PC big endian
|
||||
ARCH_FLAGS=-mhard-float -mcpu=e5500
|
||||
CFLAGS+=$(ARCH_FLAGS) -DBIG_ENDIAN_ORDER
|
||||
CFLAGS+=-DMMU -DWOLFBOOT_DUALBOOT
|
||||
CFLAGS+=-pipe # use pipes instead of temp files
|
||||
CFLAGS+=-feliminate-unused-debug-types
|
||||
LDFLAGS+=$(ARCH_FLAGS)
|
||||
LDFLAGS+=-Wl,--hash-style=both # generate both sysv and gnu symbol hash table
|
||||
LDFLAGS+=-Wl,--as-needed # remove weak functions not used
|
||||
OBJS+=src/boot_ppc_mp.o # support for spin table
|
||||
UPDATE_OBJS:=src/update_ram.o
|
||||
ifeq ($(SPMATH),1)
|
||||
MATH_OBJS += ./lib/wolfssl/wolfcrypt/src/sp_c32.o
|
||||
else
|
||||
# Use the SP math all assembly accelerations
|
||||
CFLAGS+=-DWOLFSSL_SP_PPC
|
||||
endif
|
||||
SPI_TARGET=nxp
|
||||
endif
|
||||
|
||||
ifeq ($(TARGET),nxp_t2080)
|
||||
# Power PC big endian
|
||||
ARCH_FLAGS=-m32 -mhard-float -mcpu=e6500
|
||||
ARCH_FLAGS=-mhard-float -mcpu=e6500
|
||||
CFLAGS+=$(ARCH_FLAGS) -DBIG_ENDIAN_ORDER
|
||||
CFLAGS+=-DMMU -DWOLFBOOT_DUALBOOT
|
||||
CFLAGS+=-pipe # use pipes instead of temp files
|
||||
|
|
@ -440,8 +461,8 @@ ifeq ($(TARGET),nxp_p1021)
|
|||
CFLAGS+=-pipe # use pipes instead of temp files
|
||||
LDFLAGS+=$(ARCH_FLAGS)
|
||||
LDFLAGS+=-Wl,--as-needed # remove weak functions not used
|
||||
OBJS+=src/boot_ppc_mp.o # support for spin table
|
||||
UPDATE_OBJS:=src/update_ram.o
|
||||
UPDATE_OBJS+=src/boot_ppc_mp.o
|
||||
|
||||
# Use PPC stdlib for memcpy, etc.
|
||||
#CFLAGS+=-DWOLFBOOT_USE_STDLIBC
|
||||
|
|
|
|||
|
|
@ -0,0 +1,67 @@
|
|||
# NXP QorIQ T1024 (2 core)
|
||||
|
||||
ARCH=PPC
|
||||
TARGET=nxp_t1024
|
||||
SIGN?=ECC384
|
||||
HASH?=SHA384
|
||||
IMAGE_HEADER_SIZE?=512
|
||||
DEBUG?=0
|
||||
DEBUG_UART?=1
|
||||
VTOR?=1
|
||||
CORTEX_M0?=0
|
||||
NO_ASM?=0
|
||||
EXT_FLASH?=0
|
||||
SPI_FLASH?=0
|
||||
NO_XIP?=0
|
||||
UART_FLASH?=0
|
||||
ALLOW_DOWNGRADE?=0
|
||||
NVM_FLASH_WRITEONCE?=0
|
||||
WOLFBOOT_VERSION?=0
|
||||
NO_MPU?=0
|
||||
SPMATH?=0
|
||||
SPMATHALL?=1
|
||||
RAM_CODE?=0
|
||||
DUALBANK_SWAP?=0
|
||||
WOLFTPM?=0
|
||||
ELF?=1
|
||||
DEBUG_ELF=0
|
||||
|
||||
# NOR Base Address
|
||||
ARCH_FLASH_OFFSET?=0xEC000000
|
||||
|
||||
# Flash Sector Size
|
||||
WOLFBOOT_SECTOR_SIZE=0x10000
|
||||
|
||||
# wolfBoot start address
|
||||
WOLFBOOT_ORIGIN=0xEFF40000
|
||||
# wolfBoot partition size (custom)
|
||||
BOOTLOADER_PARTITION_SIZE=0xC0000
|
||||
|
||||
# Application Partition Size
|
||||
WOLFBOOT_PARTITION_SIZE?=0x01E00000
|
||||
# Location in Flash for Application Partition
|
||||
WOLFBOOT_PARTITION_BOOT_ADDRESS?=0xEE000000
|
||||
# Load Partition to RAM Address
|
||||
WOLFBOOT_LOAD_ADDRESS?=0x70000000
|
||||
|
||||
# Location in Flash for Update Partition
|
||||
WOLFBOOT_PARTITION_UPDATE_ADDRESS?=0xEC200000
|
||||
|
||||
# Location of temporary sector used during updates
|
||||
WOLFBOOT_PARTITION_SWAP_ADDRESS?=0xEC0F0000
|
||||
|
||||
# Stage 1 loader settings (16KB)
|
||||
WOLFBOOT_STAGE1_SIZE=0x4000
|
||||
# Location in Flash for stage 1 loader (XIP from boot ROM)
|
||||
WOLFBOOT_STAGE1_FLASH_ADDR=0xEFFFC000
|
||||
# Address in RAM to load wolfBoot (end of DDR at 2GB-1MB)
|
||||
WOLFBOOT_STAGE1_LOAD_ADDR=0x7FF00000
|
||||
|
||||
# DTS (Device Tree)
|
||||
WOLFBOOT_DTS_BOOT_ADDRESS?=0xEC020000
|
||||
WOLFBOOT_DTS_UPDATE_ADDRESS?=0xEC040000
|
||||
# DTS Load to RAM Address
|
||||
WOLFBOOT_LOAD_DTS_ADDRESS?=0x7F100000
|
||||
|
||||
# Load to RAM before hash and verify
|
||||
CFLAGS_EXTRA+=-DWOLFBOOT_USE_RAMBOOT
|
||||
|
|
@ -30,7 +30,13 @@ ARCH_FLASH_OFFSET?=0xEFFF0000
|
|||
BOOTLOADER_PARTITION_SIZE=0x10000
|
||||
|
||||
WOLFBOOT_PARTITION_BOOT_ADDRESS?=0xEFFD0000
|
||||
WOLFBOOT_LOAD_ADDRESS?=0x19000
|
||||
WOLFBOOT_PARTITION_UPDATE_ADDRESS?=0xEFFB0000
|
||||
|
||||
# Location of temporary sector used during updates
|
||||
WOLFBOOT_PARTITION_SWAP_ADDRESS?=0xEFFA0000
|
||||
WOLFBOOT_LOAD_ADDRESS?=0x200000
|
||||
WOLFBOOT_LOAD_DTS_ADDRESS?=0x40000
|
||||
|
||||
# DTS (Device Tree)
|
||||
WOLFBOOT_DTS_BOOT_ADDRESS?=0xE8040000
|
||||
WOLFBOOT_DTS_UPDATE_ADDRESS?=0xE8050000
|
||||
WOLFBOOT_LOAD_DTS_ADDRESS?=0x200000
|
||||
|
|
|
|||
|
|
@ -11,6 +11,7 @@ This README describes configuration of supported targets.
|
|||
* [NXP iMX-RT](#nxp-imx-rt)
|
||||
* [NXP Kinetis](#nxp-kinetis)
|
||||
* [NXP P1021 PPC](#nxp-qoriq-p1021-ppc)
|
||||
* [NXP T1024 PPC](#nxp-qoriq-t1024-ppc)
|
||||
* [NXP T2080 PPC](#nxp-qoriq-t2080-ppc)
|
||||
* [Qemu x86-64 UEFI](#qemu-x86-64-uefi)
|
||||
* [SiFive HiFive1 RISC-V](#sifive-hifive1-risc-v)
|
||||
|
|
@ -1245,6 +1246,92 @@ make factory_wstage1.bin
|
|||
```
|
||||
|
||||
|
||||
## NXP QorIQ T1024 PPC
|
||||
|
||||
The NXP QorIQ T1024 is a two core 64-bit PPC e5500 based processor at 1400MHz. Each core has 256KB L2 cache.
|
||||
|
||||
Board: T1024RDB
|
||||
Board rev: 0x3031
|
||||
CPLD ver: 0x42
|
||||
|
||||
T1024E, Version: 1.0, (0x8548_0010)
|
||||
e5500, Version: 2.1, (0x8024_1021)
|
||||
|
||||
Reset Configuration Word (RCW):
|
||||
00000000: 0810000e 00000000 00000000 00000000
|
||||
00000010: 2d800003 40408812 fc027000 21000000
|
||||
00000020: 00000000 00000000 60000000 00036800
|
||||
00000030: 00000100 484a5808 00000000 00000006
|
||||
|
||||
Flash is NOR on IFC CS0 (0x0_EC00_0000) 64MB (default).
|
||||
|
||||
Default NOR Flash Memory Layout (64MB):
|
||||
|
||||
| Description | Address | Size |
|
||||
| ----------------- | ---------- | ------------------- |
|
||||
| RCW | 0xEC000000 | 0x00020000 (128 KB) |
|
||||
| Primary (FDT) | 0xEC020000 | 0x00020000 (128 KB) |
|
||||
| Update (FDT) | 0xEC040000 | 0x00020000 (128 KB) |
|
||||
| Free | 0xEC060000 | 0x00090000 (576 KB) |
|
||||
| Swap Sector | 0xEC0F0000 | 0x00010000 ( 64 KB) |
|
||||
| Free | 0xEC100000 | 0x00100000 ( 1 MB) |
|
||||
| Update (OS) | 0xEC200000 | 0x01E00000 ( 30 MB) |
|
||||
| Application (OS) | 0xEE000000 | 0x01E00000 ( 30 MB) |
|
||||
| QUICC | 0xEFE00000 | 0x00100000 ( 1 MB) |
|
||||
| DPAA (FMAN) | 0xEFF00000 | 0x00020000 (128 KB) |
|
||||
| wolfBoot | 0xEFF40000 | 0x000BC000 (752 KB) |
|
||||
| wolfBoot Stage 1 | 0xEFFFC000 | 0x00004000 ( 16 KB) |
|
||||
|
||||
QE: uploading microcode 'Microcode for T1024 r1.0' version 0.0.1
|
||||
|
||||
DDR4 2GB
|
||||
|
||||
### Building wolfBoot for NXP T1024 PPC
|
||||
|
||||
By default wolfBoot will use `powerpc-linux-gnu-` cross-compiler prefix. These tools can be installed with the Debian package `gcc-powerpc-linux-gnu` (`sudo apt install gcc-powerpc-linux-gnu`).
|
||||
|
||||
The `make` creates a `factory_stage1.bin` image that can be programmed at `0xEC000000`
|
||||
|
||||
```
|
||||
cp ./config/examples/nxp-t1024.config .config
|
||||
make clean
|
||||
make keytools
|
||||
make
|
||||
```
|
||||
|
||||
Or each `make` component can be manually built using:
|
||||
|
||||
```
|
||||
make stage1
|
||||
make wolfboot.elf
|
||||
make test-app/image_v1_signed.bin
|
||||
```
|
||||
|
||||
If getting errors with keystore then you can reset things using `make distclean`.
|
||||
|
||||
### Signing Custom application
|
||||
|
||||
```
|
||||
./tools/keytools/sign --ecc384 --sha384 custom.elf wolfboot_signing_private_key.der 1
|
||||
```
|
||||
|
||||
### Assembly of custom firmware image
|
||||
|
||||
```
|
||||
./tools/bin-assemble/bin-assemble factory_custom.bin \
|
||||
0xEC000000 RCW_CTS.bin \
|
||||
0xEC020000 custom.dtb \
|
||||
0xEE000000 custom_v1_signed.bin \
|
||||
0xEFE00000 iram_Type_A_T1024_r1.0.bin \
|
||||
0xEFF00000 fsl_fman_ucode_t1024_r1.0_108_4_5.bin \
|
||||
0xEFF40000 wolfboot.bin \
|
||||
0xEFFFC000 stage1/loader_stage1.bin
|
||||
```
|
||||
|
||||
Flash factory_custom.bin to NOR base 0xEC00_0000
|
||||
|
||||
|
||||
|
||||
## NXP QorIQ T2080 PPC
|
||||
|
||||
The NXP QorIQ T2080 is a PPC e6500 based processor (four cores). Support has been tested with the NAII 68PPC2.
|
||||
|
|
|
|||
|
|
@ -419,7 +419,6 @@ enum elbc_amask_sizes {
|
|||
#define DDR_SDRAM_MODE ((volatile uint32_t*)(DDR_BASE + 0x118)) /* DDR SDRAM mode configuration */
|
||||
#define DDR_SDRAM_MODE_2 ((volatile uint32_t*)(DDR_BASE + 0x11C)) /* DDR SDRAM mode configuration 2 */
|
||||
#define DDR_SDRAM_MD_CNTL ((volatile uint32_t*)(DDR_BASE + 0x120)) /* DDR SDRAM mode control */
|
||||
#define DDR_SDRAM_INTERVAL ((volatile uint32_t*)(DDR_BASE + 0x124)) /* DDR SDRAM interval configuration */
|
||||
#define DDR_SDRAM_CLK_CNTL ((volatile uint32_t*)(DDR_BASE + 0x130)) /* DDR SDRAM clock control */
|
||||
|
||||
#define DDR_SDRAM_CFG_MEM_EN 0x80000000 /* SDRAM interface logic is enabled */
|
||||
|
|
@ -482,7 +481,6 @@ enum elbc_amask_sizes {
|
|||
#define ESPI_CSMODE_CSAFT(x) (((x) & 0xF) << 8) /* CS assertion time in bits after frame end */
|
||||
#define ESPI_CSMODE_CSCG(x) (((x) & 0xF) << 3) /* Clock gaps between transmitted frames according to this size */
|
||||
|
||||
|
||||
#ifdef ENABLE_ELBC
|
||||
|
||||
static volatile uint8_t* flash_buf;
|
||||
|
|
@ -492,33 +490,31 @@ static uint32_t flash_idx;
|
|||
int ext_flash_read(uintptr_t address, uint8_t *data, int len);
|
||||
#endif
|
||||
|
||||
/* generic share NXP QorIQ driver code */
|
||||
#include "nxp_ppc.c"
|
||||
|
||||
|
||||
/* local functions */
|
||||
#ifdef ENABLE_BUS_CLK_CALC
|
||||
static uint32_t hal_get_bus_clk(void)
|
||||
{
|
||||
/* compute bus clock (system input 66MHz * ratio) */
|
||||
uint32_t bus_clk;
|
||||
#ifdef ENABLE_BUS_CLK_CALC
|
||||
/* compute bus clock (system input 66MHz * ratio */
|
||||
uint32_t plat_ratio = get32(GUTS_PORPLLSR);
|
||||
/* mask and shift by 1 to get platform ratio */
|
||||
plat_ratio = ((plat_ratio & 0x3E) >> 1);
|
||||
bus_clk = SYS_CLK * plat_ratio;
|
||||
return bus_clk;
|
||||
}
|
||||
#else
|
||||
return (uint32_t)(SYS_CLK * 6); /* can also be 8 */
|
||||
#define hal_get_bus_clk() (uint32_t)(SYS_CLK * 6)
|
||||
#endif
|
||||
}
|
||||
|
||||
#if defined(ENABLE_ESPI) || defined(ENABLE_DDR)
|
||||
#ifdef BUILD_LOADER_STAGE1
|
||||
static
|
||||
#endif
|
||||
void udelay(unsigned long delay_us)
|
||||
#define DELAY_US (hal_get_bus_clk() / 1000000)
|
||||
static void udelay(uint32_t delay_us)
|
||||
{
|
||||
delay_us *= (hal_get_bus_clk() / 1000000);
|
||||
wait_ticks(delay_us);
|
||||
wait_ticks(delay_us * DELAY_US);
|
||||
}
|
||||
#endif
|
||||
|
||||
/* ---- eSPI Driver ---- */
|
||||
#ifdef ENABLE_ESPI
|
||||
|
|
@ -903,7 +899,7 @@ static int hal_flash_init(void)
|
|||
return ret;
|
||||
}
|
||||
|
||||
void hal_ddr_init(void)
|
||||
static void hal_ddr_init(void)
|
||||
{
|
||||
#ifdef ENABLE_DDR
|
||||
uint32_t reg;
|
||||
|
|
@ -968,6 +964,12 @@ void hal_ddr_init(void)
|
|||
#endif /* ENABLE_DDR */
|
||||
}
|
||||
|
||||
void hal_early_init(void)
|
||||
{
|
||||
hal_ddr_init();
|
||||
}
|
||||
|
||||
|
||||
#ifdef ENABLE_PCIE
|
||||
#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
|
||||
#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000
|
||||
|
|
@ -987,18 +989,18 @@ static int hal_pcie_init(void)
|
|||
set_law(3, CONFIG_SYS_PCIE2_IO_PHYS, LAW_TRGT_PCIE2, LAW_SIZE_64KB),
|
||||
|
||||
/* Map TLB for PCIe */
|
||||
set_tlb(1, 2, CONFIG_SYS_PCIE2_MEM_VIRT, CONFIG_SYS_PCIE2_MEM_PHYS,
|
||||
set_tlb(1, 2, CONFIG_SYS_PCIE2_MEM_VIRT, CONFIG_SYS_PCIE2_MEM_PHYS, 0,
|
||||
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, BOOKE_PAGESZ_256M, 1);
|
||||
set_tlb(1, 3, (CONFIG_SYS_PCIE2_MEM_VIRT + 0x10000000),
|
||||
(CONFIG_SYS_PCIE2_MEM_PHYS + 0x10000000),
|
||||
(CONFIG_SYS_PCIE2_MEM_PHYS + 0x10000000), 0,
|
||||
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, BOOKE_PAGESZ_256M, 1);
|
||||
set_tlb(1, 4, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
|
||||
set_tlb(1, 4, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, 0,
|
||||
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, BOOKE_PAGESZ_256M, 1);
|
||||
set_tlb(1, 5, (CONFIG_SYS_PCIE1_MEM_VIRT + 0x10000000),
|
||||
(CONFIG_SYS_PCIE1_MEM_PHYS + 0x10000000),
|
||||
(CONFIG_SYS_PCIE1_MEM_PHYS + 0x10000000), 0,
|
||||
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, BOOKE_PAGESZ_256M, 1);
|
||||
|
||||
set_tlb(1, 6, CONFIG_SYS_PCIE2_IO_VIRT, CONFIG_SYS_PCIE2_IO_PHYS,
|
||||
set_tlb(1, 6, CONFIG_SYS_PCIE2_IO_VIRT, CONFIG_SYS_PCIE2_IO_PHYS, 0,
|
||||
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, BOOKE_PAGESZ_256K, 1);
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -1011,7 +1013,7 @@ static int hal_cpld_init(void)
|
|||
/* Setup Local Access Window (LAW) for CPLD/BCSR */
|
||||
set_law(5, BCSR_BASE, LAW_TRGT_ELBC, LAW_SIZE_256KB);
|
||||
/* Setup TLB MMU (Translation Lookaside Buffer) for CPLD/BCSR */
|
||||
set_tlb(1, 8, BCSR_BASE, BCSR_BASE, MAS3_SX | MAS3_SW | MAS3_SR,
|
||||
set_tlb(1, 8, BCSR_BASE, BCSR_BASE, 0, MAS3_SX | MAS3_SW | MAS3_SR,
|
||||
MAS2_I | MAS2_G, 0, BOOKE_PAGESZ_256K, 1);
|
||||
|
||||
/* setup eLBC for CPLD (CS1), 8-bit */
|
||||
|
|
@ -1504,7 +1506,7 @@ static void hal_mp_init(void)
|
|||
|
||||
/* map reset page to bootpg so we can copy code there */
|
||||
disable_tlb1(i_tlb);
|
||||
set_tlb(1, i_tlb, BOOT_ROM_ADDR, bootpg, /* tlb, epn, rpn */
|
||||
set_tlb(1, i_tlb, BOOT_ROM_ADDR, bootpg, 0, /* tlb, epn, rpn */
|
||||
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I, /* perms, wimge */
|
||||
0, BOOKE_PAGESZ_4K, 1); /* ts, esel, tsize, iprot */
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,23 @@
|
|||
/* nxp_ppc.c
|
||||
*
|
||||
* Copyright (C) 2023 wolfSSL Inc.
|
||||
*
|
||||
* This file is part of wolfBoot.
|
||||
*
|
||||
* wolfBoot is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* wolfBoot is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
|
||||
*/
|
||||
|
||||
/* This file gets directly included from nxp_ targets.
|
||||
* This file contains shared driver code for all NXP QorIQ platforms */
|
||||
241
hal/nxp_ppc.h
241
hal/nxp_ppc.h
|
|
@ -26,6 +26,7 @@
|
|||
/* NXP P1021 */
|
||||
#define CPU_NUMCORES 2
|
||||
#define CORE_E500
|
||||
#define LAW_MAX_ENTRIES 12
|
||||
|
||||
#define CCSRBAR_DEF (0xFF700000) /* P1021RM 4.3 default base */
|
||||
#define CCSRBAR_SIZE BOOKE_PAGESZ_1M
|
||||
|
|
@ -40,8 +41,13 @@
|
|||
/* First stage loader features */
|
||||
|
||||
#define ENABLE_L2_CACHE
|
||||
#define L2SRAM_ADDR (0xF8F80000) /* L2 as SRAM */
|
||||
#define L2SRAM_SIZE (256 * 1024)
|
||||
#define L2SRAM_ADDR (0xF8F80000) /* L2 as SRAM */
|
||||
#define L2SRAM_SIZE (256 * 1024)
|
||||
|
||||
#define INITIAL_SRAM_ADDR L2SRAM_ADDR
|
||||
#define INITIAL_SRAM_LAW_SZ LAW_SIZE_256KB
|
||||
#define INITIAL_SRAM_LAW_TRGT LAW_TRGT_ELBC
|
||||
#define INITIAL_SRAM_BOOKE_SZ BOOKE_PAGESZ_256K
|
||||
#else
|
||||
/* For wolfBoot features */
|
||||
#define ENABLE_L1_CACHE
|
||||
|
|
@ -53,28 +59,72 @@
|
|||
#define ENABLE_INTERRUPTS
|
||||
#endif
|
||||
|
||||
#elif defined(PLATFORM_nxp_t1024)
|
||||
/* NXP T1024 */
|
||||
#define CPU_NUMCORES 2
|
||||
#define CORE_E5500
|
||||
#define LAW_MAX_ENTRIES 16
|
||||
|
||||
#define CCSRBAR_DEF (0xFE000000) /* T1024RM 4.4.1 default base */
|
||||
#define CCSRBAR_SIZE BOOKE_PAGESZ_16M
|
||||
|
||||
#define INITIAL_SRAM_ADDR 0xFDFC0000
|
||||
#define INITIAL_SRAM_LAW_SZ LAW_SIZE_256KB
|
||||
#define INITIAL_SRAM_LAW_TRGT LAW_TRGT_PSRAM
|
||||
#define INITIAL_SRAM_BOOKE_SZ BOOKE_PAGESZ_256K
|
||||
|
||||
#define ENABLE_L1_CACHE
|
||||
#define ENABLE_INTERRUPTS
|
||||
|
||||
#ifdef BUILD_LOADER_STAGE1
|
||||
#define ENABLE_L2_CACHE /* setup and enable L2 in first stage only */
|
||||
#else
|
||||
/* relocate to 64-bit 0xF_ */
|
||||
#define CCSRBAR_PHYS_HIGH 0xFULL
|
||||
#define CCSRBAR_PHYS (CCSRBAR_PHYS_HIGH + CCSRBAR_DEF)
|
||||
#endif
|
||||
|
||||
#define ENABLE_DDR
|
||||
|
||||
#define FLASH_BASE_ADDR 0xEC000000
|
||||
#define FLASH_BASE_PHYS_HIGH 0xFULL
|
||||
#define FLASH_LAW_SIZE LAW_SIZE_64MB
|
||||
#define FLASH_TLB_PAGESZ BOOKE_PAGESZ_64M
|
||||
|
||||
#define USE_LONG_JUMP
|
||||
|
||||
#elif defined(PLATFORM_nxp_t2080)
|
||||
/* NXP T0280 */
|
||||
#define CPU_NUMCORES 4
|
||||
#define CORE_E6500
|
||||
#define LAW_MAX_ENTRIES 32
|
||||
|
||||
#define CCSRBAR_DEF (0xFE000000) /* T2080RM 4.3.1 default base - 0xFF000000 */
|
||||
#define CCSRBAR_DEF (0xFE000000) /* T2080RM 4.3.1 default base */
|
||||
#define CCSRBAR_SIZE BOOKE_PAGESZ_16M
|
||||
|
||||
/* relocate to 64-bit 0xE_ */
|
||||
//#define CCSRBAR_PHYS_HIGH 0xE
|
||||
//#define CCSRBAR_PHYS_HIGH 0xEULL
|
||||
//#define CCSRBAR_PHYS (CCSRBAR_PHYS_HIGH + CCSRBAR_DEF)
|
||||
|
||||
#define ENABLE_L1_CACHE
|
||||
#define ENABLE_L2_CACHE
|
||||
|
||||
#define L2SRAM_ADDR (0xF8F80000) /* L2 as SRAM */
|
||||
#define L2SRAM_SIZE (256 * 1024)
|
||||
|
||||
#define INITIAL_SRAM_ADDR L2SRAM_ADDR
|
||||
#define INITIAL_SRAM_LAW_SZ LAW_SIZE_256KB
|
||||
#define INITIAL_SRAM_LAW_TRGT LAW_TRGT_DDR_1
|
||||
#define INITIAL_SRAM_BOOKE_SZ BOOKE_PAGESZ_256K
|
||||
|
||||
#define ENABLE_INTERRUPTS
|
||||
|
||||
#define ENABLE_DDR
|
||||
|
||||
#define FLASH_BASE_ADDR 0xE8000000
|
||||
#define FLASH_BASE_PHYS_HIGH 0x0
|
||||
#define FLASH_BASE_ADDR 0xE8000000
|
||||
#define FLASH_BASE_PHYS_HIGH 0x0ULL
|
||||
#define FLASH_LAW_SIZE LAW_SIZE_128MB
|
||||
#define FLASH_TLB_PAGESZ BOOKE_PAGESZ_128M
|
||||
|
||||
#define USE_LONG_JUMP
|
||||
#else
|
||||
|
|
@ -118,9 +168,9 @@
|
|||
#define L1_CACHE_SZ (32 * 1024)
|
||||
#endif
|
||||
|
||||
#ifdef CORE_E500
|
||||
/* PowerPC e500 */
|
||||
/* EREF: 7.5.3.2 - TLB Entry Page Size */
|
||||
#if defined(CORE_E500) || defined(CORE_E5500)
|
||||
/* E500CORERM: 2.12.5.2 MAS Register 1 (MAS1)
|
||||
* E5500RM: 2.16.6.2 MAS Register 1 (MAS1) */
|
||||
#define BOOKE_PAGESZ_4K 1
|
||||
#define BOOKE_PAGESZ_16K 2
|
||||
#define BOOKE_PAGESZ_64K 3
|
||||
|
|
@ -135,6 +185,37 @@
|
|||
|
||||
#define MAS1_TSIZE_MASK 0x00000F00
|
||||
#define MAS1_TSIZE(x) (((x) << 8) & MAS1_TSIZE_MASK)
|
||||
#elif defined(CORE_E6500)
|
||||
/* E6500RM: 2.13.10.2 MMU Assist 1 (MAS1)
|
||||
* EREF 2.0: 6.5.3.2 - TLB Entry Page Size */
|
||||
#define BOOKE_PAGESZ_4K 2
|
||||
#define BOOKE_PAGESZ_8K 3
|
||||
#define BOOKE_PAGESZ_16K 4
|
||||
#define BOOKE_PAGESZ_32K 5
|
||||
#define BOOKE_PAGESZ_64K 6
|
||||
#define BOOKE_PAGESZ_128K 7
|
||||
#define BOOKE_PAGESZ_256K 8
|
||||
#define BOOKE_PAGESZ_512K 9
|
||||
#define BOOKE_PAGESZ_1M 10
|
||||
#define BOOKE_PAGESZ_2M 11
|
||||
#define BOOKE_PAGESZ_4M 12
|
||||
#define BOOKE_PAGESZ_8M 13
|
||||
#define BOOKE_PAGESZ_16M 14
|
||||
#define BOOKE_PAGESZ_32M 15
|
||||
#define BOOKE_PAGESZ_64M 16
|
||||
#define BOOKE_PAGESZ_128M 17
|
||||
#define BOOKE_PAGESZ_256M 18
|
||||
#define BOOKE_PAGESZ_512M 19
|
||||
#define BOOKE_PAGESZ_1G 20
|
||||
#define BOOKE_PAGESZ_2G 21
|
||||
#define BOOKE_PAGESZ_4G 22
|
||||
|
||||
#define MAS1_TSIZE_MASK 0x00000F80
|
||||
#define MAS1_TSIZE(x) (((x) << 7) & MAS1_TSIZE_MASK)
|
||||
#endif
|
||||
|
||||
#ifdef CORE_E500
|
||||
/* PowerPC e500 */
|
||||
|
||||
#define CACHE_LINE_SHIFT 5 /* 32 bytes per L1 cache line */
|
||||
|
||||
|
|
@ -179,44 +260,45 @@
|
|||
#define LAW_SIZE_32GB 0x22
|
||||
|
||||
|
||||
#elif defined(CORE_E6500)
|
||||
/* PowerPC e6500 */
|
||||
#elif defined(CORE_E6500) || defined(CORE_E5500)
|
||||
/* PowerPC e5500/e6500 */
|
||||
|
||||
/* CoreNet on-chip interface between the core cluster and rest of SoC */
|
||||
#define USE_CORENET_INTERFACE
|
||||
|
||||
/* EREF 2.0: 6.5.3.2 - TLB Entry Page Size */
|
||||
#define BOOKE_PAGESZ_4K 2
|
||||
#define BOOKE_PAGESZ_8K 3
|
||||
#define BOOKE_PAGESZ_16K 4
|
||||
#define BOOKE_PAGESZ_32K 5
|
||||
#define BOOKE_PAGESZ_64K 6
|
||||
#define BOOKE_PAGESZ_128K 7
|
||||
#define BOOKE_PAGESZ_256K 8
|
||||
#define BOOKE_PAGESZ_512K 9
|
||||
#define BOOKE_PAGESZ_1M 10
|
||||
#define BOOKE_PAGESZ_2M 11
|
||||
#define BOOKE_PAGESZ_4M 12
|
||||
#define BOOKE_PAGESZ_8M 13
|
||||
#define BOOKE_PAGESZ_16M 14
|
||||
#define BOOKE_PAGESZ_32M 15
|
||||
#define BOOKE_PAGESZ_64M 16
|
||||
#define BOOKE_PAGESZ_128M 17
|
||||
#define BOOKE_PAGESZ_256M 18
|
||||
#define BOOKE_PAGESZ_512M 19
|
||||
#define BOOKE_PAGESZ_1G 20
|
||||
#define BOOKE_PAGESZ_2G 21
|
||||
#define BOOKE_PAGESZ_4G 22
|
||||
|
||||
#define MAS1_TSIZE_MASK 0x00000F80
|
||||
#define MAS1_TSIZE(x) (((x) << 7) & MAS1_TSIZE_MASK)
|
||||
#define HAS_EMBEDDED_HYPERVISOR /* E.HV Supported */
|
||||
|
||||
#define CACHE_LINE_SHIFT 6 /* 64 bytes per L1 cache line */
|
||||
|
||||
/* CoreNet Platform Cache Base */
|
||||
#define CPC_BASE (CCSRBAR + 0x10000)
|
||||
#define CPC_BASE (CCSRBAR + 0x10000)
|
||||
/* 8.2 CoreNet Platform Cache (CPC) Memory Map */
|
||||
#define CPCCSR0 (0x000)
|
||||
#define CPCSRCR1 (0x100)
|
||||
#define CPCSRCR0 (0x104)
|
||||
#define CPCHDBCR0 (0xF00)
|
||||
|
||||
/* T2080 LAW - Local Access Window (Memory Map) - RM 2.4 */
|
||||
#define CPCCSR0_CPCE (0x80000000 >> 0)
|
||||
#define CPCCSR0_CPCPE (0x80000000 >> 1)
|
||||
#define CPCCSR0_CPCFI (0x80000000 >> 10)
|
||||
#define CPCCSR0_CPCLFC (0x80000000 >> 21)
|
||||
#define CPCCSR0_SRAM_ENABLE (CPCCSR0_CPCE | CPCCSR0_CPCPE)
|
||||
|
||||
#ifdef CORE_E6500
|
||||
#define CPCSRCR0_SRAMSZ_64 (0x1 << 1) /* ways 14-15 */
|
||||
#define CPCSRCR0_SRAMSZ_256 (0x3 << 1) /* ways 8-15 */
|
||||
#define CPCSRCR0_SRAMSZ_512 (0x4 << 1) /* ways 0-15 */
|
||||
#else /* CORE E5500 */
|
||||
#define CPCSRCR0_SRAMSZ_64 (0x1 << 1) /* ways 6-7 */
|
||||
#define CPCSRCR0_SRAMSZ_128 (0x2 << 1) /* ways 4-7 */
|
||||
#define CPCSRCR0_SRAMSZ_256 (0x3 << 1) /* ways 0-7 */
|
||||
#endif
|
||||
#define CPCSRCR0_SRAMEN (0x1)
|
||||
|
||||
#define CPCHDBCR0_SPEC_DIS (0x80000000 >> 4)
|
||||
|
||||
#define CORENET_DCSR_SZ_1G 0x3
|
||||
|
||||
/* T1024/T2080 LAW - Local Access Window (Memory Map) - RM 2.4 */
|
||||
#define LAWBAR_BASE(n) (0xC00 + (n * 0x10))
|
||||
#define LAWBARH(n) *((volatile uint32_t*)(CCSRBAR + LAWBAR_BASE(n) + 0x0))
|
||||
#define LAWBARL(n) *((volatile uint32_t*)(CCSRBAR + LAWBAR_BASE(n) + 0x4))
|
||||
|
|
@ -225,13 +307,20 @@
|
|||
#define LAWAR_ENABLE (1<<31)
|
||||
#define LAWAR_TRGT_ID(id) (id<<20)
|
||||
|
||||
/* T2080 Global Source/Target ID Assignments - RM Table 2-1 */
|
||||
#define LAW_TRGT_DDR_1 0x10
|
||||
#define LAW_TRGT_BMAN 0x18 /* Buffer Manager (BMan) (control) */
|
||||
#define LAW_TRGT_CORENET 0x1E
|
||||
/* T1024/T2080 Global Source/Target ID Assignments - RM Table 2-1 */
|
||||
#define LAW_TRGT_PCIE1 0x00
|
||||
#define LAW_TRGT_PCIE2 0x01
|
||||
#define LAW_TRGT_PCIE3 0x02
|
||||
#define LAW_TRGT_DDR_1 0x10 /* Memory Complex 1 */
|
||||
#define LAW_TRGT_DDR_2 0x11
|
||||
#define LAW_TRGT_BMAN 0x18 /* Buffer Manager (control) */
|
||||
#define LAW_TRGT_DCSR 0x1D /* debug facilities */
|
||||
#define LAW_TRGT_CORENET 0x1E /* CCSR */
|
||||
#define LAW_TRGT_IFC 0x1F /* Integrated Flash Controller */
|
||||
#define LAW_TRGT_QMAN 0x3C /* Queue Manager (control) */
|
||||
#define LAW_TRGT_PSRAM 0x4A /* 160 KB Platform SRAM */
|
||||
|
||||
/* T2080 2.4.3 - size is equal to 2^(enum + 1) */
|
||||
/* T1024/T2080 2.4.3 - size is equal to 2^(enum + 1) */
|
||||
#define LAW_SIZE_4KB 0x0B
|
||||
#define LAW_SIZE_8KB 0x0C
|
||||
#define LAW_SIZE_16KB 0x0D
|
||||
|
|
@ -261,7 +350,6 @@
|
|||
#define LAW_SIZE_256GB 0x25
|
||||
#define LAW_SIZE_512GB 0x26
|
||||
#define LAW_SIZE_1TB 0x27
|
||||
|
||||
#endif
|
||||
|
||||
#ifndef CACHE_LINE_SIZE
|
||||
|
|
@ -271,6 +359,7 @@
|
|||
|
||||
/* MMU Assist Registers
|
||||
* E6500RM 2.13.10
|
||||
* E5500RM 2.16.6
|
||||
* E500CORERM 2.12.5
|
||||
*/
|
||||
#define MAS0 0x270
|
||||
|
|
@ -279,6 +368,7 @@
|
|||
#define MAS3 0x273
|
||||
#define MAS6 0x276
|
||||
#define MAS7 0x3B0
|
||||
#define MAS8 0x155
|
||||
#define MMUCSR0 0x3F4 /* MMU control and status register 0 */
|
||||
|
||||
#define MAS0_TLBSEL_MSK 0x30000000
|
||||
|
|
@ -319,14 +409,45 @@
|
|||
|
||||
|
||||
/* L1 Cache */
|
||||
#define L1CFG0 0x203 /* L1 Cache Configuration Register 0 */
|
||||
#define L1CSR0 0x3F2 /* L1 Data */
|
||||
#define L1CSR1 0x3F3 /* L1 Instruction */
|
||||
#define L1CFG0 0x203 /* L1 Cache Configuration Register 0 */
|
||||
#define L1CSR2 0x25E /* L1 Data Cache Control and Status Register 2 */
|
||||
#define L1CSR0 0x3F2 /* L1 Data */
|
||||
#define L1CSR1 0x3F3 /* L1 Instruction */
|
||||
|
||||
#define L1CSR_CPE 0x00010000 /* cache parity enable */
|
||||
#define L1CSR_CLFC 0x00000100 /* cache lock bits flash clear */
|
||||
#define L1CSR_CFI 0x00000002 /* cache flash invalidate */
|
||||
#define L1CSR_CE 0x00000001 /* cache enable */
|
||||
|
||||
/* L2 Cache */
|
||||
#if defined(CORE_E6500)
|
||||
/* MMRs */
|
||||
#define L2CSR0 0x000 /* L2 Cache Control and Status 0 */
|
||||
#define L2CSR1 0x004 /* L2 Cache Control and Status 1 */
|
||||
#define L2CFG0 0x008 /* L2 Cache Configuration */
|
||||
#else
|
||||
/* SPR */
|
||||
#define L2CFG0 0x207 /* L2 Cache Configuration Register 0 */
|
||||
#define L2CSR0 0x3F9 /* L2 Data Cache Control and Status Register 0 */
|
||||
#define L2CSR1 0x3FA /* L2 Data Cache Control and Status Register 1 */
|
||||
#endif
|
||||
|
||||
#define L2CSR0_L2FI 0x00200000 /* L2 Cache Flash Invalidate */
|
||||
#define L2CSR0_L2FL 0x00000800 /* L2 Cache Flush */
|
||||
#define L2CSR0_L2LFC 0x00000400 /* L2 Cache Lock Flash Clear */
|
||||
#define L2CSR0_L2PE 0x40000000 /* L2 Cache Parity/ECC Enable */
|
||||
#define L2CSR0_L2E 0x80000000 /* L2 Cache Enable */
|
||||
|
||||
#define L2CSR0_L2E 0x80000000 /* L2 Cache Enable */
|
||||
#define L2CSR0_L2PE 0x40000000 /* L2 Cache Parity/ECC Enable */
|
||||
#define L2CSR0_L2WP 0x1c000000 /* L2 I/D Way Partioning */
|
||||
#define L2CSR0_L2CM 0x03000000 /* L2 Cache Coherency Mode */
|
||||
#define L2CSR0_L2FI 0x00200000 /* L2 Cache Flash Invalidate */
|
||||
#define L2CSR0_L2IO 0x00100000 /* L2 Cache Instruction Only */
|
||||
#define L2CSR0_L2DO 0x00010000 /* L2 Cache Data Only */
|
||||
#define L2CSR0_L2REP 0x00003000 /* L2 Line Replacement Algo */
|
||||
|
||||
|
||||
#define SCCSRBAR 0x3FE /* Shifted CCSRBAR */
|
||||
|
||||
#define SPRN_DBSR 0x130 /* Debug Status Register */
|
||||
|
|
@ -361,10 +482,10 @@
|
|||
#define IVPR 0x03F /* Interrupt Vector Prefix Register */
|
||||
|
||||
/* Guest Interrupt Vectors */
|
||||
#define GIVOR2 (0x1B8)
|
||||
#define GIVOR3 (0x1B9)
|
||||
#define GIVOR4 (0x1BA)
|
||||
#define GIVOR8 (0x1BB)
|
||||
#define GIVOR2 (0x1B8)
|
||||
#define GIVOR3 (0x1B9)
|
||||
#define GIVOR4 (0x1BA)
|
||||
#define GIVOR8 (0x1BB)
|
||||
#define GIVOR13 (0x1BC)
|
||||
#define GIVOR14 (0x1BD)
|
||||
#define GIVOR35 (0x1D1)
|
||||
|
|
@ -376,6 +497,7 @@
|
|||
#define MSR_IS (1<<5) /* Book E Instruction address space */
|
||||
#define MSR_DE (1<<9) /* Debug Exception Enable */
|
||||
#define MSR_ME (1<<12) /* Machine check enable */
|
||||
#define MSR_EE (1<<15) /* External Interrupt enable */
|
||||
#define MSR_CE (1<<17) /* Critical interrupt enable */
|
||||
#define MSR_PR (1<<14) /* User mode (problem state) */
|
||||
|
||||
|
|
@ -412,8 +534,7 @@
|
|||
(((epn) & MAS2_EPN) | (wimge))
|
||||
#define BOOKE_MAS3(rpn, user, perms) \
|
||||
(((rpn) & MAS3_RPN) | (user) | (perms))
|
||||
#define BOOKE_MAS7(rpn) \
|
||||
(((unsigned long long)(rpn) >> 32) & MAS7_RPN)
|
||||
#define BOOKE_MAS7(urpn) (urpn)
|
||||
|
||||
/* Stringification */
|
||||
#ifndef WC_STRINGIFY
|
||||
|
|
@ -429,6 +550,7 @@
|
|||
})
|
||||
#define mtmsr(v) asm volatile("mtmsr %0" : : "r" (v))
|
||||
|
||||
|
||||
#ifndef __ASSEMBLER__
|
||||
|
||||
/* The data barrier / coherency safe functions for reading and writing */
|
||||
|
|
@ -474,7 +596,7 @@ static inline void set16(volatile unsigned short *addr, int val)
|
|||
);
|
||||
}
|
||||
|
||||
static inline unsigned int get32(const volatile unsigned *addr)
|
||||
static inline unsigned int get32(const volatile unsigned int *addr)
|
||||
{
|
||||
unsigned int ret;
|
||||
__asm__ __volatile__(
|
||||
|
|
@ -486,7 +608,7 @@ static inline unsigned int get32(const volatile unsigned *addr)
|
|||
);
|
||||
return ret;
|
||||
}
|
||||
static inline void set32(volatile unsigned *addr, unsigned int val)
|
||||
static inline void set32(volatile unsigned int *addr, unsigned int val)
|
||||
{
|
||||
__asm__ __volatile__(
|
||||
"sync;"
|
||||
|
|
@ -496,8 +618,9 @@ static inline void set32(volatile unsigned *addr, unsigned int val)
|
|||
}
|
||||
|
||||
/* C version in boot_ppc.c */
|
||||
extern void set_tlb(uint8_t tlb, uint8_t esel, uint32_t epn, uint64_t rpn,
|
||||
uint8_t perms, uint8_t wimge, uint8_t ts, uint8_t tsize, uint8_t iprot);
|
||||
extern void set_tlb(uint8_t tlb, uint8_t esel, uint32_t epn, uint32_t rpn,
|
||||
uint32_t urpn, uint8_t perms, uint8_t wimge, uint8_t ts, uint8_t tsize,
|
||||
uint8_t iprot);
|
||||
extern void disable_tlb1(uint8_t esel);
|
||||
extern void flush_cache(uint32_t start_addr, uint32_t size);
|
||||
|
||||
|
|
@ -506,7 +629,7 @@ extern void uart_init(void);
|
|||
|
||||
/* from boot_ppc_start.S */
|
||||
extern unsigned long long get_ticks(void);
|
||||
extern void wait_ticks(unsigned long);
|
||||
extern void wait_ticks(unsigned long long);
|
||||
extern unsigned long get_pc(void);
|
||||
extern void relocate_code(uint32_t *dest, uint32_t *src, uint32_t length);
|
||||
extern void invalidate_dcache(void);
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,90 @@
|
|||
OUTPUT_ARCH( "powerpc" )
|
||||
|
||||
ENTRY( _reset )
|
||||
|
||||
HEAP_SIZE = 4K; /* heap not used */
|
||||
STACK_SIZE = 128K;
|
||||
|
||||
MEMORY
|
||||
{
|
||||
/* DDR4 - 2GB (offset by destination address and 4KB boot region) */
|
||||
DRAM (rwx) : ORIGIN = @WOLFBOOT_STAGE1_LOAD_ADDR@,
|
||||
LENGTH = 0x7FFFFFFF - @WOLFBOOT_STAGE1_LOAD_ADDR@
|
||||
|
||||
/* L1 SRAM - 16KB */
|
||||
L1RAM (rwx) : ORIGIN = 0xF8F80000, LENGTH = 0x4000
|
||||
|
||||
/* L2 SRAM - 160KB */
|
||||
L2RAM (rwx) : ORIGIN = 0xFDFC0000, LENGTH = 0x28000
|
||||
}
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
/* boot code boot_ppc_start.S for _reset */
|
||||
.boot :
|
||||
{
|
||||
KEEP(*(.boot))
|
||||
} > DRAM
|
||||
. = ALIGN(4);
|
||||
|
||||
/* entry point branch offset to _reset */
|
||||
.reset :
|
||||
{
|
||||
KEEP(*(.reset))
|
||||
} > DRAM
|
||||
. = ALIGN(4);
|
||||
|
||||
.text :
|
||||
{
|
||||
_start_vector = .;
|
||||
KEEP(*(.isr_vector))
|
||||
. = ALIGN(256);
|
||||
_start_text = .;
|
||||
*(.text*)
|
||||
*(.rodata*)
|
||||
*(.sdata*)
|
||||
} > DRAM
|
||||
|
||||
/* Read-only sections, merged into text segment: */
|
||||
.interp : { *(.interp) }
|
||||
.hash : { *(.hash) }
|
||||
.dynsym : { *(.dynsym) }
|
||||
.dynstr : { *(.dynstr) }
|
||||
.gnu.version : { *(.gnu.version) }
|
||||
.gnu.version_r : { *(.gnu.version_r) }
|
||||
.gnu.hash : { *(.gnu.hash) }
|
||||
.rela.dyn : { *(.rela.dyn) }
|
||||
|
||||
_stored_data = .;
|
||||
|
||||
.data : AT (_stored_data)
|
||||
{
|
||||
_start_data = .;
|
||||
KEEP(*(.data*))
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.ramcode))
|
||||
. = ALIGN(4);
|
||||
_end_data = .;
|
||||
} > DRAM
|
||||
|
||||
.bss (NOLOAD) :
|
||||
{
|
||||
_start_bss = .;
|
||||
__bss_start__ = .;
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
_end_bss = .;
|
||||
__bss_end__ = .;
|
||||
. = ALIGN(16);
|
||||
_end = .;
|
||||
} > DRAM
|
||||
|
||||
}
|
||||
|
||||
PROVIDE(_start_heap = _end);
|
||||
|
||||
/* If relocated to DDR already then use stack end from DDR */
|
||||
/* If debugging and DDR is not ready, use L1 or L2 */
|
||||
PROVIDE(_end_stack = _end + HEAP_SIZE + STACK_SIZE );
|
||||
/* PROVIDE(_end_stack = ORIGIN(L2RAM) + (LENGTH(L2RAM)) ); */
|
||||
|
|
@ -0,0 +1,109 @@
|
|||
OUTPUT_ARCH( "powerpc" )
|
||||
|
||||
ENTRY( _reset )
|
||||
|
||||
/* Boot ROM out of reset mapped to 0xEFFFF000 */
|
||||
BASE_ADDR = @WOLFBOOT_STAGE1_FLASH_ADDR@;
|
||||
|
||||
LOADER_STAGE1_SIZE = @WOLFBOOT_STAGE1_SIZE@;
|
||||
|
||||
/* Boot initialization code */
|
||||
BOOTSTRAP_TLB = 0xEFFFF000;
|
||||
|
||||
/* Entry point where RCW directs code to execute from */
|
||||
BOOTSTRAP_ENTRY = 0xEFFFFFFC;
|
||||
|
||||
MEMORY
|
||||
{
|
||||
/* Boot Location */
|
||||
FLASH (rx) : ORIGIN = BASE_ADDR, LENGTH = LOADER_STAGE1_SIZE
|
||||
|
||||
/* L1 SRAM - 16KB */
|
||||
L1RAM (rwx) : ORIGIN = 0xF8F80000, LENGTH = 0x4000
|
||||
|
||||
/* L2 SRAM - 160KB */
|
||||
L2RAM (rwx) : ORIGIN = 0xFDFC0000, LENGTH = 0x28000
|
||||
|
||||
/* DDR - 2GB: Start at 16MB to avoid using 0x0 (NULL) addresses */
|
||||
DRAM (rwx) : ORIGIN = 0x1000000, LENGTH = 0x7FFFFFFF - 0x1000000
|
||||
}
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
/* boot code boot_ppc_start.S for _reset */
|
||||
.boot BOOTSTRAP_TLB :
|
||||
{
|
||||
KEEP(*(.boot))
|
||||
} = 0xFFFC
|
||||
. = ALIGN(4);
|
||||
|
||||
/* entry point branch offset to _reset */
|
||||
.reset BOOTSTRAP_ENTRY :
|
||||
{
|
||||
KEEP(*(.reset))
|
||||
} = 0x4
|
||||
. = ALIGN(4);
|
||||
|
||||
.text :
|
||||
{
|
||||
_start_vector = .;
|
||||
KEEP(*(.isr_vector))
|
||||
. = ALIGN(256);
|
||||
_start_text = .;
|
||||
*(.text*)
|
||||
*(.rodata*)
|
||||
*(.sdata*)
|
||||
} > FLASH
|
||||
|
||||
/* Read-only sections, merged into text segment: */
|
||||
.interp : { *(.interp) }
|
||||
.hash : { *(.hash) }
|
||||
.dynsym : { *(.dynsym) }
|
||||
.dynstr : { *(.dynstr) }
|
||||
.gnu.version : { *(.gnu.version) }
|
||||
.gnu.version_r : { *(.gnu.version_r) }
|
||||
.gnu.hash : { *(.gnu.hash) }
|
||||
.rela.dyn : { *(.rela.dyn) }
|
||||
|
||||
|
||||
.reloc :
|
||||
{
|
||||
_GOT2_TABLE_ = .;
|
||||
*(.got2)
|
||||
_FIXUP_TABLE_ = .;
|
||||
*(.fixup)
|
||||
} > FLASH
|
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
|
||||
__fixup_entries = (. - _FIXUP_TABLE_) >> 2;
|
||||
|
||||
__init_end = .;
|
||||
. = ALIGN(8);
|
||||
_stored_data = .;
|
||||
|
||||
.data : AT (_stored_data)
|
||||
{
|
||||
_start_data = .;
|
||||
KEEP(*(.data*))
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.ramcode))
|
||||
. = ALIGN(4);
|
||||
_end_data = .;
|
||||
} > DRAM
|
||||
|
||||
.bss (NOLOAD) :
|
||||
{
|
||||
_start_bss = .;
|
||||
__bss_start__ = .;
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
_end_bss = .;
|
||||
__bss_end__ = .;
|
||||
. = ALIGN(16);
|
||||
_end = .;
|
||||
} > DRAM
|
||||
|
||||
}
|
||||
|
||||
PROVIDE(_start_heap = ORIGIN(L2RAM));
|
||||
PROVIDE(_end_stack = ORIGIN(L2RAM) + (LENGTH(L2RAM)) );
|
||||
|
|
@ -21,13 +21,13 @@
|
|||
#include <stdint.h>
|
||||
#include "target.h"
|
||||
#include "printf.h"
|
||||
|
||||
#include "image.h" /* for RAMFUNCTION */
|
||||
#include "nxp_ppc.h"
|
||||
|
||||
/* Tested on T2080E Rev 1.1, e6500 core 2.0, PVR 8040_0120 and SVR 8538_0011 */
|
||||
|
||||
/* T2080 */
|
||||
#define SYS_CLK (600000000)
|
||||
#define SYS_CLK (600000000) /* 100MHz PLL with 6:1 = 600 MHz */
|
||||
|
||||
/* T2080 PC16552D Dual UART */
|
||||
#define BAUD_RATE 115200
|
||||
|
|
@ -56,7 +56,6 @@
|
|||
#define UART_LSR_TEMT (0x40) /* Transmitter empty */
|
||||
#define UART_LSR_THRE (0x20) /* Transmitter holding register empty */
|
||||
|
||||
#define GET_PHYS_HIGH(addr) (((uint64_t)(addr)) >> 32)
|
||||
|
||||
/* T2080 IFC (Integrated Flash Controller) - RM 13.3 */
|
||||
#define IFC_BASE (CCSRBAR + 0x00124000)
|
||||
|
|
@ -128,7 +127,6 @@ enum ifc_amask_sizes {
|
|||
|
||||
/* NOR Flash */
|
||||
#define FLASH_BASE 0xE8000000
|
||||
#define FLASH_BASE_PHYS (0xF00000000ULL | FLASH_BASE)
|
||||
|
||||
#define FLASH_BANK_SIZE (128*1024*1024)
|
||||
#define FLASH_PAGE_SIZE (1024) /* program buffer */
|
||||
|
|
@ -146,7 +144,7 @@ enum ifc_amask_sizes {
|
|||
#endif
|
||||
/* CPLD */
|
||||
#define CPLD_BASE 0xFFDF0000
|
||||
#define CPLD_BASE_PHYS (0xF00000000ULL | CPLD_BASE)
|
||||
#define CPLD_BASE_PHYS_HIGH 0xFULL
|
||||
|
||||
#define CPLD_SPARE 0x00
|
||||
#define CPLD_SATA_MUX_SEL 0x02
|
||||
|
|
@ -250,7 +248,6 @@ enum ifc_amask_sizes {
|
|||
|
||||
/* 12.4 DDR Memory Map */
|
||||
#define DDR_BASE (CCSRBAR + 0x8000)
|
||||
#define DDR_BASE_PHYS (0xF00000000ULL | DDR_BASE)
|
||||
|
||||
#define DDR_CS_BNDS(n) *((volatile uint32_t*)(DDR_BASE + 0x000 + (n * 8))) /* Chip select n memory bounds */
|
||||
#define DDR_CS_CONFIG(n) *((volatile uint32_t*)(DDR_BASE + 0x080 + (n * 4))) /* Chip select n configuration */
|
||||
|
|
@ -291,11 +288,14 @@ enum ifc_amask_sizes {
|
|||
#define DDR_SDRAM_MODE_7 *((volatile uint32_t*)(DDR_BASE + 0x210)) /* DDR SDRAM mode configuration 7 */
|
||||
#define DDR_SDRAM_MODE_8 *((volatile uint32_t*)(DDR_BASE + 0x214)) /* DDR SDRAM mode configuration 8 */
|
||||
#define DDR_SDRAM_MD_CNTL *((volatile uint32_t*)(DDR_BASE + 0x120)) /* DDR SDRAM mode control */
|
||||
#define DDR_SDRAM_INTERVAL *((volatile uint32_t*)(DDR_BASE + 0x124)) /* DDR SDRAM interval configuration */
|
||||
#define DDR_SDRAM_CLK_CNTL *((volatile uint32_t*)(DDR_BASE + 0x130)) /* DDR SDRAM clock control */
|
||||
|
||||
#define DDR_SDRAM_CFG_MEM_EN 0x80000000 /* SDRAM interface logic is enabled */
|
||||
#define DDR_SDRAM_CFG2_D_INIT 0x00000010 /* data initialization in progress */
|
||||
#define DDR_SDRAM_CFG_2_D_INIT 0x00000010 /* data initialization in progress */
|
||||
|
||||
|
||||
/* generic share NXP QorIQ driver code */
|
||||
#include "nxp_ppc.c"
|
||||
|
||||
|
||||
#ifdef DEBUG_UART
|
||||
|
|
@ -328,33 +328,40 @@ void uart_write(const char* buf, uint32_t sz)
|
|||
{
|
||||
uint32_t pos = 0;
|
||||
while (sz-- > 0) {
|
||||
while (!(UART_LSR(UART_SEL) & UART_LSR_THRE))
|
||||
;
|
||||
UART_THR(UART_SEL) = buf[pos++];
|
||||
char c = buf[pos++];
|
||||
if (c == '\n') { /* handle CRLF */
|
||||
while ((UART_LSR(UART_SEL) & UART_LSR_THRE) == 0);
|
||||
UART_THR(UART_SEL) = '\r';
|
||||
}
|
||||
while ((UART_LSR(UART_SEL) & UART_LSR_THRE) == 0);
|
||||
UART_THR(UART_SEL) = c;
|
||||
}
|
||||
}
|
||||
#endif /* DEBUG_UART */
|
||||
|
||||
static void set_law(uint8_t idx, uint32_t addr_h, uint32_t addr_l,
|
||||
uint32_t trgt_id, uint32_t law_sz)
|
||||
{
|
||||
LAWAR(idx) = 0; /* reset */
|
||||
LAWBARH(idx) = addr_h;
|
||||
LAWBARL(idx) = addr_l;
|
||||
LAWAR(idx) = (LAWAR_ENABLE | LAWAR_TRGT_ID(trgt_id) | law_sz);
|
||||
|
||||
/* Read back so that we sync the writes */
|
||||
(void)LAWAR(idx);
|
||||
}
|
||||
|
||||
void law_init(void)
|
||||
{
|
||||
/* Buffer Manager (BMan) (control) - probably not required */
|
||||
LAWAR(3) = 0; /* reset */
|
||||
LAWBARH(3) = 0xF;
|
||||
LAWBARL(3) = 0xF4000000;
|
||||
LAWAR(3) = LAWAR_ENABLE | LAWAR_TRGT_ID(LAW_TRGT_BMAN) | LAW_SIZE_32MB;
|
||||
set_law(3, 0xF, 0xF4000000, LAW_TRGT_BMAN, LAW_SIZE_32MB);
|
||||
}
|
||||
|
||||
static void hal_flash_init(void)
|
||||
{
|
||||
/* Set up LAW to map IFC(flash) to 0xf_e800_0000
|
||||
* This must be in place along with TLB before switching back to AS/TS=0
|
||||
*/
|
||||
|
||||
/* IFC - NOR Flash */
|
||||
LAWAR(1) = 0; /* reset */
|
||||
LAWBARH(1) = GET_PHYS_HIGH(FLASH_BASE_PHYS);
|
||||
LAWBARL(1) = FLASH_BASE;
|
||||
LAWAR(1) = LAWAR_ENABLE | LAWAR_TRGT_ID(LAW_TRGT_IFC) | LAW_SIZE_128MB;
|
||||
/* LAW is also set in boot_ppc_start.S:flash_law */
|
||||
set_law(1, FLASH_BASE_PHYS_HIGH, FLASH_BASE, LAW_TRGT_IFC, LAW_SIZE_128MB);
|
||||
|
||||
/* NOR IFC Flash Timing Parameters */
|
||||
IFC_FTIM0(0) = (IFC_FTIM0_NOR_TACSE(4) | \
|
||||
|
|
@ -378,7 +385,7 @@ static void hal_flash_init(void)
|
|||
IFC_CSOR(0) = 0x0000000C; /* TRHZ (80 clocks for read enable high) */
|
||||
}
|
||||
|
||||
void hal_ddr_init(void)
|
||||
static void hal_ddr_init(void)
|
||||
{
|
||||
#ifdef ENABLE_DDR
|
||||
/* If DDR is already enabled then just return */
|
||||
|
|
@ -449,21 +456,23 @@ void hal_ddr_init(void)
|
|||
asm volatile("sync;isync");
|
||||
|
||||
/* Map LAW for DDR */
|
||||
LAWAR (4) = 0; /* reset */
|
||||
LAWBARH(4) = 0;
|
||||
LAWBARL(4) = 0x0000000;
|
||||
LAWAR (4) = LAWAR_ENABLE | LAWAR_TRGT_ID(LAW_TRGT_DDR_1) | LAW_SIZE_8GB;
|
||||
set_law(4, 0, 0, LAW_TRGT_DDR_1, LAW_SIZE_2GB);
|
||||
|
||||
/* Wait for data initialization is complete */
|
||||
while ((DDR_SDRAM_CFG_2 & DDR_SDRAM_CFG2_D_INIT));
|
||||
while ((DDR_SDRAM_CFG_2 & DDR_SDRAM_CFG_2_D_INIT));
|
||||
|
||||
/* DDR - TBL=1, Entry 19 */
|
||||
set_tlb(1, 19, DDR_ADDRESS, 0,
|
||||
set_tlb(1, 19, DDR_ADDRESS, DDR_ADDRESS, 0,
|
||||
MAS3_SX | MAS3_SW | MAS3_SR, 0,
|
||||
0, BOOKE_PAGESZ_2G, 1);
|
||||
#endif
|
||||
}
|
||||
|
||||
void hal_early_init(void)
|
||||
{
|
||||
hal_ddr_init();
|
||||
}
|
||||
|
||||
static void hal_cpld_init(void)
|
||||
{
|
||||
#ifdef ENABLE_CPLD
|
||||
|
|
@ -479,7 +488,7 @@ static void hal_cpld_init(void)
|
|||
IFC_FTIM3(3) = 0;
|
||||
|
||||
/* CPLD IFC Definitions (CS3) */
|
||||
IFC_CSPR_EXT(3) = (0xF);
|
||||
IFC_CSPR_EXT(3) = CPLD_BASE_PHYS_HIGH;
|
||||
IFC_CSPR(3) = (IFC_CSPR_PHYS_ADDR(CPLD_BASE) |
|
||||
IFC_CSPR_PORT_SIZE_16 |
|
||||
IFC_CSPR_MSEL_GPCM |
|
||||
|
|
@ -488,13 +497,11 @@ static void hal_cpld_init(void)
|
|||
IFC_CSOR(3) = 0;
|
||||
|
||||
/* IFC - CPLD */
|
||||
LAWAR (2) = 0; /* reset */
|
||||
LAWBARH(2) = GET_PHYS_HIGH(CPLD_BASE_PHYS);
|
||||
LAWBARL(2) = CPLD_BASE;
|
||||
LAWAR (2) = LAWAR_ENABLE | LAWAR_TRGT_ID(LAW_TRGT_IFC) | LAW_SIZE_4KB;
|
||||
set_law(2, CPLD_BASE_PHYS_HIGH, CPLD_BASE,
|
||||
LAW_TRGT_IFC, LAW_SIZE_4KB);
|
||||
|
||||
/* CPLD - TBL=1, Entry 17 */
|
||||
set_tlb(1, 17, CPLD_BASE, CPLD_BASE_PHYS,
|
||||
set_tlb(1, 17, CPLD_BASE, CPLD_BASE, CPLD_BASE_PHYS_HIGH,
|
||||
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
|
||||
0, BOOKE_PAGESZ_4K, 1);
|
||||
#endif
|
||||
|
|
@ -587,6 +594,6 @@ void hal_prepare_boot(void)
|
|||
#ifdef MMU
|
||||
void* hal_get_dts_address(void)
|
||||
{
|
||||
return (void*)WOLFBOOT_LOAD_DTS_ADDRESS;
|
||||
return (void*)WOLFBOOT_DTS_BOOT_ADDRESS;
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -40,6 +40,7 @@ SECTIONS
|
|||
{
|
||||
_start_vector = .;
|
||||
KEEP(*(.isr_vector))
|
||||
. = ALIGN(256);
|
||||
*(.text*)
|
||||
*(.rodata*)
|
||||
*(.sdata*)
|
||||
|
|
|
|||
|
|
@ -333,7 +333,7 @@
|
|||
#define SPI1_BASE (0x40013000) /* SPI1 base address */
|
||||
#endif
|
||||
|
||||
#define SPI1_APB2_CLOCK_ER_VAL (1 << 12)
|
||||
#define SPI1_APB2_CLOCK_ER_VAL (1 << 12)
|
||||
|
||||
#define SPI1_CR1 (*(volatile uint32_t *)(SPI1_BASE))
|
||||
#define SPI1_CR2 (*(volatile uint32_t *)(SPI1_BASE + 0x04))
|
||||
|
|
@ -342,21 +342,21 @@
|
|||
|
||||
#define SPI_CR1_CLOCK_PHASE (1 << 0)
|
||||
#define SPI_CR1_CLOCK_POLARITY (1 << 1)
|
||||
#define SPI_CR1_MASTER (1 << 2)
|
||||
#define SPI_CR1_BAUDRATE (0x07 << 3)
|
||||
#define SPI_CR1_SPI_EN (1 << 6)
|
||||
#define SPI_CR1_LSBFIRST (1 << 7)
|
||||
#define SPI_CR1_SSI (1 << 8)
|
||||
#define SPI_CR1_SSM (1 << 9)
|
||||
#define SPI_CR1_MASTER (1 << 2)
|
||||
#define SPI_CR1_BAUDRATE (0x07 << 3)
|
||||
#define SPI_CR1_SPI_EN (1 << 6)
|
||||
#define SPI_CR1_LSBFIRST (1 << 7)
|
||||
#define SPI_CR1_SSI (1 << 8)
|
||||
#define SPI_CR1_SSM (1 << 9)
|
||||
#define SPI_CR1_16BIT_FORMAT (1 << 11)
|
||||
#define SPI_CR1_TX_CRC_NEXT (1 << 12)
|
||||
#define SPI_CR1_HW_CRC_EN (1 << 13)
|
||||
#define SPI_CR1_BIDIOE (1 << 14)
|
||||
#define SPI_CR2_SSOE (1 << 2)
|
||||
#define SPI_CR1_TX_CRC_NEXT (1 << 12)
|
||||
#define SPI_CR1_HW_CRC_EN (1 << 13)
|
||||
#define SPI_CR1_BIDIOE (1 << 14)
|
||||
#define SPI_CR2_SSOE (1 << 2)
|
||||
|
||||
#define SPI_SR_RX_NOTEMPTY (1 << 0)
|
||||
#define SPI_SR_TX_EMPTY (1 << 1)
|
||||
#define SPI_SR_BUSY (1 << 7)
|
||||
#define SPI_SR_RX_NOTEMPTY (1 << 0)
|
||||
#define SPI_SR_TX_EMPTY (1 << 1)
|
||||
#define SPI_SR_BUSY (1 << 7)
|
||||
|
||||
|
||||
/* GPIO */
|
||||
|
|
|
|||
|
|
@ -1330,7 +1330,7 @@ void RAMFUNCTION ext_flash_unlock(void)
|
|||
#ifdef MMU
|
||||
void* hal_get_dts_address(void)
|
||||
{
|
||||
return (void*)WOLFBOOT_LOAD_DTS_ADDRESS;
|
||||
return (void*)WOLFBOOT_DTS_BOOT_ADDRESS;
|
||||
}
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -668,7 +668,7 @@ static inline int wb_flash_write_verify_word(struct wolfBoot_image *img,
|
|||
#define UBOOT_IMG_HDR_SZ 64
|
||||
|
||||
/* --- Flattened Device Tree Blob */
|
||||
#define UBOOT_FDT_MAGIC 0xEDFE0DD0UL
|
||||
#define UBOOT_FDT_MAGIC 0xEDFE0DD0UL
|
||||
|
||||
#ifndef EXT_ENCRYPTED
|
||||
#define WOLFBOOT_MAX_SPACE (WOLFBOOT_PARTITION_SIZE - \
|
||||
|
|
|
|||
|
|
@ -32,6 +32,11 @@
|
|||
#include <stdint.h>
|
||||
#include "image.h"
|
||||
|
||||
/* SPI transfer flags */
|
||||
#define SPI_XFER_FLAG_NONE 0x0
|
||||
#define SPI_XFER_FLAG_CONTINUE 0x1 /* keep CS asserted */
|
||||
|
||||
|
||||
#if defined(SPI_FLASH) || defined(WOLFBOOT_TPM) || defined(QSPI_FLASH) || \
|
||||
defined(OCTOSPI_FLASH)
|
||||
|
||||
|
|
@ -64,10 +69,6 @@ uint8_t spi_read(void);
|
|||
#endif
|
||||
|
||||
#ifdef WOLFBOOT_TPM
|
||||
/* SPI transfer flags */
|
||||
#define SPI_XFER_FLAG_NONE 0x0
|
||||
#define SPI_XFER_FLAG_CONTINUE 0x1 /* keep CS asserted */
|
||||
|
||||
/* Perform a SPI transaction.
|
||||
* Set flags == SPI_XFER_FLAG_CONTINUE to keep CS asserted after transfer. */
|
||||
int spi_xfer(int cs, const uint8_t* tx, uint8_t* rx, uint32_t sz, int flags);
|
||||
|
|
|
|||
|
|
@ -639,6 +639,10 @@ endif
|
|||
ifeq ($(ELF),1)
|
||||
CFLAGS+=-DWOLFBOOT_ELF
|
||||
OBJS += src/elf.o
|
||||
|
||||
ifneq ($(DEBUG_ELF),)
|
||||
CFLAGS+=-DDEBUG_ELF=$(DEBUG_ELF)
|
||||
endif
|
||||
endif
|
||||
|
||||
ifeq ($(MULTIBOOT2),1)
|
||||
|
|
|
|||
|
|
@ -33,7 +33,7 @@ extern unsigned int _start_data;
|
|||
extern unsigned int _end_data;
|
||||
|
||||
extern void main(void);
|
||||
extern void hal_ddr_init(void);
|
||||
extern void hal_early_init(void);
|
||||
|
||||
void write_tlb(uint32_t mas0, uint32_t mas1, uint32_t mas2, uint32_t mas3,
|
||||
uint32_t mas7)
|
||||
|
|
@ -46,9 +46,9 @@ void write_tlb(uint32_t mas0, uint32_t mas1, uint32_t mas2, uint32_t mas3,
|
|||
asm volatile("isync;msync;tlbwe;isync");
|
||||
}
|
||||
|
||||
void set_tlb(uint8_t tlb, uint8_t esel, uint32_t epn, uint64_t rpn,
|
||||
uint8_t perms, uint8_t wimge,
|
||||
uint8_t ts, uint8_t tsize, uint8_t iprot)
|
||||
void set_tlb(uint8_t tlb, uint8_t esel, uint32_t epn, uint32_t rpn,
|
||||
uint32_t urpn, uint8_t perms, uint8_t wimge, uint8_t ts, uint8_t tsize,
|
||||
uint8_t iprot)
|
||||
{
|
||||
uint32_t _mas0, _mas1, _mas2, _mas3, _mas7;
|
||||
|
||||
|
|
@ -56,7 +56,7 @@ void set_tlb(uint8_t tlb, uint8_t esel, uint32_t epn, uint64_t rpn,
|
|||
_mas1 = BOOKE_MAS1(1, iprot, 0, ts, tsize);
|
||||
_mas2 = BOOKE_MAS2(epn, wimge);
|
||||
_mas3 = BOOKE_MAS3(rpn, 0, perms);
|
||||
_mas7 = BOOKE_MAS7(rpn);
|
||||
_mas7 = BOOKE_MAS7(urpn);
|
||||
|
||||
write_tlb(_mas0, _mas1, _mas2, _mas3, _mas7);
|
||||
}
|
||||
|
|
@ -82,7 +82,7 @@ void invalidate_tlb(int tlb)
|
|||
mtspr(MMUCSR0, 0x2);
|
||||
}
|
||||
|
||||
void __attribute((weak)) hal_ddr_init(void)
|
||||
void __attribute((weak)) hal_early_init(void)
|
||||
{
|
||||
|
||||
}
|
||||
|
|
@ -91,7 +91,7 @@ void boot_entry_C(void)
|
|||
{
|
||||
register unsigned int *dst, *src, *end;
|
||||
|
||||
hal_ddr_init();
|
||||
hal_early_init();
|
||||
|
||||
/* Copy the .data section from flash to RAM */
|
||||
src = (unsigned int*)&_stored_data;
|
||||
|
|
@ -149,11 +149,9 @@ void do_boot(const uint32_t *app_offset)
|
|||
#ifndef BUILD_LOADER_STAGE1
|
||||
uint32_t msr;
|
||||
#endif
|
||||
|
||||
#ifdef MMU
|
||||
/* TODO: Determine if the dts_offset needs passed as argument */
|
||||
(void)dts_offset;
|
||||
#endif
|
||||
typedef void (*boot_entry)(uintptr_t r3, uintptr_t r4, uintptr_t r5, uintptr_t r6,
|
||||
uintptr_t r7, uintptr_t r8, uintptr_t r9);
|
||||
boot_entry entry = (boot_entry)app_offset;
|
||||
|
||||
#ifndef BUILD_LOADER_STAGE1
|
||||
/* invalidate cache */
|
||||
|
|
@ -165,8 +163,20 @@ void do_boot(const uint32_t *app_offset)
|
|||
mtmsr(msr);
|
||||
#endif
|
||||
|
||||
/* do branch unconditionally */
|
||||
asm volatile("mtlr %0; blr":: "r"(app_offset));
|
||||
/* ePAPR (Embedded Power Architecture Platform Requirements)
|
||||
* https://elinux.org/images/c/cf/Power_ePAPR_APPROVED_v1.1.pdf
|
||||
*/
|
||||
entry(
|
||||
#ifdef MMU
|
||||
(uintptr_t)dts_offset, /* r3 = dts address */
|
||||
#else
|
||||
0,
|
||||
#endif
|
||||
0, 0,
|
||||
EPAPR_MAGIC, /* r6 = ePAPR magic */
|
||||
WOLFBOOT_PARTITION_SIZE, /* r7 = Size of Initial Mapped Area (IMA) */
|
||||
0, 0
|
||||
);
|
||||
}
|
||||
|
||||
void arch_reboot(void) {}
|
||||
|
|
|
|||
|
|
@ -30,7 +30,7 @@
|
|||
#ifndef INTVEC_ADDR
|
||||
/* workaround to use isr_empty for all interrupts, for real IRQ's adjust the
|
||||
* offset and define additional interrupts at those offsets */
|
||||
#define INTVEC_ADDR(n) (BOOT_ROM_SIZE + (n * 0x0))
|
||||
#define INTVEC_ADDR(n) isr_empty@l
|
||||
#endif
|
||||
|
||||
/* Additional cores (mp) assembly code for core minimum startup and spin table.
|
||||
|
|
@ -40,12 +40,12 @@
|
|||
.align 12
|
||||
_mp_page_start:
|
||||
/* Time base, MAS7 and machine check pin enable */
|
||||
lis r0, (HID0_EMCP | HID0_TBEN | HID0_ENMAS7)@h
|
||||
lis r0, (HID0_EMCP | HID0_TBEN | HID0_ENMAS7)@h
|
||||
ori r0, r0, (HID0_EMCP | HID0_TBEN | HID0_ENMAS7)@l
|
||||
mtspr SPRN_HID0, r0
|
||||
|
||||
/* enable branch prediction */
|
||||
lis r0, (BUCSR_ENABLE)@h
|
||||
lis r0, (BUCSR_ENABLE)@h
|
||||
ori r0, r0, (BUCSR_ENABLE)@l
|
||||
mtspr SPRN_BUCSR, r0
|
||||
|
||||
|
|
@ -55,7 +55,7 @@ _mp_page_start:
|
|||
mttbu r3
|
||||
|
||||
/* Enable/invalidate the I-Cache */
|
||||
lis r2, (L1CSR_CFI|L1CSR_CLFC)@h
|
||||
lis r2, (L1CSR_CFI|L1CSR_CLFC)@h
|
||||
ori r2, r2, (L1CSR_CFI|L1CSR_CLFC)@l
|
||||
mtspr L1CSR1, r2
|
||||
1:
|
||||
|
|
@ -63,7 +63,7 @@ _mp_page_start:
|
|||
and. r1, r3, r2
|
||||
bne 1b
|
||||
|
||||
lis r3, (L1CSR_CPE|L1CSR_CE)@h
|
||||
lis r3, (L1CSR_CPE|L1CSR_CE)@h
|
||||
ori r3, r3, (L1CSR_CPE|L1CSR_CE)@l
|
||||
mtspr L1CSR1,r3
|
||||
isync
|
||||
|
|
@ -81,7 +81,7 @@ _mp_page_start:
|
|||
and. r1, r3, r2
|
||||
bne 1b
|
||||
|
||||
lis r3, (L1CSR_CPE|L1CSR_CE)@h
|
||||
lis r3, (L1CSR_CPE|L1CSR_CE)@h
|
||||
ori r3, r3, (L1CSR_CPE|L1CSR_CE)@l
|
||||
mtspr L1CSR0, r3
|
||||
isync
|
||||
|
|
@ -91,7 +91,7 @@ _mp_page_start:
|
|||
beq 2b
|
||||
|
||||
/* Get our PIR to figure out our table entry */
|
||||
lis r3, TORESET(_spin_table)@h
|
||||
lis r3, TORESET(_spin_table)@h
|
||||
ori r3, r3, TORESET(_spin_table)@l
|
||||
|
||||
/* Determine base address for the core (use r10) */
|
||||
|
|
|
|||
|
|
@ -77,8 +77,8 @@ All TLBs for boot will be in TLB1 and supervisor mode (not user)
|
|||
.global isr_empty
|
||||
.global _end_stack
|
||||
|
||||
/* NXP P1021 First stage loader requires GOT for PIC and relocation */
|
||||
#if defined(PLATFORM_nxp_p1021) && defined(BUILD_LOADER_STAGE1)
|
||||
/* First stage loader requires GOT for PIC and relocation */
|
||||
#if defined(NO_XIP) && defined(BUILD_LOADER_STAGE1)
|
||||
#define USE_GOT
|
||||
#endif
|
||||
|
||||
|
|
@ -113,7 +113,7 @@ GOT_ENTRY(__init_end)
|
|||
#ifndef INTVEC_ADDR
|
||||
/* workaround to use isr_empty for all interrupts, for real IRQ's adjust the
|
||||
* offset and define additional interrupts at those offsets */
|
||||
#define INTVEC_ADDR(n) (BOOT_ROM_SIZE + (n * 0x0))
|
||||
#define INTVEC_ADDR(n) isr_empty@l
|
||||
#endif
|
||||
|
||||
|
||||
|
|
@ -144,20 +144,22 @@ reset_exceptions:
|
|||
mttbl r0 /* prevent FIT and WDT exceptions */
|
||||
mttbu r0
|
||||
mtspr SPRN_TSR, r1 /* clear all timer exception status */
|
||||
#ifdef PLATFORM_nxp_p1021
|
||||
mtspr SPRN_TCR, r0 /* disable all timers */
|
||||
#endif
|
||||
mtspr SPRN_ESR, r0 /* clear exception syndrome register */
|
||||
mtspr SPRN_MCSR, r0 /* clear machine check syndrome register */
|
||||
mtxer r0 /* clear integer exception register */
|
||||
|
||||
#if defined(CORE_E5500) || defined(CORE_E6500)
|
||||
mtspr MAS8, r0 /* clear MAS8 used with Embedded Hypervisor */
|
||||
#endif
|
||||
|
||||
hardware_reg:
|
||||
/* Time base, MAS7 and machine check pin enable */
|
||||
lis r0, (HID0_EMCP | HID0_TBEN | HID0_ENMAS7)@h
|
||||
lis r0, (HID0_EMCP | HID0_TBEN | HID0_ENMAS7)@h
|
||||
ori r0, r0, (HID0_EMCP | HID0_TBEN | HID0_ENMAS7)@l
|
||||
mtspr SPRN_HID0, r0
|
||||
|
||||
#if defined(PLATFORM_nxp_p1021) && !defined(BUILD_LOADER_STAGE1)
|
||||
#if defined(CORE_E500) && !defined(BUILD_LOADER_STAGE1)
|
||||
/* Set addr streaming & broadcast
|
||||
* and optimized sync instruction (if rev 5.0 or greater) */
|
||||
li r0, (HID1_ASTME | HID1_ABE)@l
|
||||
|
|
@ -172,15 +174,17 @@ hardware_reg:
|
|||
#ifndef BUILD_LOADER_STAGE1
|
||||
branch_prediction:
|
||||
/* enable branch prediction */
|
||||
lis r0, (BUCSR_ENABLE)@h
|
||||
lis r0, (BUCSR_ENABLE)@h
|
||||
ori r0, r0, (BUCSR_ENABLE)@l
|
||||
mtspr SPRN_BUCSR, r0
|
||||
#endif
|
||||
|
||||
startup_init:
|
||||
|
||||
/* Invalidate L1 instruction and data cache */
|
||||
bl invalidate_icache;
|
||||
bl invalidate_dcache;
|
||||
li r0, L1CSR_CFI
|
||||
mtspr L1CSR1, r0
|
||||
mtspr L1CSR0, r0
|
||||
|
||||
/* Clear debug status register - read and write */
|
||||
mfspr r1, SPRN_DBSR
|
||||
|
|
@ -264,7 +268,7 @@ setup_interrupts:
|
|||
|
||||
/* Setup interrupt vectors */
|
||||
lis r1, (_start_vector)@h
|
||||
mtspr IVPR, r1
|
||||
mtspr IVPR, r1 /* set the 48-bit high-order prefix address */
|
||||
|
||||
#ifdef ENABLE_INTERRUPTS
|
||||
li r1, INTVEC_ADDR(0)
|
||||
|
|
@ -304,9 +308,9 @@ setup_interrupts:
|
|||
#if CCSRBAR_DEF != CCSRBAR_PHYS
|
||||
|
||||
/* Use R8 = new, R9 = old virtual */
|
||||
lis r8, CCSRBAR@h
|
||||
lis r8, CCSRBAR@h
|
||||
ori r8, r8, CCSRBAR@l
|
||||
lis r9, (CCSRBAR + 0x1000)@h
|
||||
lis r9, (CCSRBAR + 0x1000)@h
|
||||
ori r9, r9, (CCSRBAR + 0x1000)@l
|
||||
|
||||
create_temp_ccsr:
|
||||
|
|
@ -340,13 +344,13 @@ infinite_debug_loop:
|
|||
ccsr_temp_law:
|
||||
/* CCSR - LAW0 (Temp CoreNet 4K) */
|
||||
#define CCSR_TEMP_LAW (LAWAR_ENABLE | LAWAR_TRGT_ID(LAW_TRGT_CORENET) | LAW_SIZE_4KB)
|
||||
lis r0, CCSRBAR_PHYS_HIGH@h
|
||||
lis r0, CCSRBAR_PHYS_HIGH@h
|
||||
ori r0, r0, CCSRBAR_PHYS_HIGH@l
|
||||
lis r1, CCSRBAR_DEF@h
|
||||
lis r1, CCSRBAR_DEF@h
|
||||
ori r1, r1, CCSRBAR_DEF@l
|
||||
lis r2, CCSR_TEMP_LAW@h
|
||||
lis r2, CCSR_TEMP_LAW@h
|
||||
ori r2, r2, CCSR_TEMP_LAW@l
|
||||
stw r0, LAWBAR_BASE(0)(r9) /* LAWBARH */
|
||||
stw r0, LAWBAR_BASE(0)(r9) /* LAWBARH */
|
||||
stw r1, LAWBAR_BASE(0)+4(r9) /* LAWBARL */
|
||||
sync
|
||||
stw r2, LAWBAR_BASE(0)+8(r9) /* LAWAR */
|
||||
|
|
@ -359,12 +363,12 @@ read_old_ccsr:
|
|||
isync
|
||||
|
||||
write_new_ccsrbar:
|
||||
lis r0, CCSRBAR_PHYS_HIGH@h
|
||||
lis r0, CCSRBAR_PHYS_HIGH@h
|
||||
ori r0, r0, CCSRBAR_PHYS_HIGH@l
|
||||
lis r1, CCSRBAR@h
|
||||
lis r1, CCSRBAR@h
|
||||
ori r1, r1, CCSRBAR@l
|
||||
#define CCSRAR_C 0x80000000 /* Commit */
|
||||
lis r2, CCSRAR_C@h
|
||||
lis r2, CCSRAR_C@h
|
||||
ori r2, r2, CCSRAR_C@l
|
||||
stw r0, 0(r9) /* CCSRBARH */
|
||||
sync
|
||||
|
|
@ -381,7 +385,7 @@ write_new_ccsrbar:
|
|||
lwz r0, 0(r9)
|
||||
isync
|
||||
/* write new CCSBAR */
|
||||
lis r0, (CCSRBAR_PHYS_HIGH << 20) | (CCSRBAR >> 12)@h
|
||||
lis r0, (CCSRBAR_PHYS_HIGH << 20) | (CCSRBAR >> 12)@h
|
||||
ori r0, r0, (CCSRBAR_PHYS_HIGH << 20) | (CCSRBAR >> 12)@l
|
||||
stw r0, 0(r9)
|
||||
sync
|
||||
|
|
@ -413,21 +417,21 @@ boot_page:
|
|||
ccsr_tlb:
|
||||
/* CCSRBAR: TLB 1, Entry 1, Supervisor R/W, IG, TS=0, 1M/16M, IPROT */
|
||||
set_tlb(1, 1,
|
||||
CCSRBAR, CCSRBAR, 0,
|
||||
CCSRBAR, CCSRBAR, CCSRBAR_PHYS_HIGH,
|
||||
MAS3_SX | MAS3_SR | MAS3_SW, MAS2_I | MAS2_G, 0,
|
||||
CCSRBAR_SIZE, 1, r3);
|
||||
|
||||
#ifdef CORE_E6500
|
||||
#if defined(CORE_E5500) || defined(CORE_E6500)
|
||||
ccsr_law:
|
||||
/* CCSR - LAW0 (CoreNet 16MB) */
|
||||
#define CCSR_LAW (LAWAR_ENABLE | LAWAR_TRGT_ID(LAW_TRGT_CORENET) | LAW_SIZE_16MB)
|
||||
lis r9, CCSRBAR + LAWBAR_BASE(0)@h
|
||||
lis r9, CCSRBAR + LAWBAR_BASE(0)@h
|
||||
ori r9, r9, CCSRBAR + LAWBAR_BASE(0)@l
|
||||
lis r0, CCSRBAR_PHYS_HIGH@h
|
||||
lis r0, CCSRBAR_PHYS_HIGH@h
|
||||
ori r0, r0, CCSRBAR_PHYS_HIGH@l
|
||||
lis r1, CCSRBAR@h
|
||||
lis r1, CCSRBAR@h
|
||||
ori r1, r1, CCSRBAR@l
|
||||
lis r2, CCSR_LAW@h
|
||||
lis r2, CCSR_LAW@h
|
||||
ori r2, r2, CCSR_LAW@l
|
||||
stw r0, 0(r9) /* LAWBARH */
|
||||
stw r1, 4(r9) /* LAWBARL */
|
||||
|
|
@ -435,21 +439,21 @@ ccsr_law:
|
|||
stw r2, 8(r9) /* LAWAR */
|
||||
lwz r2, 8(r9) /* read back LAWAR (per 2.3.2 Configuring Local Access Windows) */
|
||||
isync
|
||||
#endif /* CORE_E6500 */
|
||||
#endif /* CORE_E5500 || CORE_E6500 */
|
||||
|
||||
#ifdef FLASH_BASE_ADDR
|
||||
#ifdef CORE_E6500
|
||||
/* Memory Mapped NOR Flash (128MB) at 0xE8000000 */
|
||||
#if defined(CORE_E5500) || defined(CORE_E6500)
|
||||
/* Memory Mapped NOR Flash (64/128MB) at 0xEC000000/0xE8000000 */
|
||||
flash_law:
|
||||
/* FLASH - LAW1 (IFC 128MB) */
|
||||
#define FLASH_LAW (LAWAR_ENABLE | LAWAR_TRGT_ID(LAW_TRGT_IFC) | LAW_SIZE_128MB)
|
||||
lis r9, CCSRBAR + LAWBAR_BASE(1)@h
|
||||
/* FLASH - LAW1 (IFC 64/128MB) */
|
||||
#define FLASH_LAW (LAWAR_ENABLE | LAWAR_TRGT_ID(LAW_TRGT_IFC) | FLASH_LAW_SIZE)
|
||||
lis r9, CCSRBAR + LAWBAR_BASE(1)@h
|
||||
ori r9, r9, CCSRBAR + LAWBAR_BASE(1)@l
|
||||
lis r0, FLASH_BASE_PHYS_HIGH@h
|
||||
lis r0, FLASH_BASE_PHYS_HIGH@h
|
||||
ori r0, r0, FLASH_BASE_PHYS_HIGH@l
|
||||
lis r1, FLASH_BASE_ADDR@h
|
||||
lis r1, FLASH_BASE_ADDR@h
|
||||
ori r1, r1, FLASH_BASE_ADDR@l
|
||||
lis r2, FLASH_LAW@h
|
||||
lis r2, FLASH_LAW@h
|
||||
ori r2, r2, FLASH_LAW@l
|
||||
stw r0, 0(r9) /* LAWBARH */
|
||||
stw r1, 4(r9) /* LAWBARL */
|
||||
|
|
@ -458,11 +462,12 @@ flash_law:
|
|||
lwz r2, 8(r9) /* read back LAWAR (per 2.3.2 Configuring Local Access Windows) */
|
||||
isync
|
||||
flash_tlb:
|
||||
/* Flash: TLB 1, Entry 7, Super X/R, W, TS=0, 128M, IPROT */
|
||||
/* Flash: TLB 1, Entry 7, Super X/R/W, W, TS=0, 64/128M, IPROT */
|
||||
/* Write is required for Write/Erase using CFI commands to base */
|
||||
set_tlb(1, 7,
|
||||
FLASH_BASE_ADDR, FLASH_BASE_ADDR, FLASH_BASE_PHYS_HIGH,
|
||||
MAS3_SX | MAS3_SR, MAS2_W, 0,
|
||||
BOOKE_PAGESZ_128M, 1, r3);
|
||||
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_W | MAS2_G, 0,
|
||||
FLASH_TLB_PAGESZ, 1, r3);
|
||||
#else
|
||||
flash_tlb:
|
||||
/* For TS/AS=1 map boot ROM */
|
||||
|
|
@ -471,13 +476,14 @@ flash_tlb:
|
|||
FLASH_BASE_ADDR, FLASH_BASE_ADDR, 0,
|
||||
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0,
|
||||
BOOKE_PAGESZ_1M, 1, r3);
|
||||
#endif /* CORE_E6500 */
|
||||
#endif /* CORE_E5500 || CORE_E6500 */
|
||||
#endif /* FLASH_BASE_ADDR */
|
||||
|
||||
#ifdef ENABLE_DDR
|
||||
/* Enable use of the DDR if available (like 2nd stage) */
|
||||
#if defined(CORE_E500) && defined(ENABLE_DDR)
|
||||
#ifdef BUILD_LOADER_STAGE1
|
||||
/* use cache inhibited for first stage loader to avoid
|
||||
* L1 cache as SRAM issues */
|
||||
* L1 cache as SRAM issues */
|
||||
#define DDR_WING (MAS2_I | MAS2_G)
|
||||
#else
|
||||
#define DDR_WING (MAS2_G)
|
||||
|
|
@ -492,22 +498,21 @@ flash_tlb:
|
|||
DDR_ADDRESS + (256*1024*1024), DDR_ADDRESS + (256*1024*1024), 0,
|
||||
MAS3_SX | MAS3_SW | MAS3_SR, DDR_WING, 0,
|
||||
BOOKE_PAGESZ_256M, 0, r3);
|
||||
#endif
|
||||
#endif /* CORE_E500 && ENABLE_DDR */
|
||||
|
||||
#ifdef ENABLE_L2_CACHE
|
||||
#ifdef CORE_E6500 /* --- L2 E6500 --- */
|
||||
#ifdef L2SRAM_ADDR
|
||||
l2_sram_law:
|
||||
/* L2 SRAM - LAW2 (DDR 256KB) */
|
||||
#define L2SRAM_LAW \
|
||||
(LAWAR_ENABLE | LAWAR_TRGT_ID(LAW_TRGT_DDR_1) | LAW_SIZE_256KB)
|
||||
lis r9, CCSRBAR + LAWBAR_BASE(2)@h
|
||||
#ifdef INITIAL_SRAM_ADDR
|
||||
init_sram_law:
|
||||
/* Intial SRAM LAW 2 */
|
||||
#define INITIAL_SRAM_LAW (LAWAR_ENABLE | \
|
||||
LAWAR_TRGT_ID(INITIAL_SRAM_LAW_TRGT) | \
|
||||
INITIAL_SRAM_LAW_SZ)
|
||||
lis r9, CCSRBAR + LAWBAR_BASE(2)@h
|
||||
ori r9, r9, CCSRBAR + LAWBAR_BASE(2)@l
|
||||
li r0, 0
|
||||
lis r1, L2SRAM_ADDR@h
|
||||
ori r1, r1, L2SRAM_ADDR@l
|
||||
lis r2, L2SRAM_LAW@h
|
||||
ori r2, r2, L2SRAM_LAW@l
|
||||
li r0, 0 /* UPPER=0 */
|
||||
lis r1, INITIAL_SRAM_ADDR@h
|
||||
ori r1, r1, INITIAL_SRAM_ADDR@l
|
||||
lis r2, INITIAL_SRAM_LAW@h
|
||||
ori r2, r2, INITIAL_SRAM_LAW@l
|
||||
stw r0, 0(r9) /* LAWBARH */
|
||||
stw r1, 4(r9) /* LAWBARL */
|
||||
sync
|
||||
|
|
@ -515,36 +520,23 @@ l2_sram_law:
|
|||
lwz r2, 8(r9) /* read back LAWAR (per 2.3.2 Configuring Local Access Windows) */
|
||||
isync
|
||||
|
||||
l2_sram_tlb:
|
||||
/* L2 0xFEC20000: TLB 1, Entry 9, Supervisor X/R/W, M, TS=0, 256KB, IPROT */
|
||||
init_sram_tlb:
|
||||
/* Inital SRAM: TLB 1, Entry 9, Supervisor X/R/W, M, TS=0, IPROT */
|
||||
set_tlb(1, 9,
|
||||
L2SRAM_ADDR, L2SRAM_ADDR, 0,
|
||||
INITIAL_SRAM_ADDR, INITIAL_SRAM_ADDR, 0,
|
||||
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_M, 0,
|
||||
BOOKE_PAGESZ_256K, 1, r3);
|
||||
INITIAL_SRAM_BOOKE_SZ, 1, r3);
|
||||
#endif
|
||||
|
||||
#ifdef ENABLE_L2_CACHE
|
||||
|
||||
#if defined(CORE_E5500) || defined(CORE_E6500) /* --- L2 E5500/E6500 --- */
|
||||
#ifdef L2SRAM_ADDR
|
||||
l2_setup_sram:
|
||||
/* 8.2 CoreNet Platform Cache (CPC) Memory Map */
|
||||
#define CPCCSR0 (0x000)
|
||||
#define CPCSRCR1 (0x100)
|
||||
#define CPCSRCR0 (0x104)
|
||||
#define CPCHDBCR0 (0xF00)
|
||||
|
||||
#define CPCCSR0_CPCE (0x80000000 >> 0)
|
||||
#define CPCCSR0_CPCPE (0x80000000 >> 1)
|
||||
#define CPCCSR0_CPCFI (0x80000000 >> 10)
|
||||
#define CPCCSR0_CPCLFC (0x80000000 >> 21)
|
||||
#define CPCCSR0_SRAM_ENABLE (CPCCSR0_CPCE | CPCCSR0_CPCPE)
|
||||
|
||||
#define CPCSRCR0_SRAMSZ_64 (0x1 << 1) /* ways 14-15 */
|
||||
#define CPCSRCR0_SRAMSZ_256 (0x3 << 1) /* ways 8-15 */
|
||||
#define CPCSRCR0_SRAMSZ_512 (0x4 << 1) /* ways 0-15 */
|
||||
#define CPCSRCR0_SRAMEN (0x1)
|
||||
|
||||
#define CPCHDBCR0_SPEC_DIS (0x80000000 >> 4)
|
||||
|
||||
/* T2080RM: 8.4.2.2 Enabling the CPC after Power-On Reset */
|
||||
/* T2080RM: 8.4.2.2 or T1024RM 13.4.2.2
|
||||
* Enabling the CPC after Power-On Reset */
|
||||
/* R1 = CPC base */
|
||||
lis r1, CPC_BASE@h
|
||||
lis r1, CPC_BASE@h
|
||||
ori r1, r1, CPC_BASE@l
|
||||
|
||||
/* Set CPC SRAM control register */
|
||||
|
|
@ -552,7 +544,7 @@ l2_setup_sram:
|
|||
li r0, 0
|
||||
stw r0, CPCSRCR1(r1)
|
||||
/* SRAM low address */
|
||||
lis r0, L2SRAM_ADDR@h
|
||||
lis r0, L2SRAM_ADDR@h
|
||||
ori r0, r0, L2SRAM_ADDR@l
|
||||
/* Enable SRAM and set size (must match L2SRAM_SIZE) */
|
||||
ori r0, r0, (CPCSRCR0_SRAMSZ_256 | CPCSRCR0_SRAMEN)
|
||||
|
|
@ -564,35 +556,27 @@ l2_setup_sram:
|
|||
isync
|
||||
stw r0, CPCCSR0(r1)
|
||||
mbar
|
||||
#endif /* L2SRAM_ADDR */
|
||||
|
||||
/* Disable speculation */
|
||||
lwz r0, CPCHDBCR0(r1)
|
||||
oris r0, r0, CPCHDBCR0_SPEC_DIS@h
|
||||
stw r0, CPCHDBCR0(r1)
|
||||
#endif /* L2SRAM_ADDR */
|
||||
|
||||
#if defined(CORE_E6500) /* --- L2 E6500 --- */
|
||||
l2_setup_cache:
|
||||
/* L2 Cache Control - E6500CORERM 2.2.3 Memory-mapped registers (MMRs) */
|
||||
#define L2_CLUSTER_BASE(n) (CCSRBAR + 0xC20000 + (n * 0x40000))
|
||||
#define L2CSR0 (0x000) /* L2 Cache Control and Status 0 */
|
||||
#define L2CSR1 (0x004) /* L2 Cache Control and Status 1 */
|
||||
#define L2CFG0 (0x008) /* L2 Cache Configuration */
|
||||
#define L2PID(n) (0x200 + (n * 0x10)) /* L2 Cache Partitioning ID */
|
||||
#define L2PIR(n) (0x208 + (n * 0x10)) /* L2 Cache Partitioning Allocation */
|
||||
#define L2PWR(n) (0x20C + (n * 0x10)) /* L2 Cache Partitioning Way */
|
||||
|
||||
#define L2CSR0_L2FI 0x00200000 /* L2 Cache Flash Invalidate */
|
||||
#define L2CSR0_L2FL 0x00000800 /* L2 Cache Flush */
|
||||
#define L2CSR0_L2LFC 0x00000400 /* L2 Cache Lock Flash Clear */
|
||||
#define L2CSR0_L2PE 0x40000000 /* L2 Cache Parity/ECC Enable */
|
||||
#define L2CSR0_L2E 0x80000000 /* L2 Cache Enable */
|
||||
|
||||
/* E6500CORERM: 11.7 L2 cache state */
|
||||
/* R5 = L2 cluster 1 base */
|
||||
lis r5, L2_CLUSTER_BASE(0)@h
|
||||
lis r5, L2_CLUSTER_BASE(0)@h
|
||||
ori r5, r5, L2_CLUSTER_BASE(0)@l
|
||||
/* Invalidate and clear locks */
|
||||
lis r1, (L2CSR0_L2FI | L2CSR0_L2LFC)@h
|
||||
lis r1, (L2CSR0_L2FI | L2CSR0_L2LFC)@h
|
||||
ori r1, r1, (L2CSR0_L2FI | L2CSR0_L2LFC)@l
|
||||
sync
|
||||
stw r1, L2CSR0(r5)
|
||||
|
|
@ -604,6 +588,10 @@ l2_poll_invclear:
|
|||
bne l2_poll_invclear
|
||||
isync
|
||||
|
||||
/* set stash id to (coreID) * 2 + 32 + L2 (1) */
|
||||
li r4, (32 + 1)
|
||||
stw r4, L2CSR1(r5)
|
||||
|
||||
/* enable L2 with parity */
|
||||
sync
|
||||
isync
|
||||
|
|
@ -611,37 +599,43 @@ l2_poll_invclear:
|
|||
stw r4, L2CSR0(r5)
|
||||
isync
|
||||
|
||||
/* set stash id = 32 */
|
||||
li r4, 32
|
||||
stw r4, L2CSR1(r5)
|
||||
#elif defined(CORE_E5500) /* --- L2 E5500 --- */
|
||||
l2_setup_cache:
|
||||
/* L2 Cache Control - E5500RM 2.15 L2 Cache Registers */
|
||||
#define L2_BASE (CCSRBAR + 0x20000)
|
||||
|
||||
#elif defined(CORE_E500) /* --- L2 E500 --- */
|
||||
|
||||
#ifdef L2SRAM_ADDR
|
||||
l2_sram_law:
|
||||
/* L2 SRAM - LAW2 (eLBC 256KB) */
|
||||
#define L2SRAM_LAW \
|
||||
(LAWAR_ENABLE | LAWAR_TRGT_ID(LAW_TRGT_ELBC) | LAW_SIZE_256KB)
|
||||
lis r9, CCSRBAR + LAWBAR_BASE(2)@h
|
||||
ori r9, r9, CCSRBAR + LAWBAR_BASE(2)@l
|
||||
lis r1, L2SRAM_ADDR@h
|
||||
ori r1, r1, L2SRAM_ADDR@l
|
||||
lis r2, L2SRAM_LAW@h
|
||||
ori r2, r2, L2SRAM_LAW@l
|
||||
stw r1, 0(r9) /* LAWBAR */
|
||||
/* Invalidate and clear locks */
|
||||
lis r1, (L2CSR0_L2FI | L2CSR0_L2LFC)@h
|
||||
ori r1, r1, (L2CSR0_L2FI | L2CSR0_L2LFC)@l
|
||||
sync
|
||||
stw r2, 8(r9) /* LAWAR */
|
||||
lwz r2, 8(r9) /* read back LAWAR */
|
||||
isync
|
||||
mtspr L2CSR0, r1
|
||||
isync
|
||||
|
||||
l2_sram_tlb:
|
||||
/* L2 0xF8F80000: TLB 1, Entry 9, Supervisor X/R/W, G, TS=0, 256KB, IPROT */
|
||||
set_tlb(1, 9,
|
||||
L2SRAM_ADDR, L2SRAM_ADDR, 0,
|
||||
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_G, 0,
|
||||
BOOKE_PAGESZ_256K, 1, r3);
|
||||
#endif
|
||||
/* poll till invalidate and lock bits are cleared */
|
||||
l2_poll_invclear:
|
||||
mfspr r4, L2CSR0
|
||||
and. r4, r1, r4
|
||||
bne l2_poll_invclear
|
||||
|
||||
/* set stash id to (coreID) * 2 + 32 + L2 (1) */
|
||||
li r4, (32 + 1)
|
||||
sync
|
||||
isync
|
||||
mtspr L2CSR1, r4
|
||||
isync
|
||||
sync
|
||||
|
||||
/* enable L2 with no parity */
|
||||
lis r4, (L2CSR0_L2E)@h
|
||||
sync
|
||||
isync
|
||||
mtspr L2CSR0, r4
|
||||
isync
|
||||
#endif
|
||||
#endif /* CORE_E5500 || CORE_E6500 */
|
||||
|
||||
#if defined(CORE_E500) /* --- L2 E500 --- */
|
||||
/* e500 - L2 Cache */
|
||||
l2_setup_cache:
|
||||
#define L2_BASE (CCSRBAR + 0x20000)
|
||||
|
|
@ -659,9 +653,9 @@ l2_setup_cache:
|
|||
#define L2CTL_VAL (L2CTL_EN | L2CTL_INV | L2CTL_SIZ(2))
|
||||
#endif
|
||||
/* Configure the L2 Cache */
|
||||
lis r5, L2_BASE@h
|
||||
lis r5, L2_BASE@h
|
||||
ori r5, r5, L2_BASE@l
|
||||
lis r1, L2CTL_VAL@h
|
||||
lis r1, L2CTL_VAL@h
|
||||
ori r1, r1, L2CTL_VAL@l
|
||||
msync
|
||||
isync
|
||||
|
|
@ -675,18 +669,22 @@ l2_setup_sram:
|
|||
/* Set the L2SRAM base address */
|
||||
mbar
|
||||
isync
|
||||
lis r1, L2SRAM_ADDR@h
|
||||
lis r1, L2SRAM_ADDR@h
|
||||
ori r1, r1, L2SRAM_ADDR@l
|
||||
stw r1, L2SRBAR0(r5)
|
||||
mbar
|
||||
#endif /* L2SRAM_ADDR */
|
||||
|
||||
#endif /* CORE_* */
|
||||
#endif /* CORE_E500 */
|
||||
#endif /* ENABLE_L2_CACHE */
|
||||
|
||||
|
||||
#ifdef ENABLE_L1_CACHE
|
||||
setup_l1:
|
||||
#if defined(CORE_E5500) || defined(CORE_E6500)
|
||||
/* set L1 stash id = 32: (coreID * 2) + 32 + L1 CT (0) */
|
||||
li r2, 32
|
||||
mtspr L1CSR2, r2
|
||||
#endif
|
||||
#ifndef BUILD_LOADER_STAGE1
|
||||
/* L1 Instruction Cache */
|
||||
bl icache_enable;
|
||||
|
|
@ -716,7 +714,7 @@ l1_tlb:
|
|||
|
||||
#ifdef CACHE_SRAM_ADDR
|
||||
cache_sram_init:
|
||||
lis r3, CACHE_SRAM_ADDR@h
|
||||
lis r3, CACHE_SRAM_ADDR@h
|
||||
ori r3, r3, CACHE_SRAM_ADDR@l
|
||||
/* read the cache size */
|
||||
mfspr r2, L1CFG0
|
||||
|
|
@ -729,7 +727,7 @@ cache_sram_init_loop:
|
|||
/* Data cache block zero */
|
||||
dcbz r0, r3
|
||||
/* Data cache block touch and lock set */
|
||||
#ifdef CORE_E6500
|
||||
#if defined(CORE_E6500)
|
||||
dcbtls 2, r0, r3
|
||||
dcbtls 0, r0, r3
|
||||
#else
|
||||
|
|
@ -752,13 +750,13 @@ setup_stack:
|
|||
stwu r0, -4(r1)
|
||||
stwu r0, -4(r1) /* Terminate Back chain */
|
||||
stwu r1, -8(r1) /* Save back chain and move SP */
|
||||
lis r0, RESET_VECTOR@h /* Address of reset vector */
|
||||
lis r0, RESET_VECTOR@h /* Address of reset vector */
|
||||
ori r0, r0, RESET_VECTOR@l
|
||||
stwu r1, -8(r1) /* Save back chain and move SP */
|
||||
stw r0, +12(r1) /* Save return addr (underflow vect) */
|
||||
|
||||
/* switch back to AS/TS=0 */
|
||||
lis r3, (MSR_CE | MSR_ME | MSR_DE)@h
|
||||
lis r3, (MSR_CE | MSR_ME | MSR_DE)@h
|
||||
ori r3, r3, (MSR_CE | MSR_ME | MSR_DE)@l
|
||||
mtmsr r3
|
||||
isync
|
||||
|
|
@ -770,7 +768,7 @@ setup_stack:
|
|||
#ifdef USE_LONG_JUMP
|
||||
/* load absolute address into "LR" and branch return to it */
|
||||
/* Enables long jump in 32-bit */
|
||||
lis r3, boot_entry_C@h
|
||||
lis r3, boot_entry_C@h
|
||||
ori r3, r3, boot_entry_C@l
|
||||
mtlr r3
|
||||
blr
|
||||
|
|
|
|||
|
|
@ -34,8 +34,11 @@
|
|||
|
||||
/* support for elf parsing debug printf */
|
||||
#if defined(DEBUG) || defined(ELF_PARSER)
|
||||
#if DEBUG_ELF == 0
|
||||
#if defined(DEBUG_ELF) && DEBUG_ELF == 0
|
||||
#undef DEBUG_ELF
|
||||
#else
|
||||
#undef DEBUG_ELF
|
||||
#define DEBUG_ELF
|
||||
#endif
|
||||
#endif
|
||||
|
||||
|
|
|
|||
16
src/image.c
16
src/image.c
|
|
@ -838,10 +838,9 @@ static uint32_t wb_reverse_word32(uint32_t x)
|
|||
*/
|
||||
int wolfBoot_get_dts_size(void *dts_addr)
|
||||
{
|
||||
uint32_t hdr[2];
|
||||
uint32_t magic;
|
||||
uint32_t size;
|
||||
memcpy(hdr, dts_addr, 2 * sizeof(uint32_t));
|
||||
uint32_t hdr[2], magic, size;
|
||||
|
||||
memcpy(hdr, dts_addr, sizeof(hdr));
|
||||
|
||||
#ifdef BIG_ENDIAN_ORDER
|
||||
magic = wb_reverse_word32(hdr[0]);
|
||||
|
|
@ -850,10 +849,7 @@ int wolfBoot_get_dts_size(void *dts_addr)
|
|||
magic = hdr[0];
|
||||
size = wb_reverse_word32(hdr[1]);
|
||||
#endif
|
||||
if (magic != UBOOT_FDT_MAGIC)
|
||||
return -1;
|
||||
else
|
||||
return (int)size;
|
||||
return (magic == UBOOT_FDT_MAGIC) ? (int)size : -1;
|
||||
}
|
||||
#endif
|
||||
|
||||
|
|
@ -893,7 +889,9 @@ int wolfBoot_open_image(struct wolfBoot_image *img, uint8_t part)
|
|||
}
|
||||
#ifdef MMU
|
||||
if (part == PART_DTS_BOOT || part == PART_DTS_UPDATE) {
|
||||
img->hdr = (void *)WOLFBOOT_LOAD_DTS_ADDRESS;
|
||||
img->hdr = (part == PART_DTS_BOOT) ?
|
||||
(void*)WOLFBOOT_DTS_BOOT_ADDRESS :
|
||||
(void*)WOLFBOOT_DTS_UPDATE_ADDRESS;
|
||||
wolfBoot_printf("%s partition: %p\n",
|
||||
(part == PART_DTS_BOOT) ? "DTB boot" : "DTB update", img->hdr);
|
||||
if (PART_IS_EXT(img))
|
||||
|
|
|
|||
|
|
@ -47,7 +47,7 @@ extern uint32_t dts_load_addr;
|
|||
#define WOLFBOOT_USE_RAMBOOT
|
||||
#endif
|
||||
|
||||
#if defined(EXT_FLASH) && defined(NO_XIP)
|
||||
#ifdef WOLFBOOT_USE_RAMBOOT
|
||||
/* Function to load image from flash to ram */
|
||||
int wolfBoot_ramboot(struct wolfBoot_image *img, uint8_t *src, uint8_t *dst)
|
||||
{
|
||||
|
|
@ -57,11 +57,15 @@ int wolfBoot_ramboot(struct wolfBoot_image *img, uint8_t *src, uint8_t *dst)
|
|||
/* read header into RAM */
|
||||
wolfBoot_printf("Loading header %d bytes to %p\n",
|
||||
IMAGE_HEADER_SIZE, dst);
|
||||
#if defined(EXT_FLASH) && defined(NO_XIP)
|
||||
ret = ext_flash_read((uintptr_t)src, dst, IMAGE_HEADER_SIZE);
|
||||
if (ret != IMAGE_HEADER_SIZE){
|
||||
wolfBoot_printf("Error reading header at %p\n", img);
|
||||
return -1;
|
||||
}
|
||||
#else
|
||||
memcpy(dst, src, IMAGE_HEADER_SIZE);
|
||||
#endif
|
||||
|
||||
/* check for valid header and version */
|
||||
ret = wolfBoot_get_blob_version((uint8_t*)dst);
|
||||
|
|
@ -76,12 +80,16 @@ int wolfBoot_ramboot(struct wolfBoot_image *img, uint8_t *src, uint8_t *dst)
|
|||
/* Read the entire image into RAM */
|
||||
wolfBoot_printf("Loading image %d bytes to %p\n",
|
||||
img_size, dst + IMAGE_HEADER_SIZE);
|
||||
#if defined(EXT_FLASH) && defined(NO_XIP)
|
||||
ret = ext_flash_read((uintptr_t)src + IMAGE_HEADER_SIZE,
|
||||
dst + IMAGE_HEADER_SIZE, img_size);
|
||||
if (ret < 0) {
|
||||
wolfBoot_printf("Error reading image at %p\n", src);
|
||||
return -1;
|
||||
}
|
||||
#else
|
||||
memcpy(dst + IMAGE_HEADER_SIZE, src + IMAGE_HEADER_SIZE, img_size);
|
||||
#endif
|
||||
|
||||
/* mark image as no longer external */
|
||||
img->not_ext = 1;
|
||||
|
|
@ -133,13 +141,13 @@ void RAMFUNCTION wolfBoot_start(void)
|
|||
#ifdef WOLFBOOT_USE_RAMBOOT
|
||||
load_address = (uint32_t*)(WOLFBOOT_LOAD_ADDRESS -
|
||||
IMAGE_HEADER_SIZE);
|
||||
#if defined(EXT_FLASH) && defined(NO_XIP)
|
||||
ret = wolfBoot_ramboot(&os_image, (uint8_t*)source_address,
|
||||
(uint8_t*)load_address);
|
||||
#elif defined(EXT_ENCRYPTED) && defined(MMU)
|
||||
#if defined(EXT_ENCRYPTED) && defined(MMU)
|
||||
ret = wolfBoot_ram_decrypt((uint8_t*)source_address,
|
||||
(uint8_t*)load_address);
|
||||
#endif
|
||||
#else
|
||||
ret = wolfBoot_ramboot(&os_image, (uint8_t*)source_address,
|
||||
(uint8_t*)load_address);
|
||||
#endif
|
||||
if (ret != 0) {
|
||||
goto backup_on_failure;
|
||||
}
|
||||
|
|
@ -159,9 +167,15 @@ void RAMFUNCTION wolfBoot_start(void)
|
|||
goto backup_on_failure;
|
||||
|
||||
} else {
|
||||
/* Success */
|
||||
/* Success - integrity and signature valid */
|
||||
#ifdef WOLFBOOT_LOAD_ADDRESS
|
||||
load_address = (uint32_t*)WOLFBOOT_LOAD_ADDRESS;
|
||||
break;
|
||||
#elif !defined(NO_XIP)
|
||||
load_address = (uint32_t*)os_image.fw_base;
|
||||
#else
|
||||
#error missing WOLFBOOT_LOAD_ADDRESS or XIP
|
||||
#endif
|
||||
break;
|
||||
}
|
||||
|
||||
backup_on_failure:
|
||||
|
|
@ -179,7 +193,7 @@ backup_on_failure:
|
|||
|
||||
wolfBoot_printf("Firmware Valid\n");
|
||||
|
||||
/* First time we boot this update, set to TESTING to await
|
||||
/* First time we boot this update, set to TESTING to await
|
||||
* confirmation from the system
|
||||
*/
|
||||
#ifdef WOLFBOOT_FIXED_PARTITIONS
|
||||
|
|
@ -214,13 +228,6 @@ backup_on_failure:
|
|||
#pragma GCC diagnostic ignored "-Wnonnull"
|
||||
#endif
|
||||
|
||||
#ifdef WOLFBOOT_ELF
|
||||
/* Load elf */
|
||||
if (elf_load_image((uint8_t*)load_address, (uintptr_t*)&load_address) != 0){
|
||||
wolfBoot_printf("Invalid elf, falling back to raw binary\n");
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifndef WOLFBOOT_USE_RAMBOOT
|
||||
/* if needed copy image to RAM */
|
||||
wolfBoot_printf("Loading %d bytes to RAM at %p\n", os_image.fw_size,
|
||||
|
|
@ -228,6 +235,13 @@ backup_on_failure:
|
|||
memcpy((void*)load_address, os_image.fw_base, os_image.fw_size);
|
||||
#endif
|
||||
|
||||
#ifdef WOLFBOOT_ELF
|
||||
/* Load elf */
|
||||
if (elf_load_image((uint8_t*)load_address, (uintptr_t*)&load_address) != 0){
|
||||
wolfBoot_printf("Invalid elf, falling back to raw binary\n");
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef MMU
|
||||
/* Load DTS to RAM */
|
||||
#ifdef EXT_FLASH
|
||||
|
|
@ -252,11 +266,13 @@ backup_on_failure:
|
|||
/* Allow failure, continue booting */
|
||||
}
|
||||
else {
|
||||
/* relocate DTS to RAM */
|
||||
uint8_t* dts_dst = (uint8_t*)WOLFBOOT_LOAD_DTS_ADDRESS;
|
||||
dts_size = (uint32_t)ret;
|
||||
wolfBoot_printf("Loading DTB (size %d) to RAM at %08lx\n",
|
||||
dts_size, dts_addr);
|
||||
memcpy((void*)WOLFBOOT_LOAD_DTS_ADDRESS, dts_addr, dts_size);
|
||||
dts_addr = (uint8_t*)WOLFBOOT_LOAD_DTS_ADDRESS;
|
||||
wolfBoot_printf("Loading DTB (size %d) from %p to RAM at %p\n",
|
||||
dts_size, dts_addr, WOLFBOOT_LOAD_DTS_ADDRESS);
|
||||
memcpy(dts_dst, dts_addr, dts_size);
|
||||
dts_addr = dts_dst;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -100,8 +100,10 @@ CFLAGS+=\
|
|||
# For printf support (disable NO_PRINTF_UART) and increase WOLFBOOT_STAGE1_SIZE
|
||||
ifeq ($(ARCH),PPC)
|
||||
CFLAGS+=-DNO_PRINTF_UART
|
||||
# Use PIC (Position Independent Code) for first stage loader
|
||||
CFLAGS+=-fPIC
|
||||
ifeq ($(NO_XIP),1)
|
||||
# Use PIC (Position Independent Code) for first stage loader
|
||||
CFLAGS+=-fPIC
|
||||
endif
|
||||
endif
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -32,8 +32,9 @@
|
|||
#include <string.h>
|
||||
#include <stdint.h>
|
||||
|
||||
#ifndef EXT_FLASH
|
||||
#error The stage1 loader only supports use with external flash
|
||||
|
||||
#if !defined(EXT_FLASH) && defined(NO_XIP)
|
||||
#error Using first stage loader requires XIP or External Flash (EXT_FLASH)
|
||||
#endif
|
||||
|
||||
#ifndef WOLFBOOT_STAGE1_SIZE
|
||||
|
|
@ -73,7 +74,7 @@ int main(void)
|
|||
hal_init();
|
||||
spi_flash_probe(); /* make sure external flash is initialized */
|
||||
|
||||
#ifdef BOOT_ROM_ADDR
|
||||
#if defined(NO_XIP) && defined(BOOT_ROM_ADDR)
|
||||
/* if this is executing from boot 4KB region (FCM buffer) it must
|
||||
* first be relocated to RAM before the eLBC NAND can be read */
|
||||
if ((get_pc() & BOOT_ROM_ADDR) == BOOT_ROM_ADDR) {
|
||||
|
|
@ -104,11 +105,21 @@ int main(void)
|
|||
uart_write("Loading wolfBoot to DDR\n", 24);
|
||||
#endif
|
||||
|
||||
#ifdef EXT_FLASH
|
||||
ret = ext_flash_read(
|
||||
(uintptr_t)WOLFBOOT_ORIGIN, /* flash offset */
|
||||
(uint8_t*)WOLFBOOT_STAGE1_LOAD_ADDR,/* ram destination */
|
||||
BOOTLOADER_PARTITION_SIZE /* boot-loader partition (entire) */
|
||||
);
|
||||
#else
|
||||
/* copy from flash to ram */
|
||||
memcpy32(
|
||||
(uint8_t*)WOLFBOOT_STAGE1_LOAD_ADDR,/* ram destination */
|
||||
(uint8_t*)WOLFBOOT_ORIGIN, /* flash offset */
|
||||
BOOTLOADER_PARTITION_SIZE /* boot-loader partition (entire) */
|
||||
);
|
||||
ret = 0;
|
||||
#endif
|
||||
if (ret >= 0) {
|
||||
wolfboot_start = (uint32_t*)WOLFBOOT_STAGE1_LOAD_ADDR;
|
||||
#ifdef PRINTF_ENABLED
|
||||
|
|
|
|||
|
|
@ -0,0 +1,51 @@
|
|||
/* app_nxp_t1024.c
|
||||
*
|
||||
* Copyright (C) 2023 wolfSSL Inc.
|
||||
*
|
||||
* This file is part of wolfBoot.
|
||||
*
|
||||
* wolfBoot is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* wolfBoot is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include "../hal/nxp_ppc.h"
|
||||
#include "printf.h"
|
||||
|
||||
static const char* hex_lut = "0123456789abcdef";
|
||||
|
||||
void main(void)
|
||||
{
|
||||
int i = 0;
|
||||
int j = 0;
|
||||
int k = 0;
|
||||
char snum[8];
|
||||
|
||||
uart_init();
|
||||
|
||||
uart_write("Test App\n", 9);
|
||||
|
||||
/* Wait for reboot */
|
||||
while(1) {
|
||||
for (j=0; j<1000000; j++)
|
||||
;
|
||||
i++;
|
||||
|
||||
uart_write("\r\n0x", 4);
|
||||
for (k=0; k<8; k++) {
|
||||
snum[7 - k] = hex_lut[(i >> 4*k) & 0xf];
|
||||
}
|
||||
uart_write(snum, 8);
|
||||
}
|
||||
}
|
||||
Loading…
Reference in New Issue