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wolfBoot
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Fix GPIO mode for SPI CS pins

pull/264/head
Daniele Lacamera 2022-12-20 13:54:17 +01:00
parent 1766864a6b
commit bf62ebe3fd
3 changed files with 46 additions and 41 deletions
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2
Makefile
View File

@ -205,7 +205,7 @@ src/keystore.c: $(PRIVATE_KEY)
keys: $(PRIVATE_KEY)
clean:
@rm -f src/*.o hal/*.o lib/wolfssl/wolfcrypt/src/*.o test-app/*.o
@rm -f src/*.o hal/*.o hal/spi/*.o lib/wolfssl/wolfcrypt/src/*.o test-app/*.o
@rm -f *.bin *.elf wolfboot.map test-update.rom *.hex config/target.ld
@$(MAKE) -C test-app clean
@$(MAKE) -C tools/check_config clean

76
hal/spi/spi_drv_stm32.c
View File

@ -31,8 +31,8 @@
#if defined(SPI_FLASH) || defined(QSPI_FLASH)
void RAMFUNCTION stm_gpio_config(uint32_t base, uint32_t pin, uint32_t af,
uint32_t pull, uint32_t speed)
void RAMFUNCTION stm_gpio_config(uint32_t base, uint32_t pin, uint32_t mode,
uint32_t af, uint32_t pull, uint32_t speed)
{
uint32_t reg;
uint32_t base_num = 0;
@ -80,22 +80,18 @@ void RAMFUNCTION stm_gpio_config(uint32_t base, uint32_t pin, uint32_t af,
#endif
/* Enable GPIO clock */
RCC_GPIO_CLOCK_ER |= (1 << base);
RCC_GPIO_CLOCK_ER |= (1 << base_num);
/* Set Mode and Alternate Function */
if (af == 0) {
/* mode = 0, af = 0 */
GPIO_MODE(base) &= ~(0x03 << (pin * 2));
reg = GPIO_MODE(base) & ~(0x03 << (pin * 2));
GPIO_MODE(base) = reg | (mode << (pin * 2));
if (mode < 2) {
if (pin < 8)
GPIO_AFL(base) &= ~(0xf << (pin * 4));
else
GPIO_AFH(base) &= ~(0xf << ((pin - 8) * 4));
}
else {
/* mode = 2 (af) */
reg = GPIO_MODE(base) & ~(0x03 << (pin * 2));
GPIO_MODE(base) = reg | (2 << (pin * 2));
else if (mode == 2) {
/* alternate mode */
if (pin < 8) {
reg = GPIO_AFL(base) & ~(0xf << (pin * 4));
@ -136,34 +132,52 @@ void RAMFUNCTION spi_cs_on(uint32_t base, int pin)
static void RAMFUNCTION stm_pins_setup(void)
{
#ifdef SPI_FLASH
stm_gpio_config(SPI_CLOCK_PIO_BASE, SPI_CLOCK_PIN, SPI_CLOCK_PIN_AF, 0, 3);
stm_gpio_config(SPI_MOSI_PIO_BASE, SPI_MOSI_PIN, SPI_MOSI_PIN_AF, 0, 3);
stm_gpio_config(SPI_MISO_PIO_BASE, SPI_MISO_PIN, SPI_MISO_PIN_AF, 0, 3);
#ifdef PLATFORM_stm32l0
stm_gpio_config(SPI_CLOCK_PIO_BASE, SPI_CLOCK_PIN, GPIO_MODE_AF,
SPI_CLOCK_PIN_AF, 2, 3);
stm_gpio_config(SPI_MOSI_PIO_BASE, SPI_MOSI_PIN, GPIO_MODE_AF,
SPI_MOSI_PIN_AF, 2, 3);
stm_gpio_config(SPI_MISO_PIO_BASE, SPI_MISO_PIN, GPIO_MODE_AF,
SPI_MISO_PIN_AF, 2, 3);
#else
stm_gpio_config(SPI_CLOCK_PIO_BASE, SPI_CLOCK_PIN, GPIO_MODE_AF,
SPI_CLOCK_PIN_AF, 0, 3);
stm_gpio_config(SPI_MOSI_PIO_BASE, SPI_MOSI_PIN, GPIO_MODE_AF,
SPI_MOSI_PIN_AF, 0, 0);
stm_gpio_config(SPI_MISO_PIO_BASE, SPI_MISO_PIN, GPIO_MODE_AF,
SPI_MISO_PIN_AF, 1, 0);
#endif
#endif
#ifdef QSPI_FLASH
stm_gpio_config(QSPI_CS_PIO_BASE, QSPI_CS_FLASH_PIN, QSPI_CS_FLASH_AF, 1, 3);
stm_gpio_config(QSPI_CLOCK_PIO_BASE, QSPI_CLOCK_PIN, QSPI_CLOCK_PIN_AF, 0, 3);
stm_gpio_config(QSPI_IO0_PIO_BASE, QSPI_IO0_PIN, QSPI_IO0_PIN_AF, 0, 3);
stm_gpio_config(QSPI_IO1_PIO_BASE, QSPI_IO1_PIN, QSPI_IO1_PIN_AF, 0, 3);
stm_gpio_config(QSPI_IO2_PIO_BASE, QSPI_IO2_PIN, QSPI_IO2_PIN_AF, 0, 3);
stm_gpio_config(QSPI_IO3_PIO_BASE, QSPI_IO3_PIN, QSPI_IO3_PIN_AF, 0, 3);
stm_gpio_config(QSPI_CS_PIO_BASE, QSPI_CS_FLASH_PIN, GPIO_MODE_OUTPUT,
0, 1, 3);
stm_gpio_config(QSPI_CLOCK_PIO_BASE, QSPI_CLOCK_PIN, GPIO_MODE_AF,
QSPI_CLOCK_PIN_AF, 0, 3);
stm_gpio_config(QSPI_IO0_PIO_BASE, QSPI_IO0_PIN, GPIO_MODE_AF,
QSPI_IO0_PIN_AF, 0, 3);
stm_gpio_config(QSPI_IO1_PIO_BASE, QSPI_IO1_PIN, GPIO_MODE_AF,
QSPI_IO1_PIN_AF, 0, 3);
stm_gpio_config(QSPI_IO2_PIO_BASE, QSPI_IO2_PIN, GPIO_MODE_AF,
QSPI_IO2_PIN_AF, 0, 3);
stm_gpio_config(QSPI_IO3_PIO_BASE, QSPI_IO3_PIN, GPIO_MODE_AF,
QSPI_IO3_PIN_AF, 0, 3);
#endif
}
static void stm_pins_release(void)
{
#ifdef SPI_FLASH
stm_gpio_config(SPI_CLOCK_PIO_BASE, SPI_CLOCK_PIN, 0, 0, 0);
stm_gpio_config(SPI_MOSI_PIO_BASE, SPI_MOSI_PIN, 0, 0, 0);
stm_gpio_config(SPI_MISO_PIO_BASE, SPI_MISO_PIN, 0, 0, 0);
stm_gpio_config(SPI_CLOCK_PIO_BASE, SPI_CLOCK_PIN, GPIO_MODE_INPUT, 0, 0, 0);
stm_gpio_config(SPI_MOSI_PIO_BASE, SPI_MOSI_PIN, GPIO_MODE_INPUT, 0, 0, 0);
stm_gpio_config(SPI_MISO_PIO_BASE, SPI_MISO_PIN, GPIO_MODE_INPUT, 0, 0, 0);
#endif
#ifdef QSPI_FLASH
stm_gpio_config(QSPI_CS_PIO_BASE, QSPI_CS_FLASH_PIN, 0, 0, 0);
stm_gpio_config(QSPI_CLOCK_PIO_BASE, QSPI_CLOCK_PIN, 0, 0, 0);
stm_gpio_config(QSPI_IO0_PIO_BASE, QSPI_IO0_PIN, 0, 0, 0);
stm_gpio_config(QSPI_IO1_PIO_BASE, QSPI_IO1_PIN, 0, 0, 0);
stm_gpio_config(QSPI_IO2_PIO_BASE, QSPI_IO2_PIN, 0, 0, 0);
stm_gpio_config(QSPI_IO3_PIO_BASE, QSPI_IO3_PIN, 0, 0, 0);
stm_gpio_config(QSPI_CS_PIO_BASE, QSPI_CS_FLASH_PIN, GPIO_MODE_INPUT, 0, 0, 0);
stm_gpio_config(QSPI_CLOCK_PIO_BASE, QSPI_CLOCK_PIN, GPIO_MODE_INPUT, 0, 0, 0);
stm_gpio_config(QSPI_IO0_PIO_BASE, QSPI_IO0_PIN, GPIO_MODE_INPUT, 0, 0, 0);
stm_gpio_config(QSPI_IO1_PIO_BASE, QSPI_IO1_PIN, GPIO_MODE_INPUT, 0, 0, 0);
stm_gpio_config(QSPI_IO2_PIO_BASE, QSPI_IO2_PIN, GPIO_MODE_INPUT, 0, 0, 0);
stm_gpio_config(QSPI_IO3_PIO_BASE, QSPI_IO3_PIN, GPIO_MODE_INPUT, 0, 0, 0);
#endif
}
@ -306,11 +320,11 @@ void RAMFUNCTION spi_init(int polarity, int phase)
/* Configure chip selects */
#ifdef SPI_FLASH
stm_gpio_config(SPI_CS_PIO_BASE, SPI_CS_FLASH, SPI_CS_FLASH_AF, 1, 3);
stm_gpio_config(SPI_CS_PIO_BASE, SPI_CS_FLASH, GPIO_MODE_OUTPUT, 0, 1, 3);
spi_cs_off(SPI_CS_PIO_BASE, SPI_CS_FLASH);
#endif
#ifdef WOLFBOOT_TPM
stm_gpio_config(SPI_CS_TPM_PIO_BASE, SPI_CS_TPM, SPI_CS_TPM_AF, 1, 3);
stm_gpio_config(SPI_CS_TPM_PIO_BASE, SPI_CS_TPM, GPIO_MODE_OUTPUT, 0, 1, 3);
spi_cs_off(SPI_CS_TPM_PIO_BASE, SPI_CS_TPM);
#endif

9
hal/spi/spi_drv_stm32.h
View File

@ -279,17 +279,8 @@
#ifndef SPI_MOSI_PIN_AF
#define SPI_MOSI_PIN_AF SPI_PIN_AF
#endif
#ifndef SPI_CS_FLASH_AF
#define SPI_CS_FLASH_AF SPI_PIN_AF
#endif
#ifndef SPI_CS_TPM_AF
#define SPI_CS_TPM_AF SPI_PIN_AF
#endif
#ifdef QSPI_FLASH
#ifndef QSPI_CS_FLASH_AF
#define QSPI_CS_FLASH_AF QSPI_PIN_AF
#endif
#ifndef QSPI_CLOCK_PIN_AF
#define QSPI_CLOCK_PIN_AF QSPI_PIN_AF
#endif