mirror of https://github.com/wolfSSL/wolfBoot.git
Improvements to the NXP T2080 support. Adds NOR Flash and IFC configuration. Adds CPLD support. Make `DEBUG_UART` a configure option.
David Garske
Daniele Lacamera
parent
2fc899254f
commit
bfed41889b
4
Makefile
4
Makefile
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@ -16,8 +16,10 @@ LSCRIPT_FLAGS:=
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LDFLAGS:=
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LD_START_GROUP:=-Wl,--start-group
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LD_END_GROUP:=-Wl,--end-group
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V?=0
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LSCRIPT_IN:=hal/$(TARGET).ld
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V?=0
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DEBUG?=0
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DEBUG_UART?=0
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OBJS:= \
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./hal/$(TARGET).o \
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18
arch.mk
18
arch.mk
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@ -176,24 +176,32 @@ endif
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## RISCV
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ifeq ($(ARCH),RISCV)
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CROSS_COMPILE?=riscv32-unknown-elf-
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CFLAGS+=-fno-builtin-printf -DUSE_M_TIME -g -march=rv32imac -mabi=ilp32 -mcmodel=medany -nostartfiles -DARCH_RISCV
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CFLAGS+=-DUSE_M_TIME -g -march=rv32imac -mabi=ilp32 -mcmodel=medany -nostartfiles -DARCH_RISCV
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LDFLAGS+=-march=rv32imac -mabi=ilp32 -mcmodel=medany
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MATH_OBJS += ./lib/wolfssl/wolfcrypt/src/sp_c32.o
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ifeq ($(DEBUG_UART),0)
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CFLAGS+=-fno-builtin-printf
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endif
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# Prune unused functions and data
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CFLAGS +=-ffunction-sections -fdata-sections
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LDFLAGS+=-Wl,--gc-sections
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OBJS+=src/boot_riscv.o src/vector_riscv.o
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ARCH_FLASH_OFFSET=0x20010000
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ARCH_FLASH_OFFSET?=0x20010000
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endif
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# powerpc
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ifeq ($(ARCH),PPC)
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CROSS_COMPILE?=powerpc-linux-gnu-
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CFLAGS+=-fno-builtin-printf -DUSE_M_TIME -g -nostartfiles
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CFLAGS+=-g -nostartfiles
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LDFLAGS+=-Wl,--build-id=none
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ifeq ($(DEBUG_UART),0)
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CFLAGS+=-fno-builtin-printf
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endif
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# Prune unused functions and data
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CFLAGS +=-ffunction-sections -fdata-sections
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LDFLAGS+=-Wl,--gc-sections
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@ -419,3 +427,7 @@ ifeq ($(DEBUG),1)
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WOLFCRYPT_OBJS+=./lib/wolfssl/wolfcrypt/src/logging.o
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endif
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# Debug UART
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ifeq ($(DEBUG_UART),1)
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CFLAGS+=-DDEBUG_UART
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endif
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@ -6,6 +6,7 @@ SIGN?=ECC384
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HASH?=SHA384
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IMAGE_HEADER_SIZE?=512
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DEBUG?=0
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DEBUG_UART?=1
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VTOR?=1
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CORTEX_M0?=0
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NO_ASM?=0
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398
hal/t2080.c
398
hal/t2080.c
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@ -21,46 +21,52 @@
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#include <stdint.h>
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#include "target.h"
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#define DEBUG_UART
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#define OFFSETOF(type, field) ((uint32_t)&(((type *)0)->field))
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#define CCSRBAR 0xFE000000
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/* T2080 */
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#define CCSRBAR (0xFE000000)
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#define SYS_CLK (600000000)
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/* T2080 PC16552D Dual UART */
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#define UART0_OFFSET 0x11C500
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#define UART1_OFFSET 0x11D500
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#define UART0_BASE (CCSRBAR + UART0_OFFSET)
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#define UART1_BASE (CCSRBAR + UART1_OFFSET)
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#define UART_RBR 0 /* receiver buffer register */
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#define UART_THR 0 /* transmitter holding register */
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#define UART_IER 1 /* interrupt enable register */
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#define UART_IIR 2 /* interrupt ID register */
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#define UART_FCR 2 /* FIFO control register */
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#define UART_FCR_TFR 0x04 /* Transmitter FIFO reset */
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#define UART_FCR_RFR 0x02 /* Receiver FIFO reset */
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#define UART_FCR_FEN 0x01 /* FIFO enable */
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#define UART_LCR 3 /* line control register */
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#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
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#define UART_LCR_WLS 0x03 /* Word length select: 8-bits */
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#define UART_MCR 4 /* modem control register */
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#define UART_LSR 5 /* line status register */
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#define UART_LSR_TEMT 0x40 /* Transmitter empty */
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#define UART_LSR_THRE 0x20 /* Transmitter holding register empty */
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#define UART_DLB 0 /* divisor least significant byte register */
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#define UART_DMB 1 /* divisor most significant byte register */
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#define SYS_CLK 600000000
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#define BAUD_RATE 115200
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#define UART_SEL 0 /* select UART 0 or 1 */
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/* T2080 RM 2.4 */
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#define LAWBARHn(n) *((volatile uint32_t*)(CCSRBAR + 0xC00 + n*0x10 + 0x0))
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#define LAWBARLn(n) *((volatile uint32_t*)(CCSRBAR + 0xC00 + n*0x10 + 0x4))
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#define LAWBARn(n) *((volatile uint32_t*)(CCSRBAR + 0xC00 + n*0x10 + 0x8))
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#define UART_BASE(n) (CCSRBAR + 0x11C500 + (n * 0x1000))
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#define UART_RBR(n) *((volatile uint8_t*)(UART_BASE(n) + 0)) /* receiver buffer register */
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#define UART_THR(n) *((volatile uint8_t*)(UART_BASE(n) + 0)) /* transmitter holding register */
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#define UART_IER(n) *((volatile uint8_t*)(UART_BASE(n) + 1)) /* interrupt enable register */
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#define UART_IIR(n) *((volatile uint8_t*)(UART_BASE(n) + 2)) /* interrupt ID register */
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#define UART_FCR(n) *((volatile uint8_t*)(UART_BASE(n) + 2)) /* FIFO control register */
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#define UART_LCR(n) *((volatile uint8_t*)(UART_BASE(n) + 3)) /* line control register */
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#define UART_MCR(n) *((volatile uint8_t*)(UART_BASE(n) + 4)) /* modem control register */
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#define UART_LSR(n) *((volatile uint8_t*)(UART_BASE(n) + 5)) /* line status register */
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/* enabled when UART_LCR_DLAB set */
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#define UART_DLB(n) *((volatile uint8_t*)(UART_BASE(n) + 0)) /* divisor least significant byte register */
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#define UART_DMB(n) *((volatile uint8_t*)(UART_BASE(n) + 1)) /* divisor most significant byte register */
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#define UART_FCR_TFR (0x04) /* Transmitter FIFO reset */
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#define UART_FCR_RFR (0x02) /* Receiver FIFO reset */
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#define UART_FCR_FEN (0x01) /* FIFO enable */
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#define UART_LCR_DLAB (0x80) /* Divisor latch access bit */
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#define UART_LCR_WLS (0x03) /* Word length select: 8-bits */
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#define UART_LSR_TEMT (0x40) /* Transmitter empty */
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#define UART_LSR_THRE (0x20) /* Transmitter holding register empty */
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/* T2080 LAW - Local Access Window (Memory Map) - RM 2.4 */
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#define LAWBAR_BASE(n) (CCSRBAR + 0xC00 + (n * 0x10))
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#define LAWBARHn(n) *((volatile uint32_t*)(LAWBAR_BASE(n) + 0x0))
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#define LAWBARLn(n) *((volatile uint32_t*)(LAWBAR_BASE(n) + 0x4))
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#define LAWBARn(n) *((volatile uint32_t*)(LAWBAR_BASE(n) + 0x8))
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#define LAWBARn_ENABLE (1<<31)
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#define LAWBARn_TRGT_ID(id) (id<<20)
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/* T2080 Global Source/Target ID Assignments - RM Table 2-1 */
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enum law_target_id {
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LAW_TRGT_BMAN = 0x18, /* Buffer Manager (BMan) (control) */
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LAW_TRGT_IFC = 0x1F, /* Integrated Flash Controller */
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};
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/* T2080 2.4.3 - size is equal to 2^(enum + 1) */
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enum law_sizes {
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@ -96,90 +102,117 @@ enum law_sizes {
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};
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/* T2080 IFC (Integrated Flash Controller) - RM 13.3 */
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#define IFC_BASE (CCSRBAR + 0x00124000)
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#define IFC_MAX_BANKS 8
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#define IFC_CSPR_EXT(n) *((volatile uint32_t*)(IFC_BASE + 0x000C + (n * 0xC))) /* Extended Base Address */
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#define IFC_CSPR(n) *((volatile uint32_t*)(IFC_BASE + 0x0010 + (n * 0xC))) /* Chip-select Property */
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#define IFC_AMASK(n) *((volatile uint32_t*)(IFC_BASE + 0x00A0 + (n * 0xC)))
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#define IFC_CSOR(n) *((volatile uint32_t*)(IFC_BASE + 0x0130 + (n * 0xC)))
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#define IFC_CSOR_EXT(n) *((volatile uint32_t*)(IFC_BASE + 0x0134 + (n * 0xC)))
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#define IFC_FTIM0(n) *((volatile uint32_t*)(IFC_BASE + 0x01C0 + (n * 0x30)))
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#define IFC_FTIM1(n) *((volatile uint32_t*)(IFC_BASE + 0x01C4 + (n * 0x30)))
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#define IFC_FTIM2(n) *((volatile uint32_t*)(IFC_BASE + 0x01C8 + (n * 0x30)))
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#define IFC_FTIM3(n) *((volatile uint32_t*)(IFC_BASE + 0x01CC + (n * 0x30)))
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#define IFC_CSPR_PHYS_ADDR(x) (((uint32_t)x) & 0xFFFF0000) /* Physical base address */
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#define IFC_CSPR_PORT_SIZE_8 0x00000080 /* Port Size 8 */
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#define IFC_CSPR_PORT_SIZE_16 0x00000100 /* Port Size 16 */
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#define IFC_CSPR_WP 0x00000040 /* Write Protect */
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#define IFC_CSPR_MSEL_NOR 0x00000000 /* Mode Select - NOR */
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#define IFC_CSPR_MSEL_NAND 0x00000002 /* Mode Select - NAND */
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#define IFC_CSPR_MSEL_GPCM 0x00000004 /* Mode Select - GPCM (General-purpose chip-select machine) */
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#define IFC_CSPR_V 0x00000001 /* Bank Valid */
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/* NOR Timings (IFC clocks) */
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#define IFC_FTIM0_NOR_TACSE(n) (((n) & 0x0F) << 28) /* After address hold cycle */
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#define IFC_FTIM0_NOR_TEADC(n) (((n) & 0x3F) << 16) /* External latch address delay cycles */
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#define IFC_FTIM0_NOR_TAVDS(n) (((n) & 0x3F) << 8) /* Delay between CS assertion */
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#define IFC_FTIM0_NOR_TEAHC(n) (((n) & 0x3F) << 0) /* External latch address hold cycles */
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#define IFC_FTIM1_NOR_TACO(n) (((n) & 0xFF) << 24) /* CS assertion to output enable */
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#define IFC_FTIM1_NOR_TRAD(n) (((n) & 0x3F) << 8) /* read access delay */
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#define IFC_FTIM1_NOR_TSEQ(n) (((n) & 0x3F) << 0) /* sequential read access delay */
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#define IFC_FTIM2_NOR_TCS(n) (((n) & 0x0F) << 24) /* Chip-select assertion setup time */
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#define IFC_FTIM2_NOR_TCH(n) (((n) & 0x0F) << 18) /* Chip-select hold time */
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#define IFC_FTIM2_NOR_TWPH(n) (((n) & 0x3F) << 10) /* Chip-select hold time */
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#define IFC_FTIM2_NOR_TWP(n) (((n) & 0xFF) << 0) /* Write enable pulse width */
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/* GPCM Timings (IFC clocks) */
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#define IFC_FTIM0_GPCM_TACSE(n) (((n) & 0x0F) << 28) /* After address hold cycle */
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#define IFC_FTIM0_GPCM_TEADC(n) (((n) & 0x3F) << 16) /* External latch address delay cycles */
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#define IFC_FTIM0_GPCM_TEAHC(n) (((n) & 0x3F) << 0) /* External latch address hold cycles */
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#define IFC_FTIM1_GPCM_TACO(n) (((n) & 0xFF) << 24) /* CS assertion to output enable */
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#define IFC_FTIM1_GPCM_TRAD(n) (((n) & 0x3F) << 8) /* read access delay */
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#define IFC_FTIM2_GPCM_TCS(n) (((n) & 0x0F) << 24) /* Chip-select assertion setup time */
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#define IFC_FTIM2_GPCM_TCH(n) (((n) & 0x0F) << 18) /* Chip-select hold time */
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#define IFC_FTIM2_GPCM_TWP(n) (((n) & 0xFF) << 0) /* Write enable pulse width */
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/* IFC AMASK - RM Table 13-3 - Count of MSB minus 1 */
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enum ifc_amask_sizes {
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IFC_AMASK_64KB = 0xFFFF,
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IFC_AMASK_128KB = 0xFFFE,
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IFC_AMASK_256KB = 0xFFFC,
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IFC_AMASK_512KB = 0xFFF8,
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IFC_AMASK_1MB = 0xFFF0,
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IFC_AMASK_2MB = 0xFFC0,
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IFC_AMASK_4MB = 0xFF80,
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IFC_AMASK_8MB = 0xFF00,
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IFC_AMASK_16MB = 0xFE00,
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IFC_AMASK_32MB = 0xFC00,
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IFC_AMASK_128MB = 0xF800,
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IFC_AMASK_256MB = 0xF000,
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IFC_AMASK_512MB = 0xE000,
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IFC_AMASK_1GB = 0xC000,
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IFC_AMASK_2GB = 0x8000,
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IFC_AMASK_4GB = 0x0000,
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};
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/* NOR Flash */
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#define FLASH_BASE 0xE8000000
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#define FLASH_BANK_SIZE (128*1024*1024)
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#define FLASH_PAGE_SIZE (1024) /* program buffer */
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#define FLASH_SECTOR_SIZE (128*1024)
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#define FLASH_SECTORS (FLASH_BANK_SIZE / FLASH_SECTOR_SIZE)
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#define FLASH_CFI_16BIT 0x02 /* word */
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#define FLASH_CFI_WIDTH FLASH_CFI_16BIT
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#define FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
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#define FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
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/* CPLD */
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#define CPLD_BASE 0xFFDF0000
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#define CPLD_BASE (0xFFDF0000)
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#define CPLD_LBMAP_MASK 0x3F
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#define CPLD_BANK_SEL_MASK 0x07
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#define CPLD_BANK_OVERRIDE 0x40
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#define CPLD_LBMAP_ALTBANK 0x44 /* BANK OR | BANK 4 */
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#define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK 0 */
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#define CPLD_LBMAP_RESET 0xFF
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#define CPLD_LBMAP_SHIFT 0x03
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#define CPLD_BOOT_SEL 0x80
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#define CPLD_RSTCON_EDC_RST 0x04 /* RSTCON Register */
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#define CPLD_SPARE 0x00
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#define CPLD_SATA_MUX_SEL 0x02
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#define CPLD_BANK_SEL 0x04
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#define CPLD_FW_REV 0x06
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#define CPLD_TTL_RW 0x08
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#define CPLD_TTL_LPBK 0x0A
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#define CPLD_TTL_DATA 0x0C
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#define CPLD_PROC_STATUS 0x0E /* write 1 to enable proc reset function, reset default value is 0 */
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#define CPLD_FPGA_RDY 0x10 /* read only when reg read 0x0DB1 then fpga is ready */
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#define CPLD_PCIE_SW_RESET 0x12 /* write 1 to reset the PCIe switch */
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#define CPLD_WR_TTL_INT_EN 0x14
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#define CPLD_WR_TTL_INT_DIR 0x16
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#define CPLD_INT_STAT 0x18
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#define CPLD_WR_TEMP_ALM_OVRD 0x1A /* write 0 to enable temp shutdown. reset default value is 1 */
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#define CPLD_PWR_DWN_CMD 0x1C
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#define CPLD_TEMP_ALM_INT_STAT 0x1E
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#define CPLD_WR_TEMP_ALM_INT_EN 0x20
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/* CPLD register set for T2080RDB */
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typedef struct cpld_data {
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uint8_t chip_id1; /* 0x00 - Chip ID1 register */
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uint8_t chip_id2; /* 0x01 - Chip ID2 register */
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uint8_t hw_ver; /* 0x02 - Hardware Revision Register */
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uint8_t sw_ver; /* 0x03 - Software Revision register */
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uint8_t res0[12]; /* 0x04 - 0x0F - not used */
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uint8_t reset_ctl; /* 0x10 - Reset control Register */
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uint8_t flash_csr; /* 0x11 - Flash control and status register */
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uint8_t thermal_csr; /* 0x12 - Thermal control and status register */
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uint8_t led_csr; /* 0x13 - LED control and status register */
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uint8_t sfp_csr; /* 0x14 - SFP+ control and status register */
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uint8_t misc_csr; /* 0x15 - Misc control and status register */
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uint8_t boot_or; /* 0x16 - Boot config override register */
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uint8_t boot_cfg1; /* 0x17 - Boot configuration register 1 */
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uint8_t boot_cfg2; /* 0x18 - Boot configuration register 2 */
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} cpld_data;
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#define CPLD_FLASH_BANK_0 0x00
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#define CPLD_FLASH_BANK_1 0x01
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#define CPLD_READ(reg) cpld_read( OFFSETOF(struct cpld_data, reg))
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#define CPLD_WRITE(reg, value) cpld_write(OFFSETOF(struct cpld_data, reg), value)
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#define CPLD_DATA(n) *((volatile uint8_t*)(CPLD_BASE + n))
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/* SATA */
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#define SATA_ENBL (*(volatile uint32_t *)(0xB1003F4C)) /* also saw 0xB4003F4C */
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/* IO Helpers */
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static inline uint8_t in_8(const volatile uint8_t *addr)
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{
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uint8_t ret;
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asm volatile("sync;\n"
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"lbz %0,%1;\n"
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"isync"
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: "=r" (ret)
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: "m" (*addr));
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return ret;
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}
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static inline void out_8(volatile uint8_t *addr, uint8_t val)
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{
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asm volatile("sync;\n"
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"stb %1,%0;\n"
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: "=m" (*addr)
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: "r" (val));
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}
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/* CPLD */
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static uint8_t cpld_read(uint32_t reg)
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{
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register volatile uint32_t* p = (uint32_t*)CPLD_BASE;
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return in_8((uint8_t*)(p + reg));
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}
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static void cpld_write(uint32_t reg, uint8_t value)
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{
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register volatile uint32_t* p = (uint32_t*)CPLD_BASE;
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out_8((uint8_t*)(p + reg), value);
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}
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/* Set the boot bank to the default bank */
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void cpld_set_defbank(void)
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{
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uint8_t reg = CPLD_READ(flash_csr);
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reg = (reg & ~CPLD_BANK_SEL_MASK) | CPLD_LBMAP_DFLTBANK;
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CPLD_WRITE(flash_csr, reg);
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CPLD_WRITE(reset_ctl, CPLD_LBMAP_RESET);
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}
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#ifdef DEBUG_UART
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static void uart_init(void)
|
||||
{
|
||||
|
|
@ -189,52 +222,54 @@ static void uart_init(void)
|
|||
* +0.5 to round up
|
||||
*/
|
||||
uint32_t div = (((SYS_CLK / 2.0) / (16 * BAUD_RATE)) + 0.5);
|
||||
register volatile uint8_t* uart = (uint8_t*)UART0_BASE;
|
||||
|
||||
while (!(in_8(uart + UART_LSR) & UART_LSR_TEMT))
|
||||
while (!(UART_LSR(UART_SEL) & UART_LSR_TEMT))
|
||||
;
|
||||
|
||||
/* set ier, fcr, mcr */
|
||||
out_8(uart + UART_IER, 0);
|
||||
out_8(uart + UART_FCR, (UART_FCR_TFR | UART_FCR_RFR | UART_FCR_FEN));
|
||||
UART_IER(UART_SEL) = 0;
|
||||
UART_FCR(UART_SEL) = (UART_FCR_TFR | UART_FCR_RFR | UART_FCR_FEN);
|
||||
|
||||
/* enable baud rate access (DLAB=1) - divisor latch access bit*/
|
||||
out_8(uart + UART_LCR, (UART_LCR_DLAB | UART_LCR_WLS));
|
||||
UART_LCR(UART_SEL) = (UART_LCR_DLAB | UART_LCR_WLS);
|
||||
/* set divisor */
|
||||
out_8(uart + UART_DLB, div & 0xff);
|
||||
out_8(uart + UART_DMB, (div>>8) & 0xff);
|
||||
UART_DLB(UART_SEL) = (div & 0xff);
|
||||
UART_DMB(UART_SEL) = ((div>>8) & 0xff);
|
||||
/* disable rate access (DLAB=0) */
|
||||
out_8(uart + UART_LCR, (UART_LCR_WLS));
|
||||
UART_LCR(UART_SEL) = (UART_LCR_WLS);
|
||||
}
|
||||
|
||||
static void uart_write(const char* buf, uint32_t sz)
|
||||
{
|
||||
volatile uint8_t* uart = (uint8_t*)UART0_BASE;
|
||||
uint32_t pos = 0;
|
||||
while (sz-- > 0) {
|
||||
while (!(in_8(uart + UART_LSR) & UART_LSR_THRE))
|
||||
while (!(UART_LSR(UART_SEL) & UART_LSR_THRE))
|
||||
;
|
||||
out_8(uart + UART_THR, buf[pos++]);
|
||||
UART_THR(0) = buf[pos++];
|
||||
}
|
||||
}
|
||||
#endif /* DEBUG_UART */
|
||||
|
||||
|
||||
/* called from boot_ppc_start.S */
|
||||
void law_init(void)
|
||||
{
|
||||
/* T2080RM table 2-1 */
|
||||
int id = 0x1f; /* IFC */
|
||||
LAWBARn (1) = 0;
|
||||
LAWBARHn(1) = 0xf;
|
||||
LAWBARLn(1) = 0xe8000000;
|
||||
LAWBARn (1) = (1<<31) | (id<<20) | LAW_SIZE_256MB;
|
||||
/* IFC - NOR Flash */
|
||||
LAWBARn (1) = 0; /* reset */
|
||||
LAWBARHn(1) = 0xF;
|
||||
LAWBARLn(1) = FLASH_BASE;
|
||||
LAWBARn (1) = LAWBARn_ENABLE | LAWBARn_TRGT_ID(LAW_TRGT_IFC) | LAW_SIZE_128MB;
|
||||
|
||||
id = 0x18;
|
||||
LAWBARn (2) = 0;
|
||||
LAWBARHn(2) = 0xf;
|
||||
LAWBARLn(2) = 0xf4000000;
|
||||
LAWBARn (2) = (1<<31) | (id<<20) | LAW_SIZE_32MB;
|
||||
/* IFC - CPLD */
|
||||
LAWBARn (2) = 0; /* reset */
|
||||
LAWBARHn(2) = 0xF;
|
||||
LAWBARLn(2) = CPLD_BASE;
|
||||
LAWBARn (2) = LAWBARn_ENABLE | LAWBARn_TRGT_ID(LAW_TRGT_IFC) | LAW_SIZE_4KB;
|
||||
|
||||
/* Buffer Manager (BMan) (control) */
|
||||
LAWBARn (3) = 0; /* reset */
|
||||
LAWBARHn(3) = 0xF;
|
||||
LAWBARLn(3) = 0xF4000000;
|
||||
LAWBARn (3) = LAWBARn_ENABLE | LAWBARn_TRGT_ID(LAW_TRGT_BMAN) | LAW_SIZE_32MB;
|
||||
}
|
||||
|
||||
#ifdef DEBUG_UART
|
||||
|
|
@ -248,29 +283,77 @@ static void tohexstr(uint32_t val, char* out)
|
|||
}
|
||||
#endif
|
||||
|
||||
static void hal_flash_init(void)
|
||||
{
|
||||
/* NOR IFC Flash Timing Parameters */
|
||||
IFC_FTIM0(0) = (IFC_FTIM0_NOR_TACSE(4) | \
|
||||
IFC_FTIM0_NOR_TEADC(5) | \
|
||||
IFC_FTIM0_NOR_TEAHC(5));
|
||||
IFC_FTIM1(0) = (IFC_FTIM1_NOR_TACO(53) |
|
||||
IFC_FTIM1_NOR_TRAD(26) |
|
||||
IFC_FTIM1_NOR_TSEQ(19));
|
||||
IFC_FTIM2(0) = (IFC_FTIM2_NOR_TCS(4) |
|
||||
IFC_FTIM2_NOR_TCH(4) |
|
||||
IFC_FTIM2_NOR_TWPH(14) |
|
||||
IFC_FTIM2_NOR_TWP(28));
|
||||
IFC_FTIM3(0) = 0;
|
||||
/* NOR IFC Definitions (CS0) */
|
||||
IFC_CSPR_EXT(0) = (0xF);
|
||||
IFC_CSPR(0) = (IFC_CSPR_PHYS_ADDR(FLASH_BASE) | \
|
||||
IFC_CSPR_PORT_SIZE_16 | \
|
||||
IFC_CSPR_MSEL_NOR | \
|
||||
IFC_CSPR_V);
|
||||
IFC_AMASK(0) = IFC_AMASK_128MB;
|
||||
IFC_CSOR(0) = 0x0000000C; /* TRHZ (80 clocks for read enable high) */
|
||||
}
|
||||
|
||||
static void hal_cpld_init(void)
|
||||
{
|
||||
/* CPLD IFC Timing Parameters */
|
||||
IFC_FTIM0(3) = (IFC_FTIM0_GPCM_TACSE(16) |
|
||||
IFC_FTIM0_GPCM_TEADC(16) |
|
||||
IFC_FTIM0_GPCM_TEAHC(16));
|
||||
IFC_FTIM1(3) = (IFC_FTIM1_GPCM_TACO(16) |
|
||||
IFC_FTIM1_GPCM_TRAD(31));
|
||||
IFC_FTIM2(3) = (IFC_FTIM2_GPCM_TCS(16) |
|
||||
IFC_FTIM2_GPCM_TCH(8) |
|
||||
IFC_FTIM2_GPCM_TWP(31));
|
||||
IFC_FTIM3(3) = 0;
|
||||
|
||||
/* CPLD IFC Definitions (CS3) */
|
||||
IFC_CSPR_EXT(3) = (0xF);
|
||||
IFC_CSPR(3) = (IFC_CSPR_PHYS_ADDR(CPLD_BASE) |
|
||||
IFC_CSPR_PORT_SIZE_16 |
|
||||
IFC_CSPR_MSEL_GPCM |
|
||||
IFC_CSPR_V);
|
||||
IFC_AMASK(3) = IFC_AMASK_64KB;
|
||||
IFC_CSOR(3) = 0;
|
||||
}
|
||||
|
||||
void hal_init(void)
|
||||
{
|
||||
#ifdef DEBUG_UART
|
||||
uint8_t fw;
|
||||
char buf[sizeof(uint32_t)*2];
|
||||
|
||||
uart_init();
|
||||
uart_write("wolfBoot Init\n", 14);
|
||||
|
||||
#if 0 /* NOT WORKING */
|
||||
uart_write("Board Rev: 0x", 13);
|
||||
tohexstr(CPLD_READ(hw_ver), buf);
|
||||
uart_write(buf, 8);
|
||||
uart_write(" CPLD ver: 0x", 13);
|
||||
tohexstr(CPLD_READ(sw_ver), buf);
|
||||
uart_write(buf, 8);
|
||||
uart_write("\n", 1);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
hal_flash_init();
|
||||
hal_cpld_init();
|
||||
|
||||
#if 0 /* NOT TESTED */
|
||||
/* CPLD setup */
|
||||
cpld_set_defbank();
|
||||
CPLD_DATA(CPLD_PROC_STATUS) = 1; /* Enable proc reset */
|
||||
CPLD_DATA(CPLD_WR_TEMP_ALM_OVRD) = 0; /* Enable temp alarm */
|
||||
|
||||
#ifdef DEBUG_UART
|
||||
fw = CPLD_DATA(CPLD_FW_REV);
|
||||
|
||||
uart_write("CPLD FW Rev: 0x", 15);
|
||||
tohexstr(fw, buf);
|
||||
uart_write("\n", 1);
|
||||
#endif
|
||||
|
||||
/* Disable SATA Write Protection */
|
||||
SATA_ENBL = 0;
|
||||
|
|
@ -296,13 +379,32 @@ int hal_flash_erase(uint32_t address, int len)
|
|||
|
||||
void hal_flash_unlock(void)
|
||||
{
|
||||
// CSPRn[WP]
|
||||
//protect off eff40000 +C0000
|
||||
/* Disable all flash protection bits */
|
||||
/* enter Non-volatile protection mode (C0h) */
|
||||
*((volatile uint16_t*)(FLASH_BASE + 0xAAA)) = 0xAAAA;
|
||||
*((volatile uint16_t*)(FLASH_BASE + 0x554)) = 0x5555;
|
||||
*((volatile uint16_t*)(FLASH_BASE + 0xAAA)) = 0xC0C0;
|
||||
/* clear all protection bit (80h/30h) */
|
||||
*((volatile uint16_t*)(FLASH_BASE + 0x000)) = 0x8080;
|
||||
*((volatile uint16_t*)(FLASH_BASE + 0x000)) = 0x3030;
|
||||
/* exit Non-volatile protection mode (90h/00h) */
|
||||
*((volatile uint16_t*)(FLASH_BASE + 0x000)) = 0x9090;
|
||||
*((volatile uint16_t*)(FLASH_BASE + 0x000)) = 0x0000;
|
||||
}
|
||||
|
||||
void hal_flash_lock(void)
|
||||
{
|
||||
//protect on eff40000 +C0000
|
||||
/* Enable all flash protection bits */
|
||||
/* enter Non-volatile protection mode (C0h) */
|
||||
*((volatile uint16_t*)(FLASH_BASE + 0xAAA)) = 0xAAAA;
|
||||
*((volatile uint16_t*)(FLASH_BASE + 0x554)) = 0x5555;
|
||||
*((volatile uint16_t*)(FLASH_BASE + 0xAAA)) = 0xC0C0;
|
||||
/* set all protection bit (A0h/00h) */
|
||||
*((volatile uint16_t*)(FLASH_BASE + 0x000)) = 0xA0A0;
|
||||
*((volatile uint16_t*)(FLASH_BASE + 0x000)) = 0x0000;
|
||||
/* exit Non-volatile protection mode (90h/00h) */
|
||||
*((volatile uint16_t*)(FLASH_BASE + 0x000)) = 0x9090;
|
||||
*((volatile uint16_t*)(FLASH_BASE + 0x000)) = 0x0000;
|
||||
}
|
||||
|
||||
void hal_prepare_boot(void)
|
||||
|
|
|
|||
|
|
@ -21,57 +21,37 @@
|
|||
|
||||
#include <stdint.h>
|
||||
|
||||
#define CCSRBAR 0xFE000000
|
||||
/* T2080 */
|
||||
#define CCSRBAR (0xFE000000)
|
||||
#define SYS_CLK (600000000)
|
||||
|
||||
/* T2080 PC16552D Dual UART */
|
||||
#define UART0_OFFSET 0x11C500
|
||||
#define UART1_OFFSET 0x11D500
|
||||
#define UART0_BASE (CCSRBAR + UART0_OFFSET)
|
||||
#define UART1_BASE (CCSRBAR + UART1_OFFSET)
|
||||
|
||||
#define UART_RBR 0 /* receiver buffer register */
|
||||
#define UART_THR 0 /* transmitter holding register */
|
||||
#define UART_IER 1 /* interrupt enable register */
|
||||
#define UART_IIR 2 /* interrupt ID register */
|
||||
#define UART_FCR 2 /* FIFO control register */
|
||||
#define UART_FCR_TFR 0x04 /* Transmitter FIFO reset */
|
||||
#define UART_FCR_RFR 0x02 /* Receiver FIFO reset */
|
||||
#define UART_FCR_FEN 0x01 /* FIFO enable */
|
||||
|
||||
#define UART_LCR 3 /* line control register */
|
||||
#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
|
||||
#define UART_LCR_WLS 0x03 /* Word length select: 8-bits */
|
||||
#define UART_MCR 4 /* modem control register */
|
||||
|
||||
#define UART_LSR 5 /* line status register */
|
||||
#define UART_LSR_TEMT 0x40 /* Transmitter empty */
|
||||
#define UART_LSR_THRE 0x20 /* Transmitter holding register empty */
|
||||
|
||||
#define UART_DLB 0 /* divisor least significant byte register */
|
||||
#define UART_DMB 1 /* divisor most significant byte register */
|
||||
|
||||
#define SYS_CLK 600000000
|
||||
#define BAUD_RATE 115200
|
||||
#define UART_SEL 0 /* select UART 0 or 1 */
|
||||
|
||||
#define UART_BASE(n) (CCSRBAR + 0x11C500 + (n * 0x1000))
|
||||
|
||||
static inline uint8_t in_8(const volatile unsigned char *addr)
|
||||
{
|
||||
uint8_t ret;
|
||||
asm volatile("sync;\n"
|
||||
"lbz %0,%1;\n"
|
||||
"isync"
|
||||
: "=r" (ret)
|
||||
: "m" (*addr));
|
||||
return ret;
|
||||
}
|
||||
#define UART_RBR(n) *((volatile uint8_t*)(UART_BASE(n) + 0)) /* receiver buffer register */
|
||||
#define UART_THR(n) *((volatile uint8_t*)(UART_BASE(n) + 0)) /* transmitter holding register */
|
||||
#define UART_IER(n) *((volatile uint8_t*)(UART_BASE(n) + 1)) /* interrupt enable register */
|
||||
#define UART_IIR(n) *((volatile uint8_t*)(UART_BASE(n) + 2)) /* interrupt ID register */
|
||||
#define UART_FCR(n) *((volatile uint8_t*)(UART_BASE(n) + 2)) /* FIFO control register */
|
||||
#define UART_LCR(n) *((volatile uint8_t*)(UART_BASE(n) + 3)) /* line control register */
|
||||
#define UART_MCR(n) *((volatile uint8_t*)(UART_BASE(n) + 4)) /* modem control register */
|
||||
#define UART_LSR(n) *((volatile uint8_t*)(UART_BASE(n) + 5)) /* line status register */
|
||||
|
||||
/* enabled when UART_LCR_DLAB set */
|
||||
#define UART_DLB(n) *((volatile uint8_t*)(UART_BASE(n) + 0)) /* divisor least significant byte register */
|
||||
#define UART_DMB(n) *((volatile uint8_t*)(UART_BASE(n) + 1)) /* divisor most significant byte register */
|
||||
|
||||
#define UART_FCR_TFR (0x04) /* Transmitter FIFO reset */
|
||||
#define UART_FCR_RFR (0x02) /* Receiver FIFO reset */
|
||||
#define UART_FCR_FEN (0x01) /* FIFO enable */
|
||||
#define UART_LCR_DLAB (0x80) /* Divisor latch access bit */
|
||||
#define UART_LCR_WLS (0x03) /* Word length select: 8-bits */
|
||||
#define UART_LSR_TEMT (0x40) /* Transmitter empty */
|
||||
#define UART_LSR_THRE (0x20) /* Transmitter holding register empty */
|
||||
|
||||
static inline void out_8(volatile unsigned char *addr, uint8_t val)
|
||||
{
|
||||
asm volatile("sync;\n"
|
||||
"stb %1,%0;\n"
|
||||
: "=m" (*addr)
|
||||
: "r" (val));
|
||||
}
|
||||
|
||||
static void uart_init(void)
|
||||
{
|
||||
|
|
@ -81,32 +61,30 @@ static void uart_init(void)
|
|||
* +0.5 to round up
|
||||
*/
|
||||
uint32_t div = (((SYS_CLK / 2.0) / (16 * BAUD_RATE)) + 0.5);
|
||||
register volatile uint8_t* uart = (uint8_t*)UART0_BASE;
|
||||
|
||||
while (!(in_8(uart + UART_LSR) & UART_LSR_TEMT))
|
||||
while (!(UART_LSR(UART_SEL) & UART_LSR_TEMT))
|
||||
;
|
||||
|
||||
/* set ier, fcr, mcr */
|
||||
out_8(uart + UART_IER, 0);
|
||||
out_8(uart + UART_FCR, (UART_FCR_TFR | UART_FCR_RFR | UART_FCR_FEN));
|
||||
UART_IER(UART_SEL) = 0;
|
||||
UART_FCR(UART_SEL) = (UART_FCR_TFR | UART_FCR_RFR | UART_FCR_FEN);
|
||||
|
||||
/* enable baud rate access (DLAB=1) - divisor latch access bit*/
|
||||
out_8(uart + UART_LCR, (UART_LCR_DLAB | UART_LCR_WLS));
|
||||
UART_LCR(UART_SEL) = (UART_LCR_DLAB | UART_LCR_WLS);
|
||||
/* set divisor */
|
||||
out_8(uart + UART_DLB, div & 0xff);
|
||||
out_8(uart + UART_DMB, (div>>8) & 0xff);
|
||||
UART_DLB(UART_SEL) = (div & 0xff);
|
||||
UART_DMB(UART_SEL) = ((div>>8) & 0xff);
|
||||
/* disable rate access (DLAB=0) */
|
||||
out_8(uart + UART_LCR, (UART_LCR_WLS));
|
||||
UART_LCR(UART_SEL) = (UART_LCR_WLS);
|
||||
}
|
||||
|
||||
static void uart_write(const char* buf, uint32_t sz)
|
||||
{
|
||||
volatile uint8_t* uart = (uint8_t*)UART0_BASE;
|
||||
uint32_t pos = 0;
|
||||
while (sz-- > 0) {
|
||||
while (!(in_8(uart + UART_LSR) & UART_LSR_THRE))
|
||||
while (!(UART_LSR(UART_SEL) & UART_LSR_THRE))
|
||||
;
|
||||
out_8(uart + UART_THR, buf[pos++]);
|
||||
UART_THR(0) = buf[pos++];
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue