mirror of https://github.com/wolfSSL/wolfBoot.git
Add wolfBoot support for STM32G4
David Garske
Daniele Lacamera
parent
0cb6bd42ac
commit
c075549ea2
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@ -458,6 +458,12 @@ jobs:
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arch: arm
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config-file: ./config/examples/stm32g0.config
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stm32g4_test:
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uses: ./.github/workflows/test-build.yml
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with:
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arch: arm
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config-file: ./config/examples/stm32g4.config
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stm32h5_test:
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uses: ./.github/workflows/test-build.yml
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with:
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4
arch.mk
4
arch.mk
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@ -167,6 +167,10 @@ ifeq ($(ARCH),ARM)
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ARCH_FLASH_OFFSET=0x08000000
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endif
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ifeq ($(TARGET),stm32g4)
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ARCH_FLASH_OFFSET=0x08000000
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endif
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ifeq ($(TARGET),stm32f1)
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CORTEX_M3=1
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NO_ARM_ASM=1
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@ -0,0 +1,24 @@
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ARCH?=ARM
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TARGET?=stm32g4
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SIGN?=ECC256
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HASH?=SHA256
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DEBUG?=0
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VTOR?=1
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NO_ASM?=0
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EXT_FLASH?=0
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SPI_FLASH?=0
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ALLOW_DOWNGRADE?=0
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NVM_FLASH_WRITEONCE?=1
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WOLFBOOT_VERSION?=0
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V?=0
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SPMATH?=1
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RAM_CODE?=1
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DUALBANK_SWAP?=0
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# Single-bank 512KB flash, 2KB pages.
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# Layout: 32K boot, 232K app, 232K update, 16K swap.
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WOLFBOOT_SECTOR_SIZE?=0x800
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WOLFBOOT_PARTITION_SIZE?=0x3A000
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WOLFBOOT_PARTITION_BOOT_ADDRESS?=0x08008000
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WOLFBOOT_PARTITION_UPDATE_ADDRESS?=0x08042000
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WOLFBOOT_PARTITION_SWAP_ADDRESS?=0x0807C000
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@ -45,6 +45,7 @@ This README describes configuration of supported targets.
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* [STM32F4](#stm32f4)
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* [STM32F7](#stm32f7)
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* [STM32G0](#stm32g0)
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* [STM32G4](#stm32g4)
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* [STM32H5](#stm32h5)
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* [STM32N6](#stm32n6)
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* [STM32H7](#stm32h7)
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@ -529,6 +530,79 @@ add-symbol-file test-app/image.elf 0x08008100
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mon reset init
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```
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## STM32G4
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Supports STM32G4 single-bank Category 3 parts (verified on NUCLEO-G491RE,
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STM32G491RET6: 512KB flash, 96KB SRAM, Cortex-M4F).
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The HAL boots at 170 MHz using HSI16 + PLL with PWR Range 1 Boost mode
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(RM0440 6.1.4), 4 flash wait states, prefetch + I/D-cache enabled.
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Example 512KB partitioning on STM32G491RE:
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- Sector size: 2KB
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- wolfBoot partition size: 32KB
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- Application partition size: 232KB
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```C
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#define WOLFBOOT_SECTOR_SIZE 0x800 /* 2 KB */
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#define WOLFBOOT_PARTITION_BOOT_ADDRESS 0x08008000
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#define WOLFBOOT_PARTITION_SIZE 0x3A000 /* 232 KB */
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#define WOLFBOOT_PARTITION_UPDATE_ADDRESS 0x08042000
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#define WOLFBOOT_PARTITION_SWAP_ADDRESS 0x0807C000 /* 16 KB swap */
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```
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### Building STM32G4
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Reference configuration (see [/config/examples/stm32g4.config](/config/examples/stm32g4.config)).
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You can copy this to wolfBoot root as `.config`: `cp ./config/examples/stm32g4.config .config`.
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To build you can use `make`.
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The TARGET for this is `stm32g4`: `make TARGET=stm32g4`.
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Cortex-M4F is the default ARM core for this target.
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The option `NVM_FLASH_WRITEONCE=1` is mandatory: the IAP driver writes one
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64-bit doubleword per location and cannot rewrite without an erase first.
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The default signing scheme is ECC256 with SHA256.
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NUCLEO-G491RE has no HSE, so HSI16 is used as the PLL source. The ST-LINK
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virtual COM port is wired to LPUART1 on PA2 (TX) / PA3 (RX) via AF12.
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Optional boot logs over LPUART1 at 115200 8N1 are enabled with
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`CFLAGS_EXTRA+=-DDEBUG_UART`.
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This target is single-bank only -- keep `DUALBANK_SWAP=0`.
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### STM32G4 Programming
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Compile requirements: `make TARGET=stm32g4 NVM_FLASH_WRITEONCE=1`
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The output is a single `factory.bin` that includes `wolfboot.bin` and
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`test-app/image_v1_signed.bin` combined together. This should be programmed
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to the flash start address `0x08000000`.
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Flash using the STM32CubeProgrammer CLI:
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```
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STM32_Programmer_CLI -c port=swd -d factory.bin 0x08000000
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```
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### STM32G4 Debugging
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Use `make DEBUG=1` and program firmware again.
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Start GDB server on port 3333:
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```
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ST-LINK_gdbserver -d -e -r 1 -p 3333
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OR
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st-util -p 3333
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```
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```
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arm-none-eabi-gdb
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add-symbol-file test-app/image.elf 0x08008100
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mon reset init
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```
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## STM32C0
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Supports STM32C0x0/STM32C0x1. Instructions are for the STM Nucleo-C031C6 dev board.
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@ -0,0 +1,284 @@
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/* stm32g4.c
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*
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* Copyright (C) 2026 wolfSSL Inc.
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*
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* This file is part of wolfBoot.
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*
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* wolfBoot is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 3 of the License, or
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* (at your option) any later version.
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*
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* wolfBoot is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
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*/
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#include <stdint.h>
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#include <image.h>
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#include "stm32g4.h"
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#ifndef NVM_FLASH_WRITEONCE
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# error "wolfBoot STM32G4 HAL: no WRITEONCE support detected. Please define NVM_FLASH_WRITEONCE"
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#endif
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static RAMFUNCTION void flash_wait_complete(void)
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{
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while ((FLASH_SR & FLASH_SR_BSY) == FLASH_SR_BSY)
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;
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}
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static void RAMFUNCTION flash_clear_errors(void)
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{
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FLASH_SR |= (FLASH_SR_OPERR | FLASH_SR_PROGERR | FLASH_SR_WRPERR |
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FLASH_SR_PGAERR | FLASH_SR_SIZERR | FLASH_SR_PGSERR |
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FLASH_SR_MISERR | FLASH_SR_FASTERR | FLASH_SR_RDERR |
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FLASH_SR_OPTVERR);
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}
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int RAMFUNCTION hal_flash_write(uint32_t address, const uint8_t *data, int len)
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{
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int i = 0;
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uint32_t *src, *dst;
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flash_clear_errors();
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FLASH_CR |= FLASH_CR_PG;
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while (i < len) {
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flash_clear_errors();
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if ((len - i > 3) && ((((address + i) & 0x07) == 0) &&
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((((uint32_t)data) + i) & 0x07) == 0)) {
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src = (uint32_t *)data;
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dst = (uint32_t *)address;
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flash_wait_complete();
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dst[i >> 2] = src[i >> 2];
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dst[(i >> 2) + 1] = src[(i >> 2) + 1];
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flash_wait_complete();
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i += 8;
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} else {
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uint32_t val[2];
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uint8_t *vbytes = (uint8_t *)(val);
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int off = (address + i) - (((address + i) >> 3) << 3);
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uint32_t base_addr = address & (~0x07); /* aligned to 64 bit */
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int u32_idx = (i >> 2);
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dst = (uint32_t *)(base_addr);
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val[0] = dst[u32_idx];
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val[1] = dst[u32_idx + 1];
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while ((off < 8) && (i < len))
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vbytes[off++] = data[i++];
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dst[u32_idx] = val[0];
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dst[u32_idx + 1] = val[1];
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flash_wait_complete();
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}
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}
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if ((FLASH_SR & FLASH_SR_EOP) == FLASH_SR_EOP)
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FLASH_SR |= FLASH_SR_EOP;
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FLASH_CR &= ~FLASH_CR_PG;
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return 0;
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}
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void RAMFUNCTION hal_flash_unlock(void)
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{
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flash_wait_complete();
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if ((FLASH_CR & FLASH_CR_LOCK) != 0) {
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FLASH_KEY = FLASH_KEY1;
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DMB();
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FLASH_KEY = FLASH_KEY2;
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DMB();
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while ((FLASH_CR & FLASH_CR_LOCK) != 0)
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;
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}
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}
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void RAMFUNCTION hal_flash_lock(void)
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{
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flash_wait_complete();
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if ((FLASH_CR & FLASH_CR_LOCK) == 0)
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FLASH_CR |= FLASH_CR_LOCK;
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}
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int RAMFUNCTION hal_flash_erase(uint32_t address, int len)
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{
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uint32_t end_address;
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uint32_t p;
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uint32_t page_number;
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uint32_t reg;
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if (len == 0)
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return -1;
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address -= FLASHMEM_ADDRESS_SPACE;
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end_address = address + len - 1;
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for (p = address; p < end_address; p += FLASH_PAGE_SIZE) {
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flash_wait_complete();
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flash_clear_errors();
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page_number = (p >> 11) & FLASH_CR_PNB_MASK;
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reg = FLASH_CR & ~(FLASH_CR_PNB_MASK << FLASH_CR_PNB_SHIFT);
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FLASH_CR = reg | (page_number << FLASH_CR_PNB_SHIFT) | FLASH_CR_PER;
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DMB();
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FLASH_CR |= FLASH_CR_STRT;
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flash_wait_complete();
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FLASH_CR &= ~FLASH_CR_PER;
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}
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return 0;
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}
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static void clock_pll_off(void)
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{
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uint32_t reg32;
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/* Switch back to HSI16 as SYSCLK source before turning off the PLL. */
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reg32 = RCC_CFGR;
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reg32 &= ~RCC_CFGR_SW_MASK;
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RCC_CFGR = (reg32 | RCC_CFGR_SW_HSI);
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DMB();
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while (((RCC_CFGR >> RCC_CFGR_SWS_SHIFT) & RCC_CFGR_SW_MASK)
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!= RCC_CFGR_SW_HSI)
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;
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RCC_CR &= ~RCC_CR_PLLON;
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DMB();
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while ((RCC_CR & RCC_CR_PLLRDY) != 0)
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;
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}
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/* Bring SYSCLK up to 170 MHz from HSI16 + PLL with Range 1 Boost mode.
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* Sequence per RM0440 - 6.1.4: PWR boost must precede flash wait states
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* and PLL enable. */
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static void clock_pll_on(int powersave)
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{
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uint32_t reg32;
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uint32_t pllm = 4;
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uint32_t plln = 85;
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uint32_t pllr = 2;
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uint32_t flash_waitstates = FLASH_ACR_LATENCY_4WS;
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(void)powersave;
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/* Enable PWR clock so VOS/R1MODE writes take effect. */
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RCC_APB1ENR1 |= RCC_APB1ENR1_PWREN;
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(void)RCC_APB1ENR1;
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/* Voltage scaling Range 1 (boost-capable). */
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reg32 = PWR_CR1;
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reg32 = (reg32 & ~PWR_CR1_VOS_MASK) | PWR_CR1_VOS_RANGE1;
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PWR_CR1 = reg32;
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while ((PWR_SR2 & PWR_SR2_VOSF) != 0)
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;
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/* Clear R1MODE to enable Boost (required above 150 MHz). */
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PWR_CR5 &= ~PWR_CR5_R1MODE;
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/* HSI16 already on at reset; be explicit. */
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RCC_CR |= RCC_CR_HSION;
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DMB();
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while ((RCC_CR & RCC_CR_HSIRDY) == 0)
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;
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/* Set flash wait states + caches before raising CPU frequency. */
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FLASH_ACR = (FLASH_ACR & ~FLASH_ACR_LATENCY_MASK)
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| flash_waitstates
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| FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN;
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while ((FLASH_ACR & FLASH_ACR_LATENCY_MASK) != flash_waitstates)
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;
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/* PLL must be off before reprogramming PLLCFGR. */
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RCC_CR &= ~RCC_CR_PLLON;
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while ((RCC_CR & RCC_CR_PLLRDY) != 0)
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;
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/* PLL: SRC=HSI16, M=4 (raw 3), N=85, R=2 (raw 0), enable R output.
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* VCO = 16 MHz / 4 * 85 = 340 MHz. SYSCLK = 340 / 2 = 170 MHz. */
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reg32 = RCC_PLLCFGR_PLLSRC_HSI16;
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reg32 |= ((pllm - 1) << RCC_PLLCFGR_PLLM_SHIFT);
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reg32 |= (plln << RCC_PLLCFGR_PLLN_SHIFT);
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reg32 |= (((pllr >> 1) - 1) << RCC_PLLCFGR_PLLR_SHIFT);
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reg32 |= RCC_PLLCFGR_PLLREN;
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RCC_PLLCFGR = reg32;
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DMB();
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RCC_CR |= RCC_CR_PLLON;
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while ((RCC_CR & RCC_CR_PLLRDY) == 0)
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;
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/* Switch SYSCLK source to PLL R. */
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reg32 = RCC_CFGR;
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reg32 = (reg32 & ~RCC_CFGR_SW_MASK) | RCC_CFGR_SW_PLL;
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RCC_CFGR = reg32;
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DMB();
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while (((RCC_CFGR >> RCC_CFGR_SWS_SHIFT) & RCC_CFGR_SW_MASK)
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!= RCC_CFGR_SW_PLL)
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;
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/* SYSCFG clock for any post-init configuration. */
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RCC_APB2ENR |= RCC_APB2ENR_SYSCFGEN;
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}
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/* Optional debug UART on NUCLEO-G491RE ST-LINK VCP: LPUART1 PA2/PA3 AF12.
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* Available when: wolfBoot with DEBUG_UART, or test-app (always). */
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#if defined(DEBUG_UART) || !defined(__WOLFBOOT)
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void uart_init(void)
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{
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uint32_t reg;
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const uint32_t tx_pin = NUCLEO_G491_UART_TX_PIN;
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const uint32_t rx_pin = NUCLEO_G491_UART_RX_PIN;
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RCC_AHB2ENR |= RCC_AHB2ENR_GPIOAEN;
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(void)RCC_AHB2ENR;
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RCC_APB1ENR2 |= RCC_APB1ENR2_LPUART1EN;
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(void)RCC_APB1ENR2;
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/* PA2, PA3 -> alternate function (MODER = 10b). */
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reg = GPIOA_MODER & ~((0x3u << (tx_pin * 2)) | (0x3u << (rx_pin * 2)));
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GPIOA_MODER = reg | ((0x2u << (tx_pin * 2)) | (0x2u << (rx_pin * 2)));
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/* High speed (11b) so 115200 edges are clean even at 170 MHz. */
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GPIOA_OSPEEDR |= (0x3u << (tx_pin * 2)) | (0x3u << (rx_pin * 2));
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/* AF12 (LPUART1) on PA2 and PA3 - AFRL bits [11:8] and [15:12]. */
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reg = GPIOA_AFRL & ~((0xFu << (tx_pin * 4)) | (0xFu << (rx_pin * 4)));
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GPIOA_AFRL = reg | ((NUCLEO_G491_UART_AF << (tx_pin * 4))
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| (NUCLEO_G491_UART_AF << (rx_pin * 4)));
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LPUART1_CR1 = 0;
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LPUART1_BRR = STM32G4_LPUART1_BRR(STM32G4_UART_BAUD);
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LPUART1_CR1 = USART_CR1_TE | USART_CR1_RE | USART_CR1_UE;
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while ((LPUART1_ISR & USART_ISR_TEACK) == 0)
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;
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}
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void uart_write(const char *buf, unsigned int len)
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{
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unsigned int i;
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for (i = 0; i < len; i++) {
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while ((LPUART1_ISR & USART_ISR_TXE) == 0)
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;
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LPUART1_TDR = (uint32_t)buf[i];
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}
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}
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#endif /* DEBUG_UART || !__WOLFBOOT */
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void hal_init(void)
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{
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clock_pll_on(0);
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#if defined(DEBUG_UART) && defined(__WOLFBOOT)
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uart_init();
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#endif
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}
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void RAMFUNCTION hal_prepare_boot(void)
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{
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#ifdef SPI_FLASH
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spi_flash_release();
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#endif
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#ifdef WOLFBOOT_RESTORE_CLOCK
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clock_pll_off();
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#endif
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}
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@ -0,0 +1,177 @@
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/* stm32g4.h
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*
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* Copyright (C) 2026 wolfSSL Inc.
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*
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* This file is part of wolfBoot.
|
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*
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* wolfBoot is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* wolfBoot is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
|
||||
*/
|
||||
|
||||
/* STM32G4 family (e.g. STM32G491RE on NUCLEO-G491RE).
|
||||
* Cortex-M4F, no TrustZone. Single-bank 512 KB flash, 2 KB pages.
|
||||
* Reference: RM0440. Shared register map for the wolfBoot HAL and
|
||||
* the test-app -- both pull in the same definitions so wire-up
|
||||
* doesn't drift between them. */
|
||||
|
||||
#ifndef _STM32G4_H_
|
||||
#define _STM32G4_H_
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/* Assembly helpers */
|
||||
#define DMB() __asm__ volatile ("dmb")
|
||||
#define ISB() __asm__ volatile ("isb")
|
||||
#define DSB() __asm__ volatile ("dsb")
|
||||
|
||||
|
||||
/* -------- RCC (AHB1 + 0x1000 = 0x40021000) -------- RM0440 - 7.4 -------- */
|
||||
#define RCC_BASE (0x40021000)
|
||||
#define RCC_CR (*(volatile uint32_t *)(RCC_BASE + 0x00))
|
||||
#define RCC_CFGR (*(volatile uint32_t *)(RCC_BASE + 0x08))
|
||||
#define RCC_PLLCFGR (*(volatile uint32_t *)(RCC_BASE + 0x0C))
|
||||
#define RCC_CRRCR (*(volatile uint32_t *)(RCC_BASE + 0x98))
|
||||
#define RCC_CCIPR (*(volatile uint32_t *)(RCC_BASE + 0x88))
|
||||
#define RCC_AHB2ENR (*(volatile uint32_t *)(RCC_BASE + 0x4C))
|
||||
#define RCC_APB1ENR1 (*(volatile uint32_t *)(RCC_BASE + 0x58))
|
||||
#define RCC_APB1ENR2 (*(volatile uint32_t *)(RCC_BASE + 0x5C))
|
||||
#define RCC_APB2ENR (*(volatile uint32_t *)(RCC_BASE + 0x60))
|
||||
|
||||
#define RCC_CR_PLLRDY (1 << 25)
|
||||
#define RCC_CR_PLLON (1 << 24)
|
||||
#define RCC_CR_HSIRDY (1 << 10)
|
||||
#define RCC_CR_HSION (1 << 8)
|
||||
|
||||
#define RCC_CFGR_SW_HSI 0x1
|
||||
#define RCC_CFGR_SW_PLL 0x3
|
||||
#define RCC_CFGR_SW_MASK 0x3
|
||||
#define RCC_CFGR_SWS_SHIFT 2
|
||||
|
||||
#define RCC_PLLCFGR_PLLREN (1 << 24)
|
||||
#define RCC_PLLCFGR_PLLR_SHIFT 25
|
||||
#define RCC_PLLCFGR_PLLN_SHIFT 8
|
||||
#define RCC_PLLCFGR_PLLM_SHIFT 4
|
||||
#define RCC_PLLCFGR_PLLSRC_HSI16 0x2
|
||||
|
||||
#define RCC_CRRCR_HSI48ON (1 << 0)
|
||||
#define RCC_CRRCR_HSI48RDY (1 << 1)
|
||||
|
||||
#define RCC_AHB2ENR_GPIOAEN (1 << 0)
|
||||
#define RCC_APB1ENR1_PWREN (1 << 28)
|
||||
#define RCC_APB1ENR2_LPUART1EN (1 << 0)
|
||||
#define RCC_APB2ENR_SYSCFGEN (1 << 0)
|
||||
|
||||
|
||||
/* -------- PWR (APB1 = 0x40007000) -------- RM0440 - 6.4 -------- */
|
||||
#define PWR_BASE (0x40007000)
|
||||
#define PWR_CR1 (*(volatile uint32_t *)(PWR_BASE + 0x00))
|
||||
#define PWR_CR5 (*(volatile uint32_t *)(PWR_BASE + 0x80))
|
||||
#define PWR_SR2 (*(volatile uint32_t *)(PWR_BASE + 0x14))
|
||||
|
||||
#define PWR_CR1_VOS_SHIFT 9
|
||||
#define PWR_CR1_VOS_MASK (0x3 << PWR_CR1_VOS_SHIFT)
|
||||
#define PWR_CR1_VOS_RANGE1 (0x1 << PWR_CR1_VOS_SHIFT)
|
||||
#define PWR_CR5_R1MODE (1 << 0) /* 0 = Range 1 Boost */
|
||||
#define PWR_SR2_VOSF (1 << 10)
|
||||
|
||||
|
||||
/* -------- FLASH (AHB1 + 0x2000 = 0x40022000) -------- RM0440 - 3.7 -------- */
|
||||
#define FLASH_BASE (0x40022000)
|
||||
#define FLASH_ACR (*(volatile uint32_t *)(FLASH_BASE + 0x00))
|
||||
#define FLASH_KEY (*(volatile uint32_t *)(FLASH_BASE + 0x08))
|
||||
#define FLASH_SR (*(volatile uint32_t *)(FLASH_BASE + 0x10))
|
||||
#define FLASH_CR (*(volatile uint32_t *)(FLASH_BASE + 0x14))
|
||||
|
||||
#define FLASHMEM_ADDRESS_SPACE (0x08000000)
|
||||
#define FLASH_PAGE_SIZE (0x800) /* 2KB */
|
||||
|
||||
#define FLASH_ACR_LATENCY_MASK (0x7)
|
||||
#define FLASH_ACR_PRFTEN (1 << 8)
|
||||
#define FLASH_ACR_ICEN (1 << 9)
|
||||
#define FLASH_ACR_DCEN (1 << 10)
|
||||
#define FLASH_ACR_LATENCY_4WS (0x4)
|
||||
|
||||
/* G4 has a single BSY at bit 16 (no BSY1/BSY2 like G0). */
|
||||
#define FLASH_SR_BSY (1 << 16)
|
||||
#define FLASH_SR_OPTVERR (1 << 15)
|
||||
#define FLASH_SR_RDERR (1 << 14)
|
||||
#define FLASH_SR_FASTERR (1 << 9)
|
||||
#define FLASH_SR_MISERR (1 << 8)
|
||||
#define FLASH_SR_PGSERR (1 << 7)
|
||||
#define FLASH_SR_SIZERR (1 << 6)
|
||||
#define FLASH_SR_PGAERR (1 << 5)
|
||||
#define FLASH_SR_WRPERR (1 << 4)
|
||||
#define FLASH_SR_PROGERR (1 << 3)
|
||||
#define FLASH_SR_OPERR (1 << 1)
|
||||
#define FLASH_SR_EOP (1 << 0)
|
||||
|
||||
/* G491 (Cat 3) is single-bank: PNB is 8 bits at [10:3], no BKER. */
|
||||
#define FLASH_CR_LOCK (1UL << 31)
|
||||
#define FLASH_CR_STRT (1 << 16)
|
||||
#define FLASH_CR_PER (1 << 1)
|
||||
#define FLASH_CR_PG (1 << 0)
|
||||
#define FLASH_CR_PNB_SHIFT 3
|
||||
#define FLASH_CR_PNB_MASK 0xFF
|
||||
|
||||
#define FLASH_KEY1 (0x45670123)
|
||||
#define FLASH_KEY2 (0xCDEF89AB)
|
||||
|
||||
|
||||
/* -------- GPIOA (AHB2 = 0x48000000) -------- RM0440 - 9.4 -------- */
|
||||
#define GPIOA_BASE (0x48000000)
|
||||
#define GPIOA_MODER (*(volatile uint32_t *)(GPIOA_BASE + 0x00))
|
||||
#define GPIOA_OTYPER (*(volatile uint32_t *)(GPIOA_BASE + 0x04))
|
||||
#define GPIOA_OSPEEDR (*(volatile uint32_t *)(GPIOA_BASE + 0x08))
|
||||
#define GPIOA_PUPDR (*(volatile uint32_t *)(GPIOA_BASE + 0x0C))
|
||||
#define GPIOA_ODR (*(volatile uint32_t *)(GPIOA_BASE + 0x14))
|
||||
#define GPIOA_BSRR (*(volatile uint32_t *)(GPIOA_BASE + 0x18))
|
||||
#define GPIOA_AFRL (*(volatile uint32_t *)(GPIOA_BASE + 0x20))
|
||||
#define GPIOA_AFRH (*(volatile uint32_t *)(GPIOA_BASE + 0x24))
|
||||
|
||||
|
||||
/* -------- LPUART1 (APB1 = 0x40008000) -------- RM0440 - 38.7 -------- */
|
||||
#define LPUART1_BASE (0x40008000)
|
||||
#define LPUART1_CR1 (*(volatile uint32_t *)(LPUART1_BASE + 0x00))
|
||||
#define LPUART1_BRR (*(volatile uint32_t *)(LPUART1_BASE + 0x0C))
|
||||
#define LPUART1_ISR (*(volatile uint32_t *)(LPUART1_BASE + 0x1C))
|
||||
#define LPUART1_TDR (*(volatile uint32_t *)(LPUART1_BASE + 0x28))
|
||||
|
||||
#define USART_CR1_UE (1 << 0)
|
||||
#define USART_CR1_RE (1 << 2)
|
||||
#define USART_CR1_TE (1 << 3)
|
||||
#define USART_ISR_TEACK (1 << 21)
|
||||
#define USART_ISR_TXE (1 << 7)
|
||||
|
||||
|
||||
/* -------- SYSCLK / boot defaults -------- */
|
||||
#define STM32G4_SYSCLK_HZ (170000000UL)
|
||||
#define STM32G4_UART_BAUD (115200UL)
|
||||
/* LPUART_BRR = (256 * f_LPUART) / baud. PCLK1 = SYSCLK on default prescalers. */
|
||||
#define STM32G4_LPUART1_BRR(baud) \
|
||||
((uint32_t)(((uint64_t)256u * STM32G4_SYSCLK_HZ) / (baud)))
|
||||
|
||||
|
||||
/* -------- NUCLEO-G491RE board specifics -------- */
|
||||
#define NUCLEO_G491_LED_LD2_PIN (5) /* PA5 */
|
||||
#define NUCLEO_G491_UART_TX_PIN (2) /* PA2 - LPUART1_TX */
|
||||
#define NUCLEO_G491_UART_RX_PIN (3) /* PA3 - LPUART1_RX */
|
||||
#define NUCLEO_G491_UART_AF (12)
|
||||
|
||||
|
||||
/* Public helpers implemented in hal/stm32g4.c. Available to wolfBoot when
|
||||
* DEBUG_UART is set, and to the test-app at all times. */
|
||||
void uart_init(void);
|
||||
void uart_write(const char *buf, unsigned int len);
|
||||
|
||||
#endif /* _STM32G4_H_ */
|
||||
|
|
@ -0,0 +1,50 @@
|
|||
MEMORY
|
||||
{
|
||||
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = @BOOTLOADER_PARTITION_SIZE@
|
||||
RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00018000 /* 96 KB on G491RE */
|
||||
}
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
.text :
|
||||
{
|
||||
_start_text = .;
|
||||
KEEP(*(.isr_vector))
|
||||
*(.text*)
|
||||
*(.rodata*)
|
||||
. = ALIGN(4);
|
||||
_end_text = .;
|
||||
} > FLASH
|
||||
|
||||
.edidx :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.ARM.exidx*)
|
||||
} > FLASH
|
||||
|
||||
_stored_data = .;
|
||||
.data : AT (_stored_data)
|
||||
{
|
||||
_start_data = .;
|
||||
KEEP(*(.data*))
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.ramcode))
|
||||
. = ALIGN(4);
|
||||
_end_data = .;
|
||||
} > RAM
|
||||
|
||||
.bss (NOLOAD) :
|
||||
{
|
||||
_start_bss = .;
|
||||
__bss_start__ = .;
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
_end_bss = .;
|
||||
__bss_end__ = .;
|
||||
_end = .;
|
||||
} > RAM
|
||||
. = ALIGN(4);
|
||||
}
|
||||
|
||||
END_STACK = ORIGIN(RAM) + LENGTH(RAM);
|
||||
|
|
@ -919,6 +919,23 @@ endif
|
|||
ifeq ($(TARGET),stm32g0)
|
||||
CFLAGS+=-DNVM_FLASH_WRITEONCE=1
|
||||
endif
|
||||
ifeq ($(TARGET),stm32g4)
|
||||
CFLAGS+=-DNVM_FLASH_WRITEONCE=1
|
||||
CFLAGS+=-I../hal
|
||||
LDFLAGS+=-Wl,-gc-sections
|
||||
# Test app uses printf via syscalls.o (routes _write -> uart_write).
|
||||
# syscalls.c references uart_write/uart_vprintf from string.o; string.o
|
||||
# is already pulled in when DEBUG_UART=1. Pull it in unconditionally so
|
||||
# printf is available even when DEBUG_UART is off.
|
||||
ifeq ($(DEBUG_UART),)
|
||||
APP_OBJS+=../src/string.o
|
||||
endif
|
||||
APP_OBJS+=syscalls.o
|
||||
# _Min_Heap_Size is consumed by syscalls.c _sbrk(); ARM.ld does not
|
||||
# define a heap, so anchor it at zero. _sbrk is gc'd when malloc is
|
||||
# unused, but the symbol must still resolve.
|
||||
LDFLAGS+=-Wl,--defsym=_Min_Heap_Size=0
|
||||
endif
|
||||
ifeq ($(TARGET),stm32c0)
|
||||
CFLAGS+=-DNVM_FLASH_WRITEONCE=1
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -0,0 +1,94 @@
|
|||
/* app_stm32g4.c
|
||||
*
|
||||
* Test bare-metal application for the STM32G4 (NUCLEO-G491RE).
|
||||
*
|
||||
* Copyright (C) 2026 wolfSSL Inc.
|
||||
*
|
||||
* This file is part of wolfBoot.
|
||||
*
|
||||
* wolfBoot is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* wolfBoot is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdio.h>
|
||||
#include "hal.h"
|
||||
#include "stm32g4.h"
|
||||
#include "wolfboot/wolfboot.h"
|
||||
#include "target.h"
|
||||
|
||||
#ifdef TARGET_stm32g4
|
||||
|
||||
static void led_init(void)
|
||||
{
|
||||
uint32_t reg;
|
||||
RCC_AHB2ENR |= RCC_AHB2ENR_GPIOAEN;
|
||||
reg = RCC_AHB2ENR;
|
||||
(void)reg;
|
||||
|
||||
reg = GPIOA_MODER & ~(0x3u << (NUCLEO_G491_LED_LD2_PIN * 2));
|
||||
GPIOA_MODER = reg | (0x1u << (NUCLEO_G491_LED_LD2_PIN * 2));
|
||||
GPIOA_PUPDR &= ~(0x3u << (NUCLEO_G491_LED_LD2_PIN * 2));
|
||||
}
|
||||
|
||||
static void led_on(void)
|
||||
{
|
||||
GPIOA_BSRR = (1u << NUCLEO_G491_LED_LD2_PIN);
|
||||
}
|
||||
|
||||
static void led_off(void)
|
||||
{
|
||||
GPIOA_BSRR = (1u << (NUCLEO_G491_LED_LD2_PIN + 16));
|
||||
}
|
||||
|
||||
static void busy_delay(uint32_t count)
|
||||
{
|
||||
volatile uint32_t i;
|
||||
for (i = 0; i < count; i++)
|
||||
__asm__ volatile ("nop");
|
||||
}
|
||||
|
||||
void main(void)
|
||||
{
|
||||
uint32_t version;
|
||||
uint32_t on_ticks, off_ticks;
|
||||
|
||||
hal_init();
|
||||
led_init();
|
||||
uart_init();
|
||||
|
||||
version = wolfBoot_current_firmware_version();
|
||||
printf("TEST APP\r\n");
|
||||
printf("App version: %lu\r\n", (unsigned long)version);
|
||||
|
||||
/* v1: slow blink. v2+: fast blink + mark update successful. */
|
||||
if (version >= 2) {
|
||||
wolfBoot_success();
|
||||
printf("Update confirmed.\r\n");
|
||||
on_ticks = 200000;
|
||||
off_ticks = 200000;
|
||||
} else {
|
||||
on_ticks = 600000;
|
||||
off_ticks = 600000;
|
||||
}
|
||||
|
||||
while (1) {
|
||||
led_on();
|
||||
busy_delay(on_ticks);
|
||||
led_off();
|
||||
busy_delay(off_ticks);
|
||||
}
|
||||
}
|
||||
|
||||
#endif /* TARGET_stm32g4 */
|
||||
|
|
@ -230,3 +230,28 @@ void boot_led_off(void)
|
|||
}
|
||||
|
||||
#endif /* TARGET_stm32l4 */
|
||||
|
||||
#ifdef TARGET_stm32g4
|
||||
#include "stm32g4.h"
|
||||
/* NUCLEO-G491RE user LED LD2 on PA5. */
|
||||
|
||||
void boot_led_on(void)
|
||||
{
|
||||
uint32_t reg;
|
||||
const uint32_t pin = NUCLEO_G491_LED_LD2_PIN;
|
||||
RCC_AHB2ENR |= RCC_AHB2ENR_GPIOAEN;
|
||||
reg = RCC_AHB2ENR; /* read-back so GPIOA clock is live before MODER write */
|
||||
(void)reg;
|
||||
reg = GPIOA_MODER & ~(0x03 << (pin * 2));
|
||||
GPIOA_MODER = reg | (1 << (pin * 2));
|
||||
reg = GPIOA_PUPDR & ~(0x03 << (pin * 2));
|
||||
GPIOA_PUPDR = reg | (1 << (pin * 2));
|
||||
GPIOA_BSRR = (1 << pin); /* BSRR is write-only; bare assignment, not |= */
|
||||
}
|
||||
|
||||
void boot_led_off(void)
|
||||
{
|
||||
GPIOA_BSRR = (1 << (NUCLEO_G491_LED_LD2_PIN + 16));
|
||||
}
|
||||
|
||||
#endif /* TARGET_stm32g4 */
|
||||
|
|
|
|||
Loading…
Reference in New Issue