diff --git a/arch.mk b/arch.mk index 2d3ea6ab..fbc6838c 100644 --- a/arch.mk +++ b/arch.mk @@ -128,14 +128,33 @@ endif ifeq ($(TARGET),imx_rt) ARCH_FLASH_OFFSET=0x60000000 - CFLAGS+=-I$(MCUXPRESSO_DRIVERS)/drivers -I$(MCUXPRESSO_DRIVERS) -DCPU_$(MCUXPRESSO_CPU) -I$(MCUXPRESSO_CMSIS)/Include -DDEBUG_CONSOLE_ASSERT_DISABLE=1 \ - -I$(MCUXPRESSO_DRIVERS)/project_template/ -I$(MCUXPRESSO)/boards/evkmimxrt1060/xip/ - OBJS+= $(MCUXPRESSO)/middleware/mflash/mimxrt1062/mflash_drv.o $(MCUXPRESSO_DRIVERS)/drivers/fsl_dcp.o + CFLAGS+=-I$(MCUXPRESSO_DRIVERS)/drivers -I$(MCUXPRESSO_DRIVERS) -I$(MCUXPRESSO)/middleware/mflash/mimxrt1062 \ + -I$(MCUXPRESSO_DRIVERS)/utilities/debug_console/ \ + -I$(MCUXPRESSO_DRIVERS)/utilities/str/ \ + -I$(MCUXPRESSO)/components/uart/ \ + -I$(MCUXPRESSO)/components/flash/nor \ + -I$(MCUXPRESSO)/components/flash/nor/flexspi \ + -I$(MCUXPRESSO)/components/serial_manager/ \ + -DCPU_$(MCUXPRESSO_CPU) -I$(MCUXPRESSO_CMSIS)/Include -DDEBUG_CONSOLE_ASSERT_DISABLE=1 -I$(MCUXPRESSO_DRIVERS)/project_template/ \ + -I$(MCUXPRESSO)/boards/evkmimxrt1060/xip/ -DXIP_EXTERNAL_FLASH=1 -DDEBUG_CONSOLE_ASSERT_DISABLE=1 -DPRINTF_ADVANCED_ENABLE=1 \ + -DSCANF_ADVANCED_ENABLE=1 -DSERIAL_PORT_TYPE_UART=1 + OBJS+= $(MCUXPRESSO)/middleware/mflash/mimxrt1062/mflash_drv.o $(MCUXPRESSO_DRIVERS)/drivers/fsl_dcp.o \ + $(MCUXPRESSO_DRIVERS)/drivers/fsl_clock.o $(MCUXPRESSO_DRIVERS)/drivers/fsl_flexspi.o + OBJS+= $(MCUXPRESSO_DRIVERS)/utilities/str/fsl_str.o \ + $(MCUXPRESSO)/components/uart/lpuart_adapter.o \ + $(MCUXPRESSO)/components/serial_manager/serial_manager.o \ + $(MCUXPRESSO)/components/lists/generic_list.o \ + $(MCUXPRESSO)/components/serial_manager/serial_port_uart.o \ + $(MCUXPRESSO_DRIVERS)/drivers/fsl_lpuart.o \ + $(MCUXPRESSO_DRIVERS)/utilities/debug_console/fsl_debug_console.o \ + $(MCUXPRESSO)/components/flash/nor/flexspi/fsl_flexspi_nor_flash.o \ + $(MCUXPRESSO_DRIVERS)/system_MIMXRT1062.o + ifeq ($(PKA),1) PKA_EXTRA_OBJS+=\ $(MCUXPRESSO_DRIVERS)/drivers/fsl_dcp.o \ ./lib/wolfssl/wolfcrypt/src/port/nxp/dcp_port.o - PKA_EXTRA_CFLAGS+=-DWOLFSSL_IMXRT_DCP + PKA_EXTRA_CFLAGS+=-D__FLASH_BASE=$(ARCH_FLASH_OFFSET) endif endif diff --git a/hal/imx_rt.c b/hal/imx_rt.c index bf09e635..e7a5ad2e 100644 --- a/hal/imx_rt.c +++ b/hal/imx_rt.c @@ -1,6 +1,6 @@ /* imx-rt.c * - * Custom HAL implementation. Defines the + * Custom HAL implementation. Defines the * functions used by wolfboot for a specific target. * * Copyright (C) 2020 wolfSSL Inc. @@ -26,36 +26,103 @@ #include #include "image.h" #include "fsl_common.h" -#include "evkmimxrt1060_flexspi_nor_config.h" +#include "fsl_iomuxc.h" +#include "fsl_nor_flash.h" +#include "fsl_flexspi.h" +//#include "evkmimxrt1060_flexspi_nor_config.h" +#include "fsl_flexspi_nor_flash.h" +#include "imx_rt_nor.h" +#include "xip/fsl_flexspi_nor_boot.h" + +#define FLASH_PAGE_SIZE WOLFBOOT_SECTOR_SIZE #ifdef __WOLFBOOT - const flexspi_nor_config_t __attribute__((section(".flash_config"))) qspiflash_config = { .memConfig = + { + .tag = FLEXSPI_CFG_BLK_TAG, + .version = FLEXSPI_CFG_BLK_VERSION, + .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad, + .csHoldTime = 3u, + .csSetupTime = 3u, + .sflashPadType = kSerialFlash_4Pads, + .serialClkFreq = kFlexSpiSerialClk_100MHz, + .sflashA1Size = 8u * 1024u * 1024u, + .lookupTable = { - .tag = FLEXSPI_CFG_BLK_TAG, - .version = FLEXSPI_CFG_BLK_VERSION, - .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad, - .csHoldTime = 3u, - .csSetupTime = 3u, - .sflashPadType = kSerialFlash_4Pads, - .serialClkFreq = kFlexSpiSerialClk_100MHz, - .sflashA1Size = 8u * 1024u * 1024u, - .lookupTable = - { - // Read LUTs - FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18), - FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, FLEXSPI_4PAD, 0x04), - }, + // Read LUTs + FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18), + FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, FLEXSPI_4PAD, 0x04), }, + }, .pageSize = 256u, .sectorSize = 4u * 1024u, .blockSize = 64u * 1024u, .isUniformBlockSize = false, }; +#ifndef __FLASH_BASE +# define __FLASH_BASE 0x60000000 +#endif +#ifndef FLASH_BASE +#define FLASH_BASE __FLASH_BASE +#define FLASH_SIZE 0x800000 +#define PLUGIN_FLAG 0x0UL +#endif + +const uint8_t dcd_data[1] = {0}; +extern void isr_reset(void); + +const ivt __attribute__((section(".image_vt"))) image_vector_table = { + IVT_HEADER, /* IVT Header */ + (uint32_t)isr_reset, /* Image Entry Function */ + IVT_RSVD, /* Reserved = 0 */ + (uint32_t)dcd_data, /* Address where DCD information is stored */ + (uint32_t)&boot_data, /* Address where BOOT Data Structure is stored */ + (uint32_t)&image_vector_table, /* Pointer to IVT Self (absolute address */ + (uint32_t)CSF_ADDRESS, /* Address where CSF file is stored */ + IVT_RSVD /* Reserved = 0 */ +}; + +const BOOT_DATA_T __attribute__((section(".boot_data"))) boot_data = { + FLASH_BASE, /* boot start location */ + FLASH_SIZE, /* size */ + PLUGIN_FLAG, /* Plugin flag*/ + 0xFFFFFFFF /* empty - extra data word */ +}; + +/******************************************************************************* + * Variables for BOARD_BootClockRUN configuration + ******************************************************************************/ +const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN = + { + .loopDivider = 100, /* PLL loop divider, Fout = Fin * 50 */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + }; +const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN = + { + .loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */ + .numerator = 0, /* 30 bit numerator of fractional loop divider */ + .denominator = 1, /* 30 bit denominator of fractional loop divider */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + }; +const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN = + { + .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + }; +const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN = + { + .loopDivider = 31, /* PLL loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */ + .postDivider = 8, /* Divider after PLL */ + .numerator = 0, /* 30 bit numerator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */ + .denominator = 1, /* 30 bit denominator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + }; + + void hal_init(void) { } @@ -66,8 +133,60 @@ void hal_prepare_boot(void) #endif +flexspi_mem_config_t flexcfg = { + .deviceConfig = + { + .flexspiRootClk = 120000000, + .flashSize = FLASH_SIZE, + .CSIntervalUnit = kFLEXSPI_CsIntervalUnit1SckCycle, + .CSInterval = 2, + .CSHoldTime = 3, + .CSSetupTime = 3, + .dataValidTime = 0, + .columnspace = 0, + .enableWordAddress = 0, + .AHBWriteWaitUnit = kFLEXSPI_AhbWriteWaitUnit2AhbCycle, + .AHBWriteWaitInterval = 0, + }, + .devicePort = kFLEXSPI_PortA1, + .deviceType = kSerialNorCfgOption_DeviceType_ReadSFDP_SDR, + .quadMode = kSerialNorQuadMode_NotConfig, + .transferMode = kSerialNorTransferMode_SDR, + .enhanceMode = kSerialNorEnhanceMode_Disabled, + .commandPads = kFLEXSPI_1PAD, + .queryPads = kFLEXSPI_1PAD, + .statusOverride = 0, + .busyOffset = 0, + .busyBitPolarity = 0, + +}; + +static nor_config_t norConfig = { + .memControlConfig = &flexcfg, + .driverBaseAddr = FLEXSPI, +}; + +static nor_handle_t norHandle = {NULL}; + +void FLEXSPI_ClockInit(); + +static int nor_flash_init(void) +{ + status_t status; + FLEXSPI_ClockInit(); + return Nor_Flash_Init(&norConfig, &norHandle); +} + + + int RAMFUNCTION hal_flash_write(uint32_t address, const uint8_t *data, int len) { + /* + status_t status; + status = Nor_Flash_Page_Program(&norHandle, address, data); + if (kStatus_Success != status) + return -1; + */ return 0; } @@ -81,6 +200,16 @@ void RAMFUNCTION hal_flash_lock(void) int RAMFUNCTION hal_flash_erase(uint32_t address, int len) { + /* + uint32_t end = address + len - 1; + uint32_t p; + status_t status; + for (p = address; p <= end; p += FLASH_PAGE_SIZE) { + status = Nor_Flash_Erase_Sector(&norHandle, address); + if (status != kStatus_Success) + return -1; + } + */ return 0; } diff --git a/hal/imx_rt.ld b/hal/imx_rt.ld index 2aeb490b..4dbab060 100644 --- a/hal/imx_rt.ld +++ b/hal/imx_rt.ld @@ -13,8 +13,12 @@ SECTIONS _start_text = .; KEEP(*(.flash_config)) . = ORIGIN(FLASH) + 0x1000; + KEEP(*(.image_vt)) + KEEP(*(.boot_data)) + KEEP(*(.dcd_data)) + . = ORIGIN(FLASH) + 0x2000; KEEP(*(.isr_vector)) - . = ALIGN(8); + . = ALIGN(0x8); *(.text*) *(.rodata*) *(.glue_7) /* glue arm to thumb code */ diff --git a/hal/imx_rt_nor.h b/hal/imx_rt_nor.h new file mode 100644 index 00000000..a3a14b22 --- /dev/null +++ b/hal/imx_rt_nor.h @@ -0,0 +1,235 @@ +#ifndef IMXRT_NOR +#define IMXRT_NOR +/* FLEXSPI memory config block related defintions */ +#define FLEXSPI_CFG_BLK_TAG (0x42464346UL) // ascii "FCFB" Big Endian +#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0 +#define FLEXSPI_CFG_BLK_SIZE (512) + +/* FLEXSPI Feature related definitions */ +#define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1 + +/* Lookup table related defintions */ +#define CMD_INDEX_READ 0 +#define CMD_INDEX_READSTATUS 1 +#define CMD_INDEX_WRITEENABLE 2 +#define CMD_INDEX_WRITE 4 + +#define CMD_LUT_SEQ_IDX_READ 0 +#define CMD_LUT_SEQ_IDX_READSTATUS 1 +#define CMD_LUT_SEQ_IDX_WRITEENABLE 3 +#define CMD_LUT_SEQ_IDX_WRITE 9 + +#define CMD_SDR 0x01 +#define CMD_DDR 0x21 +#define RADDR_SDR 0x02 +#define RADDR_DDR 0x22 +#define CADDR_SDR 0x03 +#define CADDR_DDR 0x23 +#define MODE1_SDR 0x04 +#define MODE1_DDR 0x24 +#define MODE2_SDR 0x05 +#define MODE2_DDR 0x25 +#define MODE4_SDR 0x06 +#define MODE4_DDR 0x26 +#define MODE8_SDR 0x07 +#define MODE8_DDR 0x27 +#define WRITE_SDR 0x08 +#define WRITE_DDR 0x28 +#define READ_SDR 0x09 +#define READ_DDR 0x29 +#define LEARN_SDR 0x0A +#define LEARN_DDR 0x2A +#define DATSZ_SDR 0x0B +#define DATSZ_DDR 0x2B +#define DUMMY_SDR 0x0C +#define DUMMY_DDR 0x2C +#define DUMMY_RWDS_SDR 0x0D +#define DUMMY_RWDS_DDR 0x2D +#define JMP_ON_CS 0x1F +#define STOP 0 + +#define FLEXSPI_1PAD 0 +#define FLEXSPI_2PAD 1 +#define FLEXSPI_4PAD 2 +#define FLEXSPI_8PAD 3 + +#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \ + (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \ + FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1)) + +//!@brief Definitions for FlexSPI Serial Clock Frequency +typedef enum _FlexSpiSerialClockFreq +{ + kFlexSpiSerialClk_30MHz = 1, + kFlexSpiSerialClk_50MHz = 2, + kFlexSpiSerialClk_60MHz = 3, + kFlexSpiSerialClk_75MHz = 4, + kFlexSpiSerialClk_80MHz = 5, + kFlexSpiSerialClk_100MHz = 6, + kFlexSpiSerialClk_120MHz = 7, + kFlexSpiSerialClk_133MHz = 8, + kFlexSpiSerialClk_166MHz = 9, +} flexspi_serial_clk_freq_t; + +//!@brief FlexSPI clock configuration type +enum +{ + kFlexSpiClk_SDR, //!< Clock configure for SDR mode + kFlexSpiClk_DDR, //!< Clock configurat for DDR mode +}; + +//!@brief FlexSPI Read Sample Clock Source definition +typedef enum _FlashReadSampleClkSource +{ + kFlexSPIReadSampleClk_LoopbackInternally = 0, + kFlexSPIReadSampleClk_LoopbackFromDqsPad = 1, + kFlexSPIReadSampleClk_LoopbackFromSckPad = 2, + kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3, +} flexspi_read_sample_clk_t; + +//!@brief Misc feature bit definitions +enum +{ + kFlexSpiMiscOffset_DiffClkEnable = 0, //!< Bit for Differential clock enable + kFlexSpiMiscOffset_Ck2Enable = 1, //!< Bit for CK2 enable + kFlexSpiMiscOffset_ParallelEnable = 2, //!< Bit for Parallel mode enable + kFlexSpiMiscOffset_WordAddressableEnable = 3, //!< Bit for Word Addressable enable + kFlexSpiMiscOffset_SafeConfigFreqEnable = 4, //!< Bit for Safe Configuration Frequency enable + kFlexSpiMiscOffset_PadSettingOverrideEnable = 5, //!< Bit for Pad setting override enable + kFlexSpiMiscOffset_DdrModeEnable = 6, //!< Bit for DDR clock confiuration indication. +}; + +//!@brief Flash Type Definition +enum +{ + kFlexSpiDeviceType_SerialNOR = 1, //!< Flash devices are Serial NOR + kFlexSpiDeviceType_SerialNAND = 2, //!< Flash devices are Serial NAND + kFlexSpiDeviceType_SerialRAM = 3, //!< Flash devices are Serial RAM/HyperFLASH + kFlexSpiDeviceType_MCP_NOR_NAND = 0x12, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND + kFlexSpiDeviceType_MCP_NOR_RAM = 0x13, //!< Flash deivce is MCP device, A1 is Serial NOR, A2 is Serial RAMs +}; + +//!@brief Flash Pad Definitions +enum +{ + kSerialFlash_1Pad = 1, + kSerialFlash_2Pads = 2, + kSerialFlash_4Pads = 4, + kSerialFlash_8Pads = 8, +}; + +//!@brief FlexSPI LUT Sequence structure +typedef struct _lut_sequence +{ + uint8_t seqNum; //!< Sequence Number, valid number: 1-16 + uint8_t seqId; //!< Sequence Index, valid number: 0-15 + uint16_t reserved; +} flexspi_lut_seq_t; + +//!@brief Flash Configuration Command Type +enum +{ + kDeviceConfigCmdType_Generic, //!< Generic command, for example: configure dummy cycles, drive strength, etc + kDeviceConfigCmdType_QuadEnable, //!< Quad Enable command + kDeviceConfigCmdType_Spi2Xpi, //!< Switch from SPI to DPI/QPI/OPI mode + kDeviceConfigCmdType_Xpi2Spi, //!< Switch from DPI/QPI/OPI to SPI mode + kDeviceConfigCmdType_Spi2NoCmd, //!< Switch to 0-4-4/0-8-8 mode + kDeviceConfigCmdType_Reset, //!< Reset device command +}; + + +/* */ +#define NOR_CMD_INDEX_READ CMD_INDEX_READ //!< 0 +#define NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS //!< 1 +#define NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE //!< 2 +#define NOR_CMD_INDEX_ERASESECTOR 3 //!< 3 +#define NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE //!< 4 +#define NOR_CMD_INDEX_CHIPERASE 5 //!< 5 +#define NOR_CMD_INDEX_DUMMY 6 //!< 6 +#define NOR_CMD_INDEX_ERASEBLOCK 7 //!< 7 + +#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI \ + 2 //!< 2 Read status DPI/QPI/OPI sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI \ + 4 //!< 4 Write Enable DPI/QPI/OPI sequence id in lookupTable stored in config block + +/* + * Serial NOR configuration block + */ +typedef struct _FlexSPIConfig +{ + uint32_t tag; //!< [0x000-0x003] Tag, fixed value 0x42464346UL + uint32_t version; //!< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix + uint32_t reserved0; //!< [0x008-0x00b] Reserved for future use + uint8_t readSampleClkSrc; //!< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3 + uint8_t csHoldTime; //!< [0x00d-0x00d] CS hold time, default value: 3 + uint8_t csSetupTime; //!< [0x00e-0x00e] CS setup time, default value: 3 + uint8_t columnAddressWidth; //!< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For + //! Serial NAND, need to refer to datasheet + uint8_t deviceModeCfgEnable; //!< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable + uint8_t deviceModeType; //!< [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch, + //! Generic configuration, etc. + uint16_t waitTimeCfgCommands; //!< [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for + //! DPI/QPI/OPI switch or reset command + flexspi_lut_seq_t deviceModeSeq; //!< [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt + //! sequence number, [31:16] Reserved + uint32_t deviceModeArg; //!< [0x018-0x01b] Argument/Parameter for device configuration + uint8_t configCmdEnable; //!< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable + uint8_t configModeType[3]; //!< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe + flexspi_lut_seq_t + configCmdSeqs[3]; //!< [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq + uint32_t reserved1; //!< [0x02c-0x02f] Reserved for future use + uint32_t configCmdArgs[3]; //!< [0x030-0x03b] Arguments/Parameters for device Configuration commands + uint32_t reserved2; //!< [0x03c-0x03f] Reserved for future use + uint32_t controllerMiscOption; //!< [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more + //! details + uint8_t deviceType; //!< [0x044-0x044] Device Type: See Flash Type Definition for more details + uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal + uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequencey, device specific definitions, See System Boot + //! Chapter for more details + uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot + //! be done using 1 LUT sequence, currently, only applicable to HyperFLASH + uint32_t reserved3[2]; //!< [0x048-0x04f] Reserved for future use + uint32_t sflashA1Size; //!< [0x050-0x053] Size of Flash connected to A1 + uint32_t sflashA2Size; //!< [0x054-0x057] Size of Flash connected to A2 + uint32_t sflashB1Size; //!< [0x058-0x05b] Size of Flash connected to B1 + uint32_t sflashB2Size; //!< [0x05c-0x05f] Size of Flash connected to B2 + uint32_t csPadSettingOverride; //!< [0x060-0x063] CS pad setting override value + uint32_t sclkPadSettingOverride; //!< [0x064-0x067] SCK pad setting override value + uint32_t dataPadSettingOverride; //!< [0x068-0x06b] data pad setting override value + uint32_t dqsPadSettingOverride; //!< [0x06c-0x06f] DQS pad setting override value + uint32_t timeoutInMs; //!< [0x070-0x073] Timeout threshold for read status command + uint32_t commandInterval; //!< [0x074-0x077] CS deselect interval between two commands + uint16_t dataValidTime[2]; //!< [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B, in terms of 0.1ns + uint16_t busyOffset; //!< [0x07c-0x07d] Busy offset, valid value: 0-31 + uint16_t busyBitPolarity; //!< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 - + //! busy flag is 0 when flash device is busy + uint32_t lookupTable[64]; //!< [0x080-0x17f] Lookup table holds Flash command sequences + flexspi_lut_seq_t lutCustomSeq[12]; //!< [0x180-0x1af] Customizable LUT Sequences + uint32_t reserved4[4]; //!< [0x1b0-0x1bf] Reserved for future use +} flexspi_common_mem_t; + +typedef struct _flexspi_nor_config +{ + flexspi_common_mem_t memConfig; //!< Common memory configuration info via FlexSPI + uint32_t pageSize; //!< Page size of Serial NOR + uint32_t sectorSize; //!< Sector size of Serial NOR + uint8_t ipcmdSerialClkFreq; //!< Clock frequency for IP command + uint8_t isUniformBlockSize; //!< Sector/Block size is the same + uint8_t reserved0[2]; //!< Reserved for future use + uint8_t serialNorType; //!< Serial NOR Flash type: 0/1/2/3 + uint8_t needExitNoCmdMode; //!< Need to exit NoCmd mode before other IP command + uint8_t halfClkForNonReadCmd; //!< Half the Serial Clock for non-read command: true/false + uint8_t needRestoreNoCmdMode; //!< Need to Restore NoCmd mode after IP commmand execution + uint32_t blockSize; //!< Block size + uint32_t reserve2[11]; //!< Reserved for future use +} flexspi_nor_config_t; + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif +#endif /* __EVKMIMXRT1060_FLEXSPI_NOR_CONFIG__ */ diff --git a/src/xmalloc_ecc.c b/src/xmalloc_ecc.c index c556d893..4a123547 100644 --- a/src/xmalloc_ecc.c +++ b/src/xmalloc_ecc.c @@ -36,7 +36,11 @@ # define SCRATCHBOARD_SIZE (512) # define SP_DIGITS_SIZE (320) # define MAX_POINTS (4) +#ifndef WC_NO_CACHE_RESISTANT +# define MULTIPOINT_SIZE (17) +#else # define MULTIPOINT_SIZE (16) +#endif #else # define SP_POINT_SIZE (244) # define SCRATCHBOARD_SIZE (640) diff --git a/test-app/Makefile b/test-app/Makefile index e0a33131..47245d89 100644 --- a/test-app/Makefile +++ b/test-app/Makefile @@ -77,7 +77,7 @@ ifeq ($(TARGET),kinetis) endif ifeq ($(TARGET),imx_rt) - CFLAGS+=-I$(MCUXPRESSO_DRIVERS)/drivers -I$(MCUXPRESSO_DRIVERS) -DCPU_$(MCUXPRESSO_CPU) -I$(MCUXPRESSO_CMSIS)/Include -DDEBUG_CONSOLE_ASSERT_DISABLE=1 \ + CFLAGS+=-I$(MCUXPRESSO_DRIVERS)/drivers -I$(MCUXPRESSO_DRIVERS) -DCPU_$(MCUXPRESSO_CPU) -I$(MCUXPRESSO_CMSIS)/Include -DDEBUG_CONSOLE_ASSERT_DISABLE=1 -DXIP_EXTERNAL_FLASH=1 \ -I$(MCUXPRESSO_DRIVERS)/project_template/ -I$(MCUXPRESSO)/boards/evkmimxrt1060/xip/ \ -I$(MCUXPRESSO_DRIVERS)/utilities/debug_console/ -I$(MCUXPRESSO)/components/serial_manager \ -I$(MCUXPRESSO)/components/uart/ -I$(MCUXPRESSO_DRIVERS)/utilities/str/ \ diff --git a/test-app/app_imx_rt.c b/test-app/app_imx_rt.c index 8042b8f0..79fc822e 100644 --- a/test-app/app_imx_rt.c +++ b/test-app/app_imx_rt.c @@ -1,16 +1,10 @@ +#include "wolfboot/wolfboot.h" +#include "fsl_common.h" +#include "fsl_clock.h" #include "fsl_debug_console.h" #include "fsl_gpio.h" -#ifndef BOARD_USER_LED_GPIO -#define BOARD_USER_LED_GPIO GPIO1 -#endif -#ifndef BOARD_USER_LED_GPIO_PIN -#define BOARD_USER_LED_GPIO_PIN (9U) -#endif - -#define EXAMPLE_LED_GPIO BOARD_USER_LED_GPIO -#define EXAMPLE_LED_GPIO_PIN BOARD_USER_LED_GPIO_PIN #define EXAMPLE_DELAY_COUNT 8000000 static int g_pinSet = false; @@ -24,28 +18,33 @@ void delay(void) } } +void BOARD_ConfigMPU(void); +void BOARD_InitPins(void); +void BOARD_InitBootClocks(void); +void BOARD_InitDebugConsole(void); + void main() { BOARD_ConfigMPU(); BOARD_InitPins(); BOARD_InitBootClocks(); + SystemCoreClockUpdate(); SysTick_Config(SystemCoreClock / 1000U); BOARD_InitDebugConsole(); - PRINTF("wolfBoot Test app, version = %\n", wolfBoot_get_image_version()); + PRINTF("wolfBoot Test app, version = %d\n", wolfBoot_current_firmware_version()); while(1) { SDK_DelayAtLeastUs(100000, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); if (g_pinSet) { - GPIO_PinWrite(EXAMPLE_LED_GPIO, EXAMPLE_LED_GPIO_PIN, 0U); + GPIO_PinWrite(GPIO1, 9U, 0U); g_pinSet = false; } else { - GPIO_PinWrite(EXAMPLE_LED_GPIO, EXAMPLE_LED_GPIO_PIN, 1U); + GPIO_PinWrite(GPIO1, 9U, 1U); g_pinSet = true; } } - } diff --git a/test-app/imx_rt_pin_mux.c b/test-app/imx_rt_pin_mux.c index 86678360..09990901 100644 --- a/test-app/imx_rt_pin_mux.c +++ b/test-app/imx_rt_pin_mux.c @@ -31,13 +31,14 @@ board: MIMXRT1060-EVK #include "fsl_common.h" #include "fsl_iomuxc.h" +#include "fsl_gpio.h" #include "pin_mux.h" /* FUNCTION ************************************************************************************************************ - * + * * Function Name : BOARD_InitBootPins * Description : Calls initialization functions. - * + * * END ****************************************************************************************************************/ void BOARD_InitBootPins(void) { BOARD_InitPins(); @@ -65,6 +66,13 @@ BOARD_InitPins: void BOARD_InitPins(void) { CLOCK_EnableClock(kCLOCK_Iomuxc); /* iomuxc clock (iomuxc_clk_enable): 0x03U */ + gpio_pin_config_t USER_LED_config = { + .direction = kGPIO_DigitalOutput, + .outputLogic = 0U, + .interruptMode = kGPIO_NoIntmode + }; + GPIO_PinInit(GPIO1, 9U, &USER_LED_config); + IOMUXC_SetPinMux( IOMUXC_GPIO_AD_B0_10_ARM_TRACE_SWO, /* GPIO_AD_B0_10 is configured as ARM_TRACE_SWO */ 0U); /* Software Input On Field: Input Path is determined by functionality */