mirror of https://github.com/wolfSSL/wolfBoot.git
Addressed reviewer's comments
Daniele Lacamera
parent
238e678db6
commit
c80937bdea
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@ -2,7 +2,7 @@ ARCH?=ARM
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TARGET?=sama5d3
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SIGN?=ECC256
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HASH?=SHA256
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DEBUG?=1
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DEBUG?=0
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VTOR?=1
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CORTEX_M0?=0
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NO_ASM?=0
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164
hal/sama5d3.c
164
hal/sama5d3.c
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@ -32,82 +32,82 @@ void sleep_us(uint32_t usec);
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/* Manual division operation */
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static int division(uint32_t dividend,
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uint32_t divisor,
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uint32_t *quotient,
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uint32_t *remainder)
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uint32_t divisor,
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uint32_t *quotient,
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uint32_t *remainder)
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{
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uint32_t shift;
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uint32_t divisor_shift;
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uint32_t factor = 0;
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unsigned char end_flag = 0;
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uint32_t shift;
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uint32_t divisor_shift;
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uint32_t factor = 0;
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unsigned char end_flag = 0;
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if (!divisor)
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return 0xffffffff;
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if (!divisor)
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return 0xffffffff;
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if (dividend < divisor) {
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*quotient = 0;
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*remainder = dividend;
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return 0;
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}
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if (dividend < divisor) {
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*quotient = 0;
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*remainder = dividend;
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return 0;
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}
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while (dividend >= divisor) {
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for (shift = 0, divisor_shift = divisor;
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dividend >= divisor_shift;
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divisor_shift <<= 1, shift++) {
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if (dividend - divisor_shift < divisor_shift) {
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factor += 1 << shift;
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dividend -= divisor_shift;
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end_flag = 1;
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break;
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}
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}
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while (dividend >= divisor) {
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for (shift = 0, divisor_shift = divisor;
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dividend >= divisor_shift;
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divisor_shift <<= 1, shift++) {
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if (dividend - divisor_shift < divisor_shift) {
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factor += 1 << shift;
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dividend -= divisor_shift;
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end_flag = 1;
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break;
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}
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}
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if (end_flag)
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continue;
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if (end_flag)
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continue;
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factor += 1 << (shift - 1);
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dividend -= divisor_shift >> 1;
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}
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factor += 1 << (shift - 1);
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dividend -= divisor_shift >> 1;
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}
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if (quotient)
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*quotient = factor;
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if (quotient)
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*quotient = factor;
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if (remainder)
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*remainder = dividend;
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if (remainder)
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*remainder = dividend;
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return 0;
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return 0;
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}
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static uint32_t div(uint32_t dividend, uint32_t divisor)
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{
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uint32_t quotient = 0;
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uint32_t remainder = 0;
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int ret;
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uint32_t quotient = 0;
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uint32_t remainder = 0;
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int ret;
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ret = division(dividend, divisor, "ient, &remainder);
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if (ret)
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return 0xffffffff;
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ret = division(dividend, divisor, "ient, &remainder);
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if (ret)
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return 0xffffffff;
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return quotient;
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return quotient;
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}
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static uint32_t mod(uint32_t dividend, uint32_t divisor)
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{
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uint32_t quotient = 0;
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uint32_t remainder = 0;
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int ret;
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uint32_t quotient = 0;
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uint32_t remainder = 0;
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int ret;
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ret = division(dividend, divisor, "ient, &remainder);
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if (ret)
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return 0xffffffff;
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ret = division(dividend, divisor, "ient, &remainder);
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if (ret)
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return 0xffffffff;
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return remainder;
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return remainder;
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}
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/* RAM configuration: 2 x MT47H64M16 on SAMA5D3-Xplained
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* 8 Mwords x 8 Banks x 16 bits x 2, total 2 Gbit
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*/
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static struct dram ddram ={
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static const struct dram ddram ={
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.timing = { /* Hardcoded for MT47H64M16, */
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.tras = 6,
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.trcd = 2,
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@ -132,7 +132,7 @@ static struct dram ddram ={
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void master_clock_set(uint32_t prescaler)
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{
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uint32_t mck = PMC_MCKR & (PMC_MDIV_MASK | PMC_CSS_MASK);
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uint32_t mck = PMC_MCKR & (PMC_MDIV_MASK | PMC_CSS_MASK);
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uint32_t diff = mck ^ prescaler;
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if (diff & PMC_ALTPRES_MASK) {
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@ -262,7 +262,6 @@ static void ddr_init(void)
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cal &= ~(MPDDRC_IOCALIBR_RDIV_MASK);
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cal |= MPDDRC_IOCALIBR_RDIV_DDR2_RZQ_50; /* 50 ohm */
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cal &= ~(MPDDRC_IOCALIBR_TZQIO_MASK);
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//cal |= (80 << MPDDRC_IOCALIBR_TZQIO_SHIFT); /* 100 cycles at 133MHz is 0.75 us, 100 cycles at 166MHz is 0.6 us */
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cal |= (100 << MPDDRC_IOCALIBR_TZQIO_SHIFT); /* 100 cycles at 133MHz is 0.75 us, 100 cycles at 166MHz is 0.6 us */
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MPDDRC_IO_CALIBR = cal;
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@ -608,7 +607,7 @@ int ext_flash_read(uintptr_t address, uint8_t *data, int len)
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sz = remaining;
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do {
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ret = nand_check_bad_block(block);
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ret = nand_check_bad_block(block);
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if (ret < 0) {
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/* Block is bad, skip it */
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block++;
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@ -661,35 +660,39 @@ void pit_init(void)
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void sleep_us(uint32_t usec)
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{
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uint32_t base = PIT_PIIR;
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uint32_t delay;
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uint32_t current;
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uint32_t base = PIT_PIIR;
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uint32_t delay;
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uint32_t current;
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/* Since our division function which costs much run time
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* causes the delay time error.
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* So here using shifting to implement the division.
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* to change "1000" to "1024", this cause some inaccuacy,
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* but it is acceptable.
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* ((MASTER_CLOCK / 1024) * usec) / (16 * 1024)
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*/
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/* Since our division function which costs much run time
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* causes the delay time error.
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* So here using shifting to implement the division.
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* to change "1000" to "1024", this cause some inaccuacy,
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* but it is acceptable.
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* ((MASTER_CLOCK / 1024) * usec) / (16 * 1024)
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*/
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delay = ((MASTER_FREQ >> 10) * usec) >> 14;
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do {
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current = PIT_PIIR;
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current -= base;
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} while (current < delay);
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do {
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current = PIT_PIIR;
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current -= base;
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} while (current < delay);
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}
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int ext_flash_write(uintptr_t address, const uint8_t *data, int len)
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{
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/* TODO */
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(void)address;
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(void)data;
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(void)len;
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return 0;
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}
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int ext_flash_erase(uintptr_t address, int len)
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{
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/* TODO */
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(void)address;
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(void)len;
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return 0;
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}
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@ -704,22 +707,12 @@ void ext_flash_lock(void)
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void* hal_get_dts_address(void)
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{
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return (void*)&dts_addr;
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return (void*)&dts_addr;
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}
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void* hal_get_dts_update_address(void)
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{
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return NULL; /* Not yet supported */
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}
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/* QSPI functions */
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void qspi_init(uint32_t cpu_clock, uint32_t flash_freq)
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{
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}
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void zynq_init(uint32_t cpu_clock)
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{
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return NULL; /* Not yet supported */
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}
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@ -740,6 +733,9 @@ void hal_prepare_boot(void)
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int RAMFUNCTION hal_flash_write(uint32_t address, const uint8_t *data, int len)
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{
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(void)address;
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(void)data;
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(void)len;
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return 0;
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}
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@ -754,6 +750,8 @@ void RAMFUNCTION hal_flash_lock(void)
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int RAMFUNCTION hal_flash_erase(uint32_t address, int len)
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{
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(void)address;
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(void)len;
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return 0;
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}
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@ -1,3 +1,25 @@
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/* sama5d3.h
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*
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* Header file for SAMA5D3 HAL
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*
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* Copyright (C) 2024 wolfSSL Inc.
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*
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* This file is part of wolfBoot.
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*
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* wolfBoot is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 3 of the License, or
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* (at your option) any later version.
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*
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* wolfBoot is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
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*/
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#ifndef SAMA5D3_HAL_H
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#define SAMA5D3_HAL_H
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@ -5,9 +27,9 @@
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#include <stdint.h>
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/* CPU/Board clock settings */
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#define CPU_FREQ 264000000
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#define MASTER_FREQ 132000000
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#define CRYSTAL_FREQ 12000000
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#define CPU_FREQ 264000000UL
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#define MASTER_FREQ 132000000UL
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#define CRYSTAL_FREQ 12000000UL
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#define MULA 43
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/* PLLA register
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@ -309,11 +331,11 @@ extern void *kernel_addr, *update_addr, *dts_addr;
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#define NAND_FLASH_OOB_SIZE 0x40 /* 64B */
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/* Address space mapping for atsama5d3 */
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#define DRAM_BASE 0x20000000
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#define CS1_BASE 0x40000000
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#define CS2_BASE 0x50000000
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#define CS3_BASE 0x60000000
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#define NFC_CMD_BASE 0x70000000
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#define DRAM_BASE 0x20000000UL
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#define CS1_BASE 0x40000000UL
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#define CS2_BASE 0x50000000UL
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#define CS3_BASE 0x60000000UL
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#define NFC_CMD_BASE 0x70000000UL
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/* NAND flash is mapped to CS3 */
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#define NAND_BASE CS3_BASE
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@ -405,4 +427,22 @@ extern void *kernel_addr, *update_addr, *dts_addr;
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#define MAX_ECC_BYTES 8
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#endif
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#define GPIOE_BASE 0xFFFFFA00
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#define GPIOE_PER *(volatile uint32_t *)(GPIOE_BASE + 0x00)
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#define GPIOE_PDR *(volatile uint32_t *)(GPIOE_BASE + 0x04)
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#define GPIOE_PSR *(volatile uint32_t *)(GPIOE_BASE + 0x08)
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#define GPIOE_OER *(volatile uint32_t *)(GPIOE_BASE + 0x10)
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#define GPIOE_ODR *(volatile uint32_t *)(GPIOE_BASE + 0x14)
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#define GPIOE_OSR *(volatile uint32_t *)(GPIOE_BASE + 0x18)
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#define GPIOE_SODR *(volatile uint32_t *)(GPIOE_BASE + 0x30)
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#define GPIOE_CODR *(volatile uint32_t *)(GPIOE_BASE + 0x34)
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#define GPIOE_IER *(volatile uint32_t *)(GPIOE_BASE + 0x40)
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#define GPIOE_IDR *(volatile uint32_t *)(GPIOE_BASE + 0x44)
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#define GPIOE_MDER *(volatile uint32_t *)(GPIOE_BASE + 0x50)
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#define GPIOE_MDDR *(volatile uint32_t *)(GPIOE_BASE + 0x54)
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#define GPIOE_PPUDR *(volatile uint32_t *)(GPIOE_BASE + 0x60)
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#define GPIOE_PPUER *(volatile uint32_t *)(GPIOE_BASE + 0x64)
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#endif
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@ -2,7 +2,7 @@
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*
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* Test bare-metal boot application
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*
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* Copyright (C) 2021 wolfSSL Inc.
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* Copyright (C) 2024 wolfSSL Inc.
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*
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* This file is part of wolfBoot.
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*
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@ -24,29 +24,13 @@
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#include <stdlib.h>
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#include <stdint.h>
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#include <string.h>
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#include <hal/sama5d3.h>
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#include "wolfboot/wolfboot.h"
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#ifdef TARGET_sama5d3
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/* Blue LED is PE23, Red LED is PE24 */
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#define GPIOE_BASE 0xFFFFFA00
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#define GPIOE_PER *(volatile uint32_t *)(GPIOE_BASE + 0x00)
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#define GPIOE_PDR *(volatile uint32_t *)(GPIOE_BASE + 0x04)
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#define GPIOE_PSR *(volatile uint32_t *)(GPIOE_BASE + 0x08)
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#define GPIOE_OER *(volatile uint32_t *)(GPIOE_BASE + 0x10)
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#define GPIOE_ODR *(volatile uint32_t *)(GPIOE_BASE + 0x14)
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#define GPIOE_OSR *(volatile uint32_t *)(GPIOE_BASE + 0x18)
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#define GPIOE_SODR *(volatile uint32_t *)(GPIOE_BASE + 0x30)
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#define GPIOE_CODR *(volatile uint32_t *)(GPIOE_BASE + 0x34)
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#define GPIOE_IER *(volatile uint32_t *)(GPIOE_BASE + 0x40)
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#define GPIOE_IDR *(volatile uint32_t *)(GPIOE_BASE + 0x44)
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#define GPIOE_MDER *(volatile uint32_t *)(GPIOE_BASE + 0x50)
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#define GPIOE_MDDR *(volatile uint32_t *)(GPIOE_BASE + 0x54)
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#define GPIOE_PPUDR *(volatile uint32_t *)(GPIOE_BASE + 0x60)
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#define GPIOE_PPUER *(volatile uint32_t *)(GPIOE_BASE + 0x64)
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#define BLUE_LED_PIN 23
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#define RED_LED_PIN 24
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Loading…
Reference in New Issue