mirror of https://github.com/wolfSSL/wolfBoot.git
STM32H7 Test Program
This wolfBoot application has been specifically developed for and tested on NUCLEO-H753ZI. Toogle between application A and B to use the application code to test firmware update capability of wolfBoot and to distinguish the two application versions.pull/103/head
Benjamin Bruun
Daniele Lacamera
parent
3516620f1a
commit
cff0c54cc5
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@ -21,6 +21,15 @@
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
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*/
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/** ------------------------------------------------------------------------------------------------------------------------
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* WOLFBOOT APPLICATION FOR NUCLEO-H753ZI BOARD ONLY! |
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* |
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* The following application runs on the above mentioned board. |
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* It contains setup of LD1, LD2 and LD3. |
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* As well as setup of UART serial commmunication using USART2 on pins PD5 (TX) and PD6 (RX). |
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* ------------------------------------------------------------------------------------------------------------------------
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*/
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#include <stdio.h>
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#include <stdlib.h>
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#include <stdint.h>
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@ -29,68 +38,370 @@
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#include "hal.h"
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#include "wolfboot/wolfboot.h"
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#define SET_BIT(REG, BIT) ((REG) |= (BIT))
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#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
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#define READ_BIT(REG, BIT) ((REG) & (BIT))
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#define CLEAR_REG(REG) ((REG) = (0x00))
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#define WRITE_REG(REG, VAL) ((REG) = (VAL))
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#define READ_REG(REG) ((REG))
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#define UNUSED(x) ((void)(x))
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#define AHB4_CLOCK_ER (*(volatile uint32_t *)(0x580244E0))
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#define GPIOB_AHB4_CLOCK_ER (1 << 1)
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#define GPIOE_AHB4_CLOCK_ER (1 << 4)
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// ASSEMBLY HELPERS
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// ======================================================================
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// It ensures that all explicit memory accesses are observed.
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#ifndef DMB
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#define DMB() __asm__ volatile("dmb") // DMB: Data Memory Barrier
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#endif
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#ifndef ISB
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#define ISB() __asm__ volatile("isb") // ISB: Instruction Synchronization Barrier
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#endif
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#ifndef DSB
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#define DSB() __asm__ volatile("dsb") // DSB: Data Synchronization Barrier
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#endif
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// GENERAL DEFINITIONS
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// ======================================================================
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#define FIRMWARE_A 1
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#define FIRMWARE_B 0
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#define LED_OFF 0
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#define LED_INIT 1
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#define LED_ON 2
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// USER LED
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// ======================================================================
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// Defining LED pin numbers in the corresponding GPIO group
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#define LD1_PIN (0) // Nucleo LD1 - Green Led
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#define LD2_PIN (1) // Nucleo LD2 - Yellow Led
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#define LD3_PIN (14) // Nucleo LD3 - Red Led
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// GPIO GROUP B
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#define GPIOB_BASE 0x58020400
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#define GPIOE_BASE 0x58021000
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#define GPIOB_MODE (*(volatile uint32_t *)(GPIOB_BASE + 0x00))
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#define GPIOB_PUPD (*(volatile uint32_t *)(GPIOB_BASE + 0x0c))
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#define GPIOB_BSRR (*(volatile uint32_t *)(GPIOB_BASE + 0x18))
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#define GPIOB_AFL (*(volatile uint32_t *)(GPIOB_BASE + 0x20))
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#define GPIOB_AFH (*(volatile uint32_t *)(GPIOB_BASE + 0x24))
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#define GPIOB_AHB4_CLOCK_ER (1 << 1)
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// GPIO GROUP E
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#define GPIOE_BASE 0x58021000
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#define GPIOE_MODE (*(volatile uint32_t *)(GPIOE_BASE + 0x00))
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#define GPIOE_PUPD (*(volatile uint32_t *)(GPIOE_BASE + 0x0c))
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#define GPIOE_BSRR (*(volatile uint32_t *)(GPIOE_BASE + 0x18))
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#define GPIOE_AFL (*(volatile uint32_t *)(GPIOE_BASE + 0x20))
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#define GPIOE_AFH (*(volatile uint32_t *)(GPIOE_BASE + 0x24))
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#define GPIOE_AHB4_CLOCK_ER (1 << 4)
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// UART SETUP
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// ======================================================================
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// USART2 Base address (chosen because of its pin layout on Nucleo board)
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#define UART_BASE (0x40004400)
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#define RCC_BASE (0x58024400)
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#define GPIOD_BASE (0x58020C00)
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#define LED_BOOT_PIN (0) //PB0 - Nucleo LD1 - Green Led
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#define LED_USR_PIN (1) //PE1 - Nucleo LD2 - Yellow Led
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static void boot_led_on(void)
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#define UART_PIN_AF 7 // AF stands for Alternate Function. For PD5/PD6 AF7 equals USART2 RX/TX.
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#define UART_TX_PIN 5 // PD5, USART Transmit pin
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#define UART_RX_PIN 6 // PD6, USART Receive pin
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// UART/USART: Defining register start addresses.
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#define UART_CR1 (*(volatile uint32_t *)(UART_BASE + 0x00))
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#define UART_CR2 (*(volatile uint32_t *)(UART_BASE + 0x04))
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#define UART_BRR (*(volatile uint32_t *)(UART_BASE + 0x0C))
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#define UART_ISR (*(volatile uint32_t *)(UART_BASE + 0x1C))
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#define UART_RDR (*(volatile uint32_t *)(UART_BASE + 0x24))
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#define UART_TDR (*(volatile uint32_t *)(UART_BASE + 0x28))
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#define UART_RQR (*(volatile uint32_t *)(UART_BASE + 0x18))
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// RCC: Defining register start addresses.
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#define RCC_D2CCIP2R (*(volatile uint32_t *)(RCC_BASE + 0x54))
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#define RCC_AHB1ENR (*(volatile uint32_t *)(RCC_BASE + 0xD8))
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#define RCC_AHB4ENR (*(volatile uint32_t *)(RCC_BASE + 0xE0))
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#define RCC_APB1ENR (*(volatile uint32_t *)(RCC_BASE + 0xE8))
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#define RCC_APB2ENR (*(volatile uint32_t *)(RCC_BASE + 0xF0))
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// GPIO: Defining register start addresses.
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#define GPIOD_MODE (*(volatile uint32_t *)(GPIOD_BASE + 0x00))
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#define GPIOD_BSRR (*(volatile uint32_t *)(GPIOD_BASE + 0x18))
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#define GPIOD_AFRL (*(volatile uint32_t *)(GPIOD_BASE + 0x20))
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#define GPIOD_AFRH (*(volatile uint32_t *)(GPIOD_BASE + 0x24))
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// UART/USART: Defining register bit placement for CR1 and ISR register for readabilty.
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#define UART_CR1_UART_ENABLE (1 << 0)
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#define UART_CR1_TX_ENABLE (1 << 3)
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#define UART_CR1_RX_ENABLE (1 << 2)
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#define UART_CR1_SYMBOL_LEN (1 << 28)
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#define UART_CR1_PARITY_ENABLED (1 << 10)
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#define UART_CR1_PARITY_ODD (1 << 9)
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#define UART_ISR_TX_FIFO_NOT_FULL (1 << 7)
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#define UART_ISR_RX_FIFO_NOT_EMPTY (1 << 5)
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#define UART_ISR_TRANSMISSION_COMPLETE (1 << 6)
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#define UART_ISR_TX_DATA_REGISTER_EMPTY (1 << 7)
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// RCC: Defining register bit placement for APB1, APB2, AHB1 and AHB4 register for readabilty.
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#define RCC_APB1_USART2_EN (1 << 17)
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#define RCC_APB1_USART3_EN (1 << 18)
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#define RCC_APB1_UART4_EN (1 << 19)
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#define RCC_APB1_UART5_EN (1 << 20)
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#define RCC_APB1_UART7_EN (1 << 30)
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#define RCC_APB1_UART8_EN (1 << 31)
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#define RCC_APB2_USART1_EN (1 << 4)
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#define RCC_APB2_USART6_EN (1 << 5)
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#define RCC_AHB1_DMA1_EN (1 << 0)
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#define RCC_AHB1_DMA2_EN (1 << 1)
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#define RCC_AHB4_GPIOD_EN (1 << 3)
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// HSI Clock speed
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#define CLOCK_SPEED 64000000
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// Marking the update partition as ready to be swapped and executed.
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#define UPDATE_PARTITION_BASE (0x08060000)
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// The four character is expected to write: W O L F (0x57 0x4F 0x4C 0x46)
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// Character = W. Hex = 57. BIN = 0101 0111, DEC = 87
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#define UPDATE_CHARACTER_1 (*(volatile uint32_t *)(UPDATE_PARTITION_BASE + 0x00))
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// Character = O. Hex = 4F. BIN = 0100 1111
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#define UPDATE_CHARACTER_2 (*(volatile uint32_t *)(UPDATE_PARTITION_BASE + 0x01))
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// Character = L. Hex = 4C. BIN = 0100 1100
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#define UPDATE_CHARACTER_3 (*(volatile uint32_t *)(UPDATE_PARTITION_BASE + 0x02))
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// Character = F. Hex = 46. BIN = 0100 0110
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#define UPDATE_CHARACTER_4 (*(volatile uint32_t *)(UPDATE_PARTITION_BASE + 0x03))
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// Marking the update partition as ready to be swapped and executed.
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#define UPDATE_PARTITION_MAGIC_BASE (0x0809FFFC)
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#define UPDATE_MAGIC_1 (*(volatile uint32_t *)(UPDATE_PARTITION_MAGIC_BASE + 0x00))
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#define UPDATE_MAGIC_2 (*(volatile uint32_t *)(UPDATE_PARTITION_MAGIC_BASE + 0x01))
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#define UPDATE_MAGIC_3 (*(volatile uint32_t *)(UPDATE_PARTITION_MAGIC_BASE + 0x02))
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#define UPDATE_MAGIC_4 (*(volatile uint32_t *)(UPDATE_PARTITION_MAGIC_BASE + 0x03))
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static void ld1_write(uint8_t led_status)
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{
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if (led_status == 0)
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{
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SET_BIT(GPIOB_BSRR, (1 << (LD1_PIN + 16)));
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}
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else if (led_status == 2)
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{
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SET_BIT(GPIOB_BSRR, (1 << LD1_PIN));
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}
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else if (led_status == 1)
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{
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uint32_t reg;
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uint32_t pin = LED_BOOT_PIN;
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AHB4_CLOCK_ER |= GPIOB_AHB4_CLOCK_ER;
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uint32_t pin = LD1_PIN;
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SET_BIT(RCC_AHB4ENR, GPIOB_AHB4_CLOCK_ER);
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reg = GPIOB_MODE & ~(0x03 << (pin * 2));
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GPIOB_MODE = reg | (1 << (pin * 2));
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reg = GPIOB_PUPD & ~(0x03 << (pin * 2));
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GPIOB_PUPD = reg | (1 << (pin * 2));
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GPIOB_BSRR |= (1 << pin);
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}
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}
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static void boot_led_off(void)
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{
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GPIOB_BSRR |= (1 << (LED_BOOT_PIN + 16));
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}
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void usr_led_on(void)
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static void ld2_write(uint8_t led_status)
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{
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if (led_status == 0)
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{
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GPIOE_BSRR |= (1 << (LD2_PIN + 16));
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}
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else if (led_status == 2)
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{
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SET_BIT(GPIOE_BSRR, (1 << LD2_PIN));
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}
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else if (led_status == 1)
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{
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uint32_t reg;
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uint32_t pin = LED_USR_PIN;
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AHB4_CLOCK_ER |= GPIOE_AHB4_CLOCK_ER;
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uint32_t pin = LD2_PIN;
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RCC_AHB4ENR |= GPIOE_AHB4_CLOCK_ER;
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reg = GPIOE_MODE & ~(0x03 << (pin * 2));
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GPIOE_MODE = reg | (1 << (pin * 2));
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reg = GPIOE_PUPD & ~(0x03 << (pin * 2));
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GPIOE_PUPD = reg | (1 << (pin * 2));
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GPIOE_BSRR |= (1 << pin);
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}
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}
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void usr_led_off(void)
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static void ld3_write(uint8_t led_status)
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{
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GPIOE_BSRR |= (1 << (LED_USR_PIN + 16));
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if (led_status == 0)
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{
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GPIOB_BSRR |= (1 << (LD3_PIN + 16));
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}
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else if (led_status == 2)
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{
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SET_BIT(GPIOB_BSRR, (1 << LD3_PIN));
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}
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else if (led_status == 1)
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{
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uint32_t reg;
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uint32_t pin = LD3_PIN;
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RCC_AHB4ENR |= GPIOB_AHB4_CLOCK_ER;
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reg = GPIOB_MODE & ~(0x03 << (pin * 2));
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GPIOB_MODE = reg | (1 << (pin * 2));
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reg = GPIOB_PUPD & ~(0x03 << (pin * 2));
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GPIOB_PUPD = reg | (1 << (pin * 2));
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GPIOB_BSRR |= (1 << pin);
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}
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}
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int uart_setup(uint32_t bitrate)
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{
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uint32_t reg;
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if ((bitrate != 9600) && (bitrate != 115200))
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return -1; // Bitrate not accepted
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// Enable UART pins
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SET_BIT(RCC_AHB4ENR, RCC_AHB4_GPIOD_EN);
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// Set mode = AF. The PORT D I/O pin is first reset and then set to AF (bit config 10:Alternate function mode)
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reg = GPIOD_MODE & ~(0x03 << (UART_TX_PIN * 2));
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GPIOD_MODE = reg | (2 << (UART_TX_PIN * 2));
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reg = GPIOD_MODE & ~(0x03 << (UART_RX_PIN * 2));
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GPIOD_MODE = reg | (2 << (UART_RX_PIN * 2));
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// Alternate function. Use AFLR for pins 0-7 and AFHR for pins 8-15
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reg = GPIOD_AFRL & ~(0xf << ((UART_TX_PIN)*4));
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GPIOD_AFRL = reg | (UART_PIN_AF << ((UART_TX_PIN)*4));
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reg = GPIOD_AFRL & ~(0xf << ((UART_RX_PIN)*4));
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GPIOD_AFRL = reg | (UART_PIN_AF << ((UART_RX_PIN)*4));
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// Disable UART to enable settings to be written into the registers.
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if (READ_BIT(UART_CR1, UART_CR1_UART_ENABLE) == 1)
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{
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CLEAR_BIT(UART_CR1, UART_CR1_UART_ENABLE);
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}
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// Set general UART clock source (all uarts but nr 1 and 6). 011 = HSI Clock Source
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SET_BIT(RCC_D2CCIP2R, (1 << 0));
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SET_BIT(RCC_D2CCIP2R, (1 << 1));
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CLEAR_BIT(RCC_D2CCIP2R, (1 << 2));
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// Enable clock for USART_2
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SET_BIT(RCC_APB1ENR, RCC_APB1_USART2_EN);
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// Enable FIFO mode
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SET_BIT(UART_CR1, (1 << 29));
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// Configure the M bits (word length)
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CLEAR_BIT(UART_CR1, (1 << 28)); // Word length is 8 bits by default
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CLEAR_BIT(UART_CR1, (1 << 12)); // Word length is 8 bits by default
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// Configure clock (speed/bitrate). Requires UE = 0.
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WRITE_REG(UART_BRR, (CLOCK_SPEED / bitrate));
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// Configure stop bits (00: 1 stop bit / 10: 2 stop bits.)
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CLEAR_BIT(UART_CR2, (1 << 12));
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CLEAR_BIT(UART_CR2, (1 << 13));
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// Set the TE bit in USART_CR1 to send an idle frame as first transmission.
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SET_BIT(UART_CR1, UART_CR1_TX_ENABLE);
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SET_BIT(UART_CR1, UART_CR1_RX_ENABLE);
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// Configure parity bits, disabled
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CLEAR_BIT(UART_CR1, UART_CR1_PARITY_ENABLED);
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CLEAR_BIT(UART_CR1, UART_CR1_PARITY_ODD);
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ISB();
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DSB();
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// Turn on UART. USART_CR1 Register, Bit 0.
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SET_BIT(UART_CR1, UART_CR1_UART_ENABLE);
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if (READ_BIT(UART_CR1, UART_CR1_UART_ENABLE) == 1)
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return 0;
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else
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return -1;
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}
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void uart_write(const char c)
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{
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// USART transmit data register(TDR), bit 0-8 contains the data character to be transmitted.
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// The register mus be written only when TXE/TXFNF = 1;
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// TXE : Set by hardware when the content of the USART_TDR register has been transferred
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// into the shift register.
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// TXFNF : Set by hardware when TXFIFO is not full meaning that data can be written
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// in the USART_TDR.
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while (READ_BIT(UART_CR1, UART_CR1_TX_ENABLE) == 0)
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;
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while (READ_BIT(UART_ISR, UART_ISR_TX_FIFO_NOT_FULL) == 0)
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;
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UART_TDR = c;
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}
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void uart_print(const char *s)
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{
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int i = 0;
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while (s[i])
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{
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uart_write(s[i++]);
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}
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}
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void main(void)
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{
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uint8_t firmware_version = 0;
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hal_init();
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boot_led_on();
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usr_led_on();
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boot_led_off();
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// LED Indicator of Firmware Type A/B. A = ON, B = OFF
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if (FIRMWARE_A)
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ld3_write(LED_INIT);
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// LED Indicator of successful UART initialization. SUCCESS = ON, FAIL = OFF
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if (uart_setup(9600) < 0)
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ld2_write(LED_OFF);
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else
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ld2_write(LED_INIT);
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firmware_version = wolfBoot_current_firmware_version(); // The same as: wolfBoot_get_image_version(PART_BOOT);
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// LED Indicator of version number lower than 1.
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if (firmware_version <= 0)
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ld1_write(LED_OFF);
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else
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ld1_write(LED_INIT);
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uart_print(" \n\r");
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uart_print("| ------------------------------------------------------------------- |\n\r");
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uart_print("| STM32H753 User Application in BOOT partition started by wolfBoot |\n\r");
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uart_print("| ------------------------------------------------------------------- |\n\n\r");
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if (FIRMWARE_A)
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uart_print("\tUSER APPLICATION: A\n\n\r");
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if (FIRMWARE_B)
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uart_print("\tUSER APPLICATION: B\n\n\r");
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uart_print("\tFIRMWARE VERSION: ");
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if (firmware_version <= 9)
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{
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uart_write(firmware_version + '0');
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uart_print(" \n\n\r");
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}
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else
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uart_print("Version higher than 9, extend print method!\n\n\r");
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if ((firmware_version > 1) && FIRMWARE_B)
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{
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uart_print("[INFO] Executing API function call wolfBoot_success()\n\r");
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wolfBoot_success();
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uart_print("[INFO] BOOT partition marked with: IMG_STATE_SUCCESS\n\r");
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}
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char char_temp = READ_REG(UPDATE_CHARACTER_1);
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uart_print("[DATA] Content of 0x08060000 (1 byte): ");
|
||||
uart_write(char_temp);
|
||||
uart_print("\n\r");
|
||||
|
||||
if ((char_temp == 'W') && FIRMWARE_A)
|
||||
{
|
||||
uart_print("[INFO] Executing API function call wolfBoot_update_trigger()\n\r");
|
||||
wolfBoot_update_trigger();
|
||||
while(1)
|
||||
}
|
||||
else if (FIRMWARE_B)
|
||||
uart_print("[INFO] User application B is running and update cannot be triggered\n\r");
|
||||
|
||||
while (1)
|
||||
;
|
||||
}
|
||||
Loading…
Reference in New Issue