mirror of https://github.com/wolfSSL/wolfBoot.git
Add support for the RT1050 HyperFlash configuration (default on EVKB).
David Garske
Daniele Lacamera
parent
7073bf33b4
commit
d223b34319
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@ -1053,7 +1053,7 @@ DCP support (hardware acceleration for SHA256 operations) can be enabled by usin
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Firmware can be directly uploaded to the target by copying `factory.bin` to the virtual USB drive associated to the device, or by loading the image directly into flash using a JTAG/SWD debugger.
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For the RT1050 board it comes wired to use the HyperFlash, but wolfBoot is setup for QSPI. There is a rework that can be performed (see AN12183) to use the onboard 8MB ISSI IS25WP064A. Optionally you can define `CONFIG_FLASH_W25Q64JV` for the Winbond W25Q64JV.
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The RT1050 EVKB board comes wired to use the 64MB HyperFlash. If you'd like to use QSPI there is a rework that can be performed (see AN12183). The default onboard QSPI 8MB ISSI IS25WP064A (`CONFIG_FLASH_IS25WP064A`). To use a Winbond W25Q64JV define `CONFIG_FLASH_W25Q64JV`.
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### Testing Update
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156
hal/imx_rt.c
156
hal/imx_rt.c
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@ -276,6 +276,153 @@ const flexspi_nor_config_t __attribute__((section(".flash_config"))) qspiflash_c
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/** Flash configuration in the .flash_config section of flash **/
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#ifdef CPU_MIMXRT1052DVJ6B
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#ifdef CONFIG_FLASH_W25Q64JV
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/* Winbond W25Q64JV */
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#define WRITE_STATUS_CMD 0x31
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#define QE_ENABLE 0x02 /* S9 */
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#elif defined(CONFIG_FLASH_IS25WP064A)
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/* ISSI IS25WP064A (on EVKB with rework see AN12183) */
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#define WRITE_STATUS_CMD 0x1
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#define QE_ENABLE 0x40 /* S6 */
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#else
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/* Hyperflash - Default on RT1050-EVKB */
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#define CONFIG_HYPERFLASH
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#endif
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#ifdef CONFIG_HYPERFLASH
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#define CONFIG_FLASH_SIZE (64 * 1024 * 1024) /* 64MBytes */
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#define CONFIG_FLASH_PAGE_SIZE 512UL /* 512Bytes */
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#define CONFIG_FLASH_SECTOR_SIZE (256 * 1024) /* 256KBytes */
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#define CONFIG_FLASH_BLOCK_SIZE (256 * 1024) /* 256KBytes */
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#define CONFIG_FLASH_UNIFORM_BLOCKSIZE true
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#define CONFIG_SERIAL_CLK_FREQ kFlexSpiSerialClk_133MHz
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const flexspi_nor_config_t __attribute__((section(".flash_config"))) qspiflash_config = {
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.memConfig = {
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.tag = FLEXSPI_CFG_BLK_TAG,
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.version = FLEXSPI_CFG_BLK_VERSION,
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.readSampleClkSrc = kFlexSPIReadSampleClk_ExternalInputFromDqsPad,
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.csHoldTime = 3u,
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.csSetupTime = 3u,
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.columnAddressWidth = 3u,
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/* Enable DDR mode, Word-addressable, Safe configuration, Differential clock */
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.controllerMiscOption =
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(1u << kFlexSpiMiscOffset_DdrModeEnable) | (1u << kFlexSpiMiscOffset_WordAddressableEnable) |
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(1u << kFlexSpiMiscOffset_SafeConfigFreqEnable) | (1u << kFlexSpiMiscOffset_DiffClkEnable),
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.deviceType = kFlexSpiDeviceType_SerialNOR,
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.sflashPadType = kSerialFlash_8Pads,
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.serialClkFreq = CONFIG_SERIAL_CLK_FREQ,
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.lutCustomSeqEnable = 0x1,
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.sflashA1Size = CONFIG_FLASH_SIZE,
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.dataValidTime = {15u, 0u},
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.busyOffset = 15u,
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.busyBitPolarity = 1u,
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.lookupTable = {
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/* Read LUTs */
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[0] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0xA0, RADDR_DDR, FLEXSPI_8PAD, 0x18),
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[1] = FLEXSPI_LUT_SEQ(CADDR_DDR, FLEXSPI_8PAD, 0x10, DUMMY_DDR, FLEXSPI_8PAD, 0x0C),
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[2] = FLEXSPI_LUT_SEQ(READ_DDR, FLEXSPI_8PAD, 0x04, STOP, FLEXSPI_1PAD, 0x0),
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/* Read Status LUTs - 0 */
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[4 * 1 + 0] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0x0, CMD_DDR, FLEXSPI_8PAD, 0x0),
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[4 * 1 + 1] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0x0, CMD_DDR, FLEXSPI_8PAD, 0xAA),
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[4 * 1 + 2] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0x0, CMD_DDR, FLEXSPI_8PAD, 0x05),
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[4 * 1 + 3] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0x0, CMD_DDR, FLEXSPI_8PAD, 0x70),
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/* Read Status LUTs - 1 */
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[4 * 2 + 0] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0xA0, RADDR_DDR, FLEXSPI_8PAD, 0x18),
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[4 * 2 + 1] = FLEXSPI_LUT_SEQ(CADDR_DDR, FLEXSPI_8PAD, 0x10, DUMMY_RWDS_DDR, FLEXSPI_8PAD, 0x0B),
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[4 * 2 + 2] = FLEXSPI_LUT_SEQ(READ_DDR, FLEXSPI_8PAD, 0x4, STOP, FLEXSPI_1PAD, 0x0),
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/* Write Enable LUTs - 0 */
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[4 * 3 + 0] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0x0, CMD_DDR, FLEXSPI_8PAD, 0x0),
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[4 * 3 + 1] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0x0, CMD_DDR, FLEXSPI_8PAD, 0xAA),
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[4 * 3 + 2] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0x0, CMD_DDR, FLEXSPI_8PAD, 0x05),
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[4 * 3 + 3] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0x0, CMD_DDR, FLEXSPI_8PAD, 0xAA),
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/* Write Enable LUTs - 1 */
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[4 * 4 + 0] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0x0, CMD_DDR, FLEXSPI_8PAD, 0x0),
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[4 * 4 + 1] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0x0, CMD_DDR, FLEXSPI_8PAD, 0x55),
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[4 * 4 + 2] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0x0, CMD_DDR, FLEXSPI_8PAD, 0x02),
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[4 * 4 + 3] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0x0, CMD_DDR, FLEXSPI_8PAD, 0x55),
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/* Erase Sector LUTs - 0 */
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[4 * 5 + 0] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0x0, CMD_DDR, FLEXSPI_8PAD, 0x0),
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[4 * 5 + 1] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0x0, CMD_DDR, FLEXSPI_8PAD, 0xAA),
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[4 * 5 + 2] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0x0, CMD_DDR, FLEXSPI_8PAD, 0x05),
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[4 * 5 + 3] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0x0, CMD_DDR, FLEXSPI_8PAD, 0x80),
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/* Erase Sector LUTs - 1 */
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[4 * 6 + 0] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0x0, CMD_DDR, FLEXSPI_8PAD, 0x0),
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[4 * 6 + 1] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0x0, CMD_DDR, FLEXSPI_8PAD, 0xAA),
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[4 * 6 + 2] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0x0, CMD_DDR, FLEXSPI_8PAD, 0x05),
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[4 * 6 + 3] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0x0, CMD_DDR, FLEXSPI_8PAD, 0xAA),
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/* Erase Sector LUTs - 2 */
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[4 * 7 + 0] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0x0, CMD_DDR, FLEXSPI_8PAD, 0x0),
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[4 * 7 + 1] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0x0, CMD_DDR, FLEXSPI_8PAD, 0x55),
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[4 * 7 + 2] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0x0, CMD_DDR, FLEXSPI_8PAD, 0x02),
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[4 * 7 + 3] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0x0, CMD_DDR, FLEXSPI_8PAD, 0x55),
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/* Erase Sector LUTs - 3 */
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[4 * 8 + 0] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0x0, RADDR_DDR, FLEXSPI_8PAD, 0x18),
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[4 * 8 + 1] = FLEXSPI_LUT_SEQ(CADDR_DDR, FLEXSPI_8PAD, 0x10, CMD_DDR, FLEXSPI_8PAD, 0x0),
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[4 * 8 + 2] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0x30, STOP, FLEXSPI_1PAD, 0x0),
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/* Page Program LUTs - 0 */
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[4 * 9 + 0] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0x0, CMD_DDR, FLEXSPI_8PAD, 0x0),
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[4 * 9 + 1] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0x0, CMD_DDR, FLEXSPI_8PAD, 0xAA),
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[4 * 9 + 2] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0x0, CMD_DDR, FLEXSPI_8PAD, 0x05),
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[4 * 9 + 3] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0x0, CMD_DDR, FLEXSPI_8PAD, 0xA0),
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/* Page Program LUTs - 1 */
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[4 * 10 + 0] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0x0, RADDR_DDR, FLEXSPI_8PAD, 0x18),
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[4 * 10 + 1] = FLEXSPI_LUT_SEQ(CADDR_DDR, FLEXSPI_8PAD, 0x10, WRITE_DDR, FLEXSPI_8PAD, 0x80),
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/* Erase Chip LUTs - 0 */
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[4 * 11 + 0] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0x0, CMD_DDR, FLEXSPI_8PAD, 0x0),
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[4 * 11 + 1] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0x0, CMD_DDR, FLEXSPI_8PAD, 0xAA),
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[4 * 11 + 2] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0x0, CMD_DDR, FLEXSPI_8PAD, 0x05),
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[4 * 11 + 3] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0x0, CMD_DDR, FLEXSPI_8PAD, 0x80),
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/* Erase Chip LUTs - 1 */
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[4 * 12 + 0] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0x0, CMD_DDR, FLEXSPI_8PAD, 0x0),
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[4 * 12 + 1] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0x0, CMD_DDR, FLEXSPI_8PAD, 0xAA),
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[4 * 12 + 2] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0x0, CMD_DDR, FLEXSPI_8PAD, 0x05),
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[4 * 12 + 3] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0x0, CMD_DDR, FLEXSPI_8PAD, 0xAA),
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/* Erase Chip LUTs - 2 */
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[4 * 13 + 0] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0x0, CMD_DDR, FLEXSPI_8PAD, 0x0),
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[4 * 13 + 1] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0x0, CMD_DDR, FLEXSPI_8PAD, 0x55),
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[4 * 13 + 2] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0x0, CMD_DDR, FLEXSPI_8PAD, 0x02),
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[4 * 13 + 3] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0x0, CMD_DDR, FLEXSPI_8PAD, 0x55),
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/* Erase Chip LUTs - 3 */
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[4 * 14 + 0] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0x0, CMD_DDR, FLEXSPI_8PAD, 0x0),
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[4 * 14 + 1] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0x0, CMD_DDR, FLEXSPI_8PAD, 0xAA),
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[4 * 14 + 2] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0x0, CMD_DDR, FLEXSPI_8PAD, 0x05),
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[4 * 14 + 3] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0x0, CMD_DDR, FLEXSPI_8PAD, 0x10),
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},
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/* LUT customized sequence */
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.lutCustomSeq = {
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{.seqNum = 0, .seqId = 0, .reserved = 0},
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{.seqNum = 2, .seqId = 1, .reserved = 0},
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{.seqNum = 2, .seqId = 3, .reserved = 0},
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{.seqNum = 4, .seqId = 5, .reserved = 0},
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{.seqNum = 2, .seqId = 9, .reserved = 0},
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{.seqNum = 4, .seqId = 11, .reserved = 0}
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},
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},
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.pageSize = CONFIG_FLASH_PAGE_SIZE,
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.sectorSize = CONFIG_FLASH_SECTOR_SIZE,
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.ipcmdSerialClkFreq = 1u,
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.serialNorType = 1u,
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.blockSize = CONFIG_FLASH_BLOCK_SIZE,
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.isUniformBlockSize = CONFIG_FLASH_UNIFORM_BLOCKSIZE,
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};
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#else /* QSPI */
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#define CONFIG_FLASH_SIZE (8 * 1024 * 1024) /* 8MBytes */
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#define CONFIG_FLASH_PAGE_SIZE 256UL /* 256Bytes */
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#define CONFIG_FLASH_SECTOR_SIZE (4 * 1024) /* 4Bytes */
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@ -285,14 +432,6 @@ const flexspi_nor_config_t __attribute__((section(".flash_config"))) qspiflash_c
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#define CONFIG_FLASH_ADDR_WIDTH 24u /* Width of flash addresses (either 24 or 32) */
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#define CONFIG_FLASH_QE_ENABLE 1
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#ifdef CONFIG_FLASH_W25Q64JV /* Winbond W25Q64JV */
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#define WRITE_STATUS_CMD 0x31
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#define QE_ENABLE 0x02 /* S9 */
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#else /* Default - ISSI IS25WP064A (on EVKB) */
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#define WRITE_STATUS_CMD 0x1
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#define QE_ENABLE 0x40 /* S6 */
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#endif
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/* Note: By default the RT1050-EVKB uses HyperFlex.
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* To use QSPI flash a rework is required. See AN12183
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*/
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@ -401,6 +540,7 @@ const flexspi_nor_config_t __attribute__((section(".flash_config"))) qspiflash_c
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.isUniformBlockSize = CONFIG_FLASH_UNIFORM_BLOCKSIZE,
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.ipcmdSerialClkFreq = 0,
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};
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#endif
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#endif /* CPU_MIMXRT1052DVJ6B */
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#ifndef __FLASH_BASE
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