diff --git a/docs/Targets.md b/docs/Targets.md
index ee658ac6..9daec6ce 100644
--- a/docs/Targets.md
+++ b/docs/Targets.md
@@ -8542,9 +8542,9 @@ as well as the MAX32666FTHR2 board with the onboard debugger.
 - 1MB Flash: 8KB page erase, 128-bit (16-byte) write unit, dual-bank (FLC0/FLC1)
 - 560KB SRAM
 - Bare-metal implementation (no MSDK required for boot)
-- UART0 debug output:
-  - P1.13 TX, P1.12 RX on FTHR board
-  - P0.9 TX, P0.10 RX on FTHR2 board
+- UART debug output (115200 8N1):
+  - FTHR board: UART1 MAP_B, P1.13 TX, P1.12 RX (via external MAX32625PICO)
+  - FTHR2 board: UART0 MAP_A, P0.9 TX, P0.10 RX (via onboard debugger)
 
 ### MAX32666: Memory Layout
 
diff --git a/hal/max32666.c b/hal/max32666.c
index adce76f6..a2acf4c2 100644
--- a/hal/max32666.c
+++ b/hal/max32666.c
@@ -116,10 +116,6 @@ static void RAMFUNCTION icc_enable(void)
 
 static void RAMFUNCTION flc_unlock(volatile uint32_t *flc_base)
 {
-    FLC_REG(flc_base, FLC_ACNTL_OFF) = FLC_ACNTL_UNLOCK_KEY1;
-    FLC_REG(flc_base, FLC_ACNTL_OFF) = FLC_ACNTL_UNLOCK_KEY2;
-
-    /* Set unlock bits in CN register */
     FLC_REG(flc_base, FLC_CN_OFF) =
         (FLC_REG(flc_base, FLC_CN_OFF) & ~FLC_CN_UNLOCK_MASK) |
         FLC_CN_UNLOCK_UNLOCKED;
@@ -127,7 +123,9 @@ static void RAMFUNCTION flc_unlock(volatile uint32_t *flc_base)
 
 static void RAMFUNCTION flc_lock(volatile uint32_t *flc_base)
 {
-    FLC_REG(flc_base, FLC_ACNTL_OFF) = 0;
+    FLC_REG(flc_base, FLC_CN_OFF) =
+        (FLC_REG(flc_base, FLC_CN_OFF) & ~FLC_CN_UNLOCK_MASK) |
+        FLC_CN_UNLOCK_LOCKED;
 }
 
 static void RAMFUNCTION flc_wait_done(volatile uint32_t *flc_base)
diff --git a/hal/max32666.h b/hal/max32666.h
index 31efb1f5..94f1d734 100644
--- a/hal/max32666.h
+++ b/hal/max32666.h
@@ -120,21 +120,18 @@
 #define FLC_CN_OFF              0x08UL
 #define FLC_INTR_OFF            0x024UL
 #define FLC_DATA_OFF            0x030UL     /* DATA[0..3] = 128-bit write data */
-#define FLC_ACNTL_OFF           0x040UL
 
 /* FLC0 registers */
 #define FLC0_ADDR               (*(volatile uint32_t *)(FLC0_BASE + FLC_ADDR_OFF))
 #define FLC0_CLKDIV             (*(volatile uint32_t *)(FLC0_BASE + FLC_CLKDIV_OFF))
 #define FLC0_CN                 (*(volatile uint32_t *)(FLC0_BASE + FLC_CN_OFF))
 #define FLC0_INTR               (*(volatile uint32_t *)(FLC0_BASE + FLC_INTR_OFF))
-#define FLC0_ACNTL              (*(volatile uint32_t *)(FLC0_BASE + FLC_ACNTL_OFF))
 
 /* FLC1 registers */
 #define FLC1_ADDR               (*(volatile uint32_t *)(FLC1_BASE + FLC_ADDR_OFF))
 #define FLC1_CLKDIV             (*(volatile uint32_t *)(FLC1_BASE + FLC_CLKDIV_OFF))
 #define FLC1_CN                 (*(volatile uint32_t *)(FLC1_BASE + FLC_CN_OFF))
 #define FLC1_INTR               (*(volatile uint32_t *)(FLC1_BASE + FLC_INTR_OFF))
-#define FLC1_ACNTL              (*(volatile uint32_t *)(FLC1_BASE + FLC_ACNTL_OFF))
 
 /* FLC_CN (Control) register bits */
 #define FLC_CN_WR               (1UL << 0)          /* Start write */
@@ -156,10 +153,6 @@
 #define FLC_INTR_DONEIE         (1UL << 8)          /* Done interrupt enable */
 #define FLC_INTR_AFIE           (1UL << 9)          /* Fault interrupt enable */
 
-/* FLC unlock sequence (ACNTL register) */
-#define FLC_ACNTL_UNLOCK_KEY1   0x3A7F5200UL
-#define FLC_ACNTL_UNLOCK_KEY2   0xA1E34F20UL
-
 /* FLC clock divider: flash requires 1 MHz clock
  * CLKDIV = SystemClock / 1MHz
  * At 96 MHz: CLKDIV = 96
@@ -283,7 +276,7 @@
 
 /* Select debug UART instance
  * MAX32666FTHR  uses UART1 MAP_B (P1.12 RX, P1.13 TX) through external PICO
- * MAX32666FTHR2 uses UART0 MAP_A (P0.0 TX, P0.1 RX) through onboard DAPLINK
+ * MAX32666FTHR2 uses UART0 MAP_A (P0.9 TX, P0.10 RX) through onboard DAPLINK
  */
 #ifndef DEBUG_UART_NUM
 #ifdef MAX32666_FTHR2