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Merge pull request #59 from wolfSSL/stm32wb-hal-fixes 

Stm32wb hal fixes
psoc6_hwcrypto^2
David Garske 2020-06-15 07:01:50 -07:00 committed by GitHub
parent d7639517a1 b662f961c7
commit e5752249cb
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GPG Key ID: 4AEE18F83AFDEB23
2 changed files with 47 additions and 33 deletions
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78
hal/stm32wb.c
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@ -97,7 +97,8 @@ PKA_HandleTypeDef hpka = { };
#define FLASH_ACR_LATENCY_MASK (0x07)
#ifndef WOLFSSL_STM32_PKA
#define FLASH_SR_BSY (1 << 16)
#define FLASH_SR_BSY (1 << 16)
#define FLASH_SR_CFGBSY (1 << 18)
#define FLASH_SR_SIZERR (1 << 6)
#define FLASH_SR_PGAERR (1 << 5)
#define FLASH_SR_WRPERR (1 << 4)
@ -109,11 +110,12 @@ PKA_HandleTypeDef hpka = { };
#define FLASH_CR_PER (1 << 1)
#define FLASH_CR_PG (1 << 0)
#define FLASH_CR_FSTPG (1 << 18)
#endif /* !WOLFSSL_STM32_PKA */
#define FLASH_CR_PNB_SHIFT 3
#define FLASH_CR_PNB_MASK 0x3f
#define FLASH_CR_PNB_MASK 0xFF
#define FLASH_KEY1 (0x45670123)
#define FLASH_KEY2 (0xCDEF89AB)
@ -128,7 +130,7 @@ static void RAMFUNCTION flash_set_waitstates(unsigned int waitstates)
static RAMFUNCTION void flash_wait_complete(void)
{
while ((FLASH_SR & FLASH_SR_BSY) == FLASH_SR_BSY)
while ((FLASH_SR & (FLASH_SR_BSY | FLASH_SR_CFGBSY)) != 0)
;
}
@ -137,21 +139,50 @@ static void RAMFUNCTION flash_clear_errors(void)
FLASH_SR |= ( FLASH_SR_SIZERR | FLASH_SR_PGAERR | FLASH_SR_WRPERR | FLASH_SR_PROGERR);
}
void RAMFUNCTION hal_flash_unlock(void)
{
flash_wait_complete();
if ((FLASH_CR & FLASH_CR_LOCK) != 0) {
FLASH_KEY = FLASH_KEY1;
DMB();
FLASH_KEY = FLASH_KEY2;
DMB();
while ((FLASH_CR & FLASH_CR_LOCK) != 0)
;
}
}
void RAMFUNCTION hal_flash_lock(void)
{
flash_wait_complete();
if ((FLASH_CR & FLASH_CR_LOCK) == 0)
FLASH_CR |= FLASH_CR_LOCK;
}
int RAMFUNCTION hal_flash_write(uint32_t address, const uint8_t *data, int len)
{
int i = 0;
uint32_t *src, *dst;
uint32_t pdword[2] __attribute__((aligned(16)));
uint32_t reg;
flash_clear_errors();
FLASH_CR |= FLASH_CR_PG;
reg = FLASH_CR & (~FLASH_CR_FSTPG);
FLASH_CR = reg | FLASH_CR_PG;
while (i < len) {
flash_clear_errors();
if ((len - i > 3) && ((((address + i) & 0x07) == 0) && ((((uint32_t)data) + i) & 0x07) == 0)) {
uint32_t idx = i >> 2;
src = (uint32_t *)data;
dst = (uint32_t *)(address + FLASHMEM_ADDRESS_SPACE);
dst = (uint32_t *)(address);
pdword[0] = src[idx];
pdword[1] = src[idx + 1];
flash_wait_complete();
dst[i >> 2] = src[i >> 2];
dst[(i >> 2) + 1] = src[(i >> 2) + 1];
dst[idx] = pdword[0];
dst[idx + 1] = pdword[1];
flash_wait_complete();
i+=8;
} else {
@ -176,42 +207,26 @@ int RAMFUNCTION hal_flash_write(uint32_t address, const uint8_t *data, int len)
return 0;
}
void RAMFUNCTION hal_flash_unlock(void)
{
flash_wait_complete();
if ((FLASH_CR & FLASH_CR_LOCK) != 0) {
FLASH_KEY = FLASH_KEY1;
DMB();
FLASH_KEY = FLASH_KEY2;
DMB();
while ((FLASH_CR & FLASH_CR_LOCK) != 0)
;
}
}
void RAMFUNCTION hal_flash_lock(void)
{
flash_wait_complete();
if ((FLASH_CR & FLASH_CR_LOCK) == 0)
FLASH_CR |= FLASH_CR_LOCK;
}
int RAMFUNCTION hal_flash_erase(uint32_t address, int len)
{
int start = -1, end = -1;
uint32_t end_address;
uint32_t p;
if (len == 0)
return -1;
address -= FLASHMEM_ADDRESS_SPACE;
end_address = address + len - 1;
flash_wait_complete();
for (p = address; p < end_address; p += FLASH_PAGE_SIZE) {
uint32_t reg = FLASH_CR & (~(FLASH_CR_PNB_MASK << FLASH_CR_PNB_SHIFT));
FLASH_CR = reg | ((p >> 12) << FLASH_CR_PNB_SHIFT) | FLASH_CR_PER | FLASH_CR_PG;
uint32_t reg;
flash_clear_errors();
reg = FLASH_CR & ~((FLASH_CR_PNB_MASK << FLASH_CR_PNB_SHIFT) | FLASH_CR_FSTPG | FLASH_CR_PG);
FLASH_CR = reg | ((p >> 12) << FLASH_CR_PNB_SHIFT) | FLASH_CR_PER;
DMB();
FLASH_CR |= FLASH_CR_STRT;
DMB();
flash_wait_complete();
FLASH_CR &= ~(FLASH_CR_PER | FLASH_CR_PG);
FLASH_CR &= ~(FLASH_CR_PER);
}
return 0;
}
@ -310,7 +325,6 @@ void hal_prepare_boot(void)
#ifdef SPI_FLASH
spi_release();
#endif
hal_flash_lock();
clock_pll_off();
}

2
lib/wolfssl

@ -1 +1 @@
Subproject commit a104caef130ec58027f51d99b8254af83f5c744f
Subproject commit 02327aee290596777f48f2db982650ee835f3da6