From e88a7dcae3f7e42f3c7af85a8cb695ee17deeace Mon Sep 17 00:00:00 2001 From: David Garske Date: Wed, 14 Dec 2022 13:14:33 -0800 Subject: [PATCH] Progress on DDR support for QorIQ. Refactor the platform to use "nxp_". --- arch.mk | 2 +- ..._68ppc2.config => nxp-t2080-68ppc2.config} | 2 +- .../{t2080.config => nxp-t2080.config} | 2 +- docs/Targets.md | 20 +- hal/{t2080.c => nxp_t2080.c} | 182 ++++++++++++++---- hal/{t2080.ld => nxp_t2080.ld} | 4 +- src/boot_ppc.c | 10 + src/boot_ppc_start.S | 3 - test-app/{app_t2080.c => app_nxp_t2080.c} | 4 +- 9 files changed, 176 insertions(+), 53 deletions(-) rename config/examples/{t2080_68ppc2.config => nxp-t2080-68ppc2.config} (98%) rename config/examples/{t2080.config => nxp-t2080.config} (97%) rename hal/{t2080.c => nxp_t2080.c} (83%) rename hal/{t2080.ld => nxp_t2080.ld} (91%) rename test-app/{app_t2080.c => app_nxp_t2080.c} (98%) diff --git a/arch.mk b/arch.mk index 42731f00..36d7b6bd 100644 --- a/arch.mk +++ b/arch.mk @@ -258,7 +258,7 @@ ifeq ($(ARCH),ARM_BE) endif endif -ifeq ($(TARGET),t2080) +ifeq ($(TARGET),nxp_t2080) # Power PC big endian ARCH_FLAGS=-m32 -mhard-float -mcpu=e6500 CFLAGS+=$(ARCH_FLAGS) -DBIG_ENDIAN_ORDER diff --git a/config/examples/t2080_68ppc2.config b/config/examples/nxp-t2080-68ppc2.config similarity index 98% rename from config/examples/t2080_68ppc2.config rename to config/examples/nxp-t2080-68ppc2.config index bea5ebe8..af634341 100644 --- a/config/examples/t2080_68ppc2.config +++ b/config/examples/nxp-t2080-68ppc2.config @@ -1,7 +1,7 @@ # NAII 68PPC2 NXP T2080 wolfBoot Configuration Template ARCH=PPC -TARGET=t2080 +TARGET=nxp_t2080 SIGN?=ECC384 HASH?=SHA384 IMAGE_HEADER_SIZE?=512 diff --git a/config/examples/t2080.config b/config/examples/nxp-t2080.config similarity index 97% rename from config/examples/t2080.config rename to config/examples/nxp-t2080.config index 6ef81fb7..a84f49af 100644 --- a/config/examples/t2080.config +++ b/config/examples/nxp-t2080.config @@ -1,5 +1,5 @@ ARCH=PPC -TARGET=t2080 +TARGET=nxp_t2080 SIGN?=ED25519 HASH?=SHA256 DEBUG?=1 diff --git a/docs/Targets.md b/docs/Targets.md index 78acbe8b..262ef380 100644 --- a/docs/Targets.md +++ b/docs/Targets.md @@ -1042,8 +1042,8 @@ WOLFBOOT_PARTITION_SWAP_ADDRESS?=0xff000 The NXP QorIQ T2080 is a PPC e6500 based processor. Support has been tested with the NAII 68PPC2. Example configurations for this target are provided in: -* NXP T2080: [/config/examples/t2080.config](/config/examples/t2080.config). -* NAII 68PPC2: [/config/examples/t2080_68ppc2.config](/config/examples/t2080_68ppc2.config). +* NXP T2080: [/config/examples/nxp-t2080.config](/config/examples/nxp-t2080.config). +* NAII 68PPC2: [/config/examples/nxp-t2080-68ppc2.config](/config/examples/nxp-t2080-68ppc2.config). ### Design NXP T2080 PPC @@ -1062,7 +1062,7 @@ By default wolfBoot will use `powerpc-linux-gnu-` cross-compiler prefix. These t The `make` creates a `factory.bin` image that can be programmed at `0xE8080000` ``` -cp ./config/examples/t2080_68ppc2.config .config +cp ./config/examples/nxp-t2080-68ppc2.config .config make clean make keytools make @@ -1110,9 +1110,21 @@ Example Boot Debug Output: ``` wolfBoot Init Part: Active 0, Address E8080000 -Part: Size 1028 +Image size 1028 Firmware Valid Loading 1028 bytes to RAM at 19000 +Failed parsing DTB to load. +Booting at 19000 +Test App + +0x00000001 +0x00000002 +0x00000003 +0x00000004 +0x00000005 +0x00000006 +0x00000007 +... ``` #### Flash Programming with Lauterbach diff --git a/hal/t2080.c b/hal/nxp_t2080.c similarity index 83% rename from hal/t2080.c rename to hal/nxp_t2080.c index 0d5bec2c..4d87fd68 100644 --- a/hal/t2080.c +++ b/hal/nxp_t2080.c @@ -1,4 +1,4 @@ -/* t2080.c +/* nxp_t2080.c * * Copyright (C) 2022 wolfSSL Inc. * @@ -280,7 +280,7 @@ enum ifc_amask_sizes { #define SATA_ENBL (*(volatile uint32_t *)(0xB1003F4C)) /* also saw 0xB4003F4C */ /* DDR */ -#if 0 /* DDR support not done */ +#if 1 #define ENABLE_DDR #endif /* NAII 68PPC2 - 8GB discrete DDR3 IM8G08D3EBDG-15E */ @@ -312,6 +312,50 @@ enum ifc_amask_sizes { #define DDR_TRTP_PS 7500 #define DDR_REF_RATE_PS 7800000 +#define DDR_CS0_BNDS_VAL 0x000000FF +#define DDR_CS1_BNDS_VAL 0x010001FF +#define DDR_CS2_BNDS_VAL 0x0300033F +#define DDR_CS3_BNDS_VAL 0x0340037F +#define DDR_CS0_CONFIG_VAL 0x80044402 +#define DDR_CS1_CONFIG_VAL 0x80044402 +#define DDR_CS2_CONFIG_VAL 0x00000202 +#define DDR_CS3_CONFIG_VAL 0x00040202 +#define DDR_CS_CONFIG_2_VAL 0x00000000 + +#define DDR_TIMING_CFG_0_VAL 0xFF530004 +#define DDR_TIMING_CFG_1_VAL 0x98906345 +#define DDR_TIMING_CFG_2_VAL 0x0040A114 +#define DDR_TIMING_CFG_3_VAL 0x010A1100 +#define DDR_TIMING_CFG_4_VAL 0x00000001 +#define DDR_TIMING_CFG_5_VAL 0x04402400 + +#define DDR_SDRAM_MODE_VAL 0x00441C70 +#define DDR_SDRAM_MODE_2_VAL 0x00980000 +#define DDR_SDRAM_MODE_3_8_VAL 0x00000000 +#define DDR_SDRAM_MD_CNTL_VAL 0x00000000 + +#define DDR_SDRAM_CFG_VAL 0xE7040000 +#define DDR_SDRAM_CFG_2_VAL 0x00401010 + +#define DDR_SDRAM_INTERVAL_VAL 0x0C300100 +#define DDR_DATA_INIT_VAL 0xDEADBEEF +#define DDR_SDRAM_CLK_CNTL_VAL 0x02400000 +#define DDR_ZQ_CNTL_VAL 0x89080600 + +#define DDR_WRLVL_CNTL_VAL 0x8675F604 +#define DDR_WRLVL_CNTL_2_VAL 0x05060607 +#define DDR_WRLVL_CNTL_3_VAL 0x080A0A0B + +#define DDR_SDRAM_RCW_1_VAL 0x00000000 +#define DDR_SDRAM_RCW_2_VAL 0x00000000 + +#define DDR_DDRCDR_1_VAL 0x80040000 +#define DDR_DDRCDR_2_VAL 0x00000001 + +#define DDR_ERR_INT_EN_VAL 0x0000001D +#define DDR_ERR_SBE_VAL 0x00010000 + + /* 12.4 DDR Memory Map */ #define DDR_BASE (CCSRBAR + 0x8000) #define DDR_BASE_PHYS (0xF00000000ULL | DDR_BASE) @@ -321,9 +365,10 @@ enum ifc_amask_sizes { #define DDR_CS_CONFIG_2(n) *((volatile uint32_t*)(DDR_BASE + 0x0C0 + (n * 4))) /* Chip select n configuration 2 */ #define DDR_SDRAM_CFG *((volatile uint32_t*)(DDR_BASE + 0x110)) /* DDR SDRAM control configuration */ #define DDR_SDRAM_CFG_2 *((volatile uint32_t*)(DDR_BASE + 0x114)) /* DDR SDRAM control configuration 2 */ -#define DDR_DATA_INIT *((volatile uint32_t*)(DDR_BASE + 0x124)) /* DDR SDRAM interval configuration */ +#define DDR_SDRAM_INTERVAL *((volatile uint32_t*)(DDR_BASE + 0x124)) /* DDR SDRAM interval configuration */ #define DDR_INIT_ADDR *((volatile uint32_t*)(DDR_BASE + 0x148)) /* DDR training initialization address */ #define DDR_INIT_EXT_ADDR *((volatile uint32_t*)(DDR_BASE + 0x14C)) /* DDR training initialization extended address */ +#define DDR_DATA_INIT *((volatile uint32_t*)(DDR_BASE + 0x128)) /* DDR training initialization value */ #define DDR_TIMING_CFG_0 *((volatile uint32_t*)(DDR_BASE + 0x104)) /* DDR SDRAM timing configuration 0 */ #define DDR_TIMING_CFG_1 *((volatile uint32_t*)(DDR_BASE + 0x108)) /* DDR SDRAM timing configuration 1 */ #define DDR_TIMING_CFG_2 *((volatile uint32_t*)(DDR_BASE + 0x10C)) /* DDR SDRAM timing configuration 2 */ @@ -335,11 +380,15 @@ enum ifc_amask_sizes { #define DDR_WRLVL_CNTL *((volatile uint32_t*)(DDR_BASE + 0x174)) /* DDR write leveling control */ #define DDR_WRLVL_CNTL_2 *((volatile uint32_t*)(DDR_BASE + 0x190)) /* DDR write leveling control 2 */ #define DDR_WRLVL_CNTL_3 *((volatile uint32_t*)(DDR_BASE + 0x194)) /* DDR write leveling control 3 */ +#define DDR_SR_CNTR *((volatile uint32_t*)(DDR_BASE + 0x17C)) /* DDR Self Refresh Counter */ +#define DDR_SDRAM_RCW_1 *((volatile uint32_t*)(DDR_BASE + 0x180)) /* DDR Register Control Word 1 */ +#define DDR_SDRAM_RCW_2 *((volatile uint32_t*)(DDR_BASE + 0x184)) /* DDR Register Control Word 2 */ #define DDR_DDRCDR_1 *((volatile uint32_t*)(DDR_BASE + 0xB28)) /* DDR Control Driver Register 1 */ #define DDR_DDRCDR_2 *((volatile uint32_t*)(DDR_BASE + 0xB2C)) /* DDR Control Driver Register 2 */ -#define DDR_ERR_DISABLE *((volatile uint32_t*)(DDR_BASE + 0xE44)) /* Memory error disable */ #define DDR_DDRDSR_1 *((volatile uint32_t*)(DDR_BASE + 0xB20)) /* DDR Debug Status Register 1 */ #define DDR_DDRDSR_2 *((volatile uint32_t*)(DDR_BASE + 0xB24)) /* DDR Debug Status Register 2 */ +#define DDR_ERR_DISABLE *((volatile uint32_t*)(DDR_BASE + 0xE44)) /* Memory error disable */ +#define DDR_ERR_INT_EN *((volatile uint32_t*)(DDR_BASE + 0xE48)) /* Memory error interrupt enable */ #define DDR_ERR_SBE *((volatile uint32_t*)(DDR_BASE + 0xE58)) /* Single-Bit ECC memory error management */ #define DDR_SDRAM_MODE *((volatile uint32_t*)(DDR_BASE + 0x118)) /* DDR SDRAM mode configuration */ #define DDR_SDRAM_MODE_2 *((volatile uint32_t*)(DDR_BASE + 0x11C)) /* DDR SDRAM mode configuration 2 */ @@ -349,9 +398,12 @@ enum ifc_amask_sizes { #define DDR_SDRAM_MODE_6 *((volatile uint32_t*)(DDR_BASE + 0x20C)) /* DDR SDRAM mode configuration 6 */ #define DDR_SDRAM_MODE_7 *((volatile uint32_t*)(DDR_BASE + 0x210)) /* DDR SDRAM mode configuration 7 */ #define DDR_SDRAM_MODE_8 *((volatile uint32_t*)(DDR_BASE + 0x214)) /* DDR SDRAM mode configuration 8 */ +#define DDR_SDRAM_MD_CNTL *((volatile uint32_t*)(DDR_BASE + 0x120)) /* DDR SDRAM mode control */ #define DDR_SDRAM_INTERVAL *((volatile uint32_t*)(DDR_BASE + 0x124)) /* DDR SDRAM interval configuration */ #define DDR_SDRAM_CLK_CNTL *((volatile uint32_t*)(DDR_BASE + 0x130)) /* DDR SDRAM clock control */ +#define DDR_SDRAM_CFG_MEM_EN 0x80000000 /* SDRAM interface logic is enabled */ +#define DDR_SDRAM_CFG2_D_INIT 0x00000010 /* data initialization in progress */ #ifdef DEBUG_UART @@ -400,27 +452,11 @@ void law_init(void) LAWBARLn(1) = FLASH_BASE; LAWBARn (1) = LAWBARn_ENABLE | LAWBARn_TRGT_ID(LAW_TRGT_IFC) | LAW_SIZE_128MB; -#ifdef ENABLE_CPLD - /* IFC - CPLD */ - LAWBARn (2) = 0; /* reset */ - LAWBARHn(2) = GET_PHYS_HIGH(CPLD_BASE_PHYS); - LAWBARLn(2) = CPLD_BASE; - LAWBARn (2) = LAWBARn_ENABLE | LAWBARn_TRGT_ID(LAW_TRGT_IFC) | LAW_SIZE_4KB; -#endif - /* Buffer Manager (BMan) (control) - probably not required */ LAWBARn (3) = 0; /* reset */ LAWBARHn(3) = 0xF; LAWBARLn(3) = 0xF4000000; LAWBARn (3) = LAWBARn_ENABLE | LAWBARn_TRGT_ID(LAW_TRGT_BMAN) | LAW_SIZE_32MB; - -#ifdef ENABLE_DDR - /* DDR */ - LAWBARn (4) = 0; /* reset */ - LAWBARHn(4) = 0; - LAWBARLn(4) = 0x0000000; - LAWBARn (4) = LAWBARn_ENABLE | LAWBARn_TRGT_ID(LAW_TRGT_DDR_1) | LAW_SIZE_8GB; -#endif } extern void write_tlb(uint32_t mas0, uint32_t mas1, uint32_t mas2, uint32_t mas3, @@ -441,23 +477,6 @@ void set_tlb(uint8_t tlb, uint8_t esel, uint32_t epn, uint64_t rpn, write_tlb(_mas0, _mas1, _mas2, _mas3, _mas7); } -/* setup memory map assist */ -void tlbs_init(void) -{ -#ifdef ENABLE_CPLD - /* CPLD - TBL=1, Entry 17 */ - set_tlb(1, 17, CPLD_BASE, CPLD_BASE_PHYS, - MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, - 0, BOOKE_PAGESZ_4K, 1); -#endif -#ifdef ENABLE_DDR - /* DDR - TBL=1, Entry 19 */ - set_tlb(1, 19, DDR_ADDRESS, 0, - MAS3_SX | MAS3_SW | MAS3_SR, 0, - 0, BOOKE_PAGESZ_2G, 1); -#endif -} - static void hal_flash_init(void) { /* NOR IFC Flash Timing Parameters */ @@ -482,9 +501,84 @@ static void hal_flash_init(void) IFC_CSOR(0) = 0x0000000C; /* TRHZ (80 clocks for read enable high) */ } -static void hal_ddr_init(void) +void hal_ddr_init(void) { #ifdef ENABLE_DDR + /* Setup DDR CS (chip select) bounds */ + DDR_CS_BNDS(0) = DDR_CS0_BNDS_VAL; + DDR_CS_CONFIG(0) = DDR_CS0_CONFIG_VAL; + DDR_CS_CONFIG_2(0) = DDR_CS_CONFIG_2_VAL; + DDR_CS_BNDS(1) = DDR_CS1_BNDS_VAL; + DDR_CS_CONFIG(1) = DDR_CS1_CONFIG_VAL; + DDR_CS_CONFIG_2(1) = DDR_CS_CONFIG_2_VAL; + DDR_CS_BNDS(2) = DDR_CS2_BNDS_VAL; + DDR_CS_CONFIG(2) = DDR_CS2_CONFIG_VAL; + DDR_CS_CONFIG_2(2) = DDR_CS_CONFIG_2_VAL; + DDR_CS_BNDS(3) = DDR_CS3_BNDS_VAL; + DDR_CS_CONFIG(3) = DDR_CS3_CONFIG_VAL; + DDR_CS_CONFIG_2(3) = DDR_CS_CONFIG_2_VAL; + + /* DDR SDRAM timing configuration */ + DDR_TIMING_CFG_0 = DDR_TIMING_CFG_0_VAL; + DDR_TIMING_CFG_1 = DDR_TIMING_CFG_1_VAL; + DDR_TIMING_CFG_2 = DDR_TIMING_CFG_2_VAL; + DDR_TIMING_CFG_3 = DDR_TIMING_CFG_3_VAL; + DDR_TIMING_CFG_4 = DDR_TIMING_CFG_4_VAL; + DDR_TIMING_CFG_5 = DDR_TIMING_CFG_5_VAL; + + /* DDR SDRAM mode configuration */ + DDR_SDRAM_MODE = DDR_SDRAM_MODE_VAL; + DDR_SDRAM_MODE_2 = DDR_SDRAM_MODE_2_VAL; + DDR_SDRAM_MODE_3 = DDR_SDRAM_MODE_3_8_VAL; + DDR_SDRAM_MODE_4 = DDR_SDRAM_MODE_3_8_VAL; + DDR_SDRAM_MODE_5 = DDR_SDRAM_MODE_3_8_VAL; + DDR_SDRAM_MODE_6 = DDR_SDRAM_MODE_3_8_VAL; + DDR_SDRAM_MODE_7 = DDR_SDRAM_MODE_3_8_VAL; + DDR_SDRAM_MODE_8 = DDR_SDRAM_MODE_3_8_VAL; + DDR_SDRAM_MD_CNTL = DDR_SDRAM_MD_CNTL_VAL; + + /* DDR Configuration */ + DDR_SDRAM_INTERVAL = DDR_SDRAM_INTERVAL_VAL; + DDR_SDRAM_CLK_CNTL = DDR_SDRAM_CLK_CNTL_VAL; + DDR_DATA_INIT = DDR_DATA_INIT_VAL; + DDR_ZQ_CNTL = DDR_ZQ_CNTL_VAL; + DDR_WRLVL_CNTL = DDR_WRLVL_CNTL_VAL; + DDR_WRLVL_CNTL_2 = DDR_WRLVL_CNTL_2_VAL; + DDR_WRLVL_CNTL_3 = DDR_WRLVL_CNTL_3_VAL; + DDR_SR_CNTR = 0; + DDR_SDRAM_RCW_1 = 0; + DDR_SDRAM_RCW_2 = 0; + DDR_DDRCDR_1 = DDR_DDRCDR_1_VAL; + DDR_DDRCDR_2 = DDR_DDRCDR_2_VAL; + DDR_SDRAM_CFG_2 = DDR_SDRAM_CFG_2_VAL; + DDR_INIT_ADDR = 0; + DDR_INIT_EXT_ADDR = 0; + DDR_ERR_DISABLE = 0; + DDR_ERR_INT_EN = DDR_ERR_INT_EN_VAL; + DDR_ERR_SBE = DDR_ERR_SBE_VAL; + + /* Set values, but do not enable the DDR yet */ + DDR_SDRAM_CFG = (DDR_SDRAM_CFG_VAL & ~DDR_SDRAM_CFG_MEM_EN); + + /* TODO: Errata A009942 */ + + /* Enable controller */ + DDR_SDRAM_CFG |= DDR_SDRAM_CFG_MEM_EN; + asm volatile("sync;isync"); + + /* Map LAW for DDR */ + LAWBARn (4) = 0; /* reset */ + LAWBARHn(4) = 0; + LAWBARLn(4) = 0x0000000; + LAWBARn (4) = LAWBARn_ENABLE | LAWBARn_TRGT_ID(LAW_TRGT_DDR_1) | LAW_SIZE_8GB; + + /* Wait for data initialization is complete */ + while ((DDR_SDRAM_CFG_2 & DDR_SDRAM_CFG2_D_INIT)); + + /* DDR - TBL=1, Entry 19 */ + set_tlb(1, 19, DDR_ADDRESS, 0, + MAS3_SX | MAS3_SW | MAS3_SR, 0, + 0, BOOKE_PAGESZ_2G, 1); #endif } @@ -510,6 +604,17 @@ static void hal_cpld_init(void) IFC_CSPR_V); IFC_AMASK(3) = IFC_AMASK_64KB; IFC_CSOR(3) = 0; + + /* IFC - CPLD */ + LAWBARn (2) = 0; /* reset */ + LAWBARHn(2) = GET_PHYS_HIGH(CPLD_BASE_PHYS); + LAWBARLn(2) = CPLD_BASE; + LAWBARn (2) = LAWBARn_ENABLE | LAWBARn_TRGT_ID(LAW_TRGT_IFC) | LAW_SIZE_4KB; + + /* CPLD - TBL=1, Entry 17 */ + set_tlb(1, 17, CPLD_BASE, CPLD_BASE_PHYS, + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, + 0, BOOKE_PAGESZ_4K, 1); #endif } @@ -524,7 +629,6 @@ void hal_init(void) hal_flash_init(); hal_cpld_init(); - hal_ddr_init(); #ifdef ENABLE_CPLD CPLD_DATA(CPLD_PROC_STATUS) = 1; /* Enable proc reset */ diff --git a/hal/t2080.ld b/hal/nxp_t2080.ld similarity index 91% rename from hal/t2080.ld rename to hal/nxp_t2080.ld index 35883caf..3b4172e0 100644 --- a/hal/t2080.ld +++ b/hal/nxp_t2080.ld @@ -12,8 +12,8 @@ BOOTSTRAP_ENTRY = 0xEFFFFFFC; MEMORY { FLASH (rx) : ORIGIN = @WOLFBOOT_ORIGIN@, LENGTH = @BOOTLOADER_PARTITION_SIZE@ - /* Use L1 memory (DDR is not setup yet) */ - RAM (rwx) : ORIGIN = 0xFDD00000, LENGTH = 0x4000 + /* Note: If DDR not setup, can use L1 memory at 0xFDD00000 and 0x4000 length */ + RAM (rwx) : ORIGIN = 0x00000000, LENGTH = 0x7FFFFFFF } SECTIONS diff --git a/src/boot_ppc.c b/src/boot_ppc.c index 5e402d07..eaf22608 100644 --- a/src/boot_ppc.c +++ b/src/boot_ppc.c @@ -32,6 +32,7 @@ extern unsigned int _start_data; extern unsigned int _end_data; extern void main(void); +extern void hal_ddr_init(void); #define MTSPR(rn, v) asm volatile("mtspr " rn ",%0" : : "r" (v)) @@ -62,10 +63,17 @@ void invalidate_tlb(int tlb) MTSPR(MMUCSR0, 0x2); } +void __attribute((weak)) hal_ddr_init(void) +{ + +} + void boot_entry_C(void) { register unsigned int *dst, *src; + hal_ddr_init(); + /* Copy the .data section from flash to RAM */ src = (unsigned int*)&_stored_data; dst = (unsigned int*)&_start_data; @@ -92,8 +100,10 @@ void do_boot(const uint32_t *app_offset, const uint32_t* dts_offset) void do_boot(const uint32_t *app_offset) #endif { +#ifdef MMU /* TODO: Determine if the dts_offset needs passed as argument */ (void)dts_offset; +#endif asm volatile("mtlr %0; blr":: "r"(app_offset)); } diff --git a/src/boot_ppc_start.S b/src/boot_ppc_start.S index d1e93f2d..76b94b7e 100644 --- a/src/boot_ppc_start.S +++ b/src/boot_ppc_start.S @@ -447,9 +447,6 @@ ram_q: tlbwe isync - /* Init the MMU Assist registers */ - bl tlbs_init - /* switch back to AS/TS=0 */ lis 3,(MSR_DE)@h ori 3,3,(MSR_DE)@l diff --git a/test-app/app_t2080.c b/test-app/app_nxp_t2080.c similarity index 98% rename from test-app/app_t2080.c rename to test-app/app_nxp_t2080.c index 0be51e2a..7f8d78d1 100644 --- a/test-app/app_t2080.c +++ b/test-app/app_nxp_t2080.c @@ -1,6 +1,6 @@ -/* app_t2080.c +/* app_nxp_t2080.c * - * Copyright (C) 2021 wolfSSL Inc. + * Copyright (C) 2022 wolfSSL Inc. * * This file is part of wolfBoot. *