Added SPI support for nrf52

hal/nrf52.ld

@@ -1,7 +1,7 @@
 MEMORY
 {
-    FLASH (rx) : ORIGIN = 0x0001f000, LENGTH = ##WOLFBOOT_PARTITION_BOOT_ADDRESS##
+    FLASH (rx) : ORIGIN = 0x00000000, LENGTH = ##WOLFBOOT_PARTITION_BOOT_ADDRESS##
-    RAM (rwx) :  ORIGIN = 0x20002800, LENGTH = 0xD800
+    RAM (rwx) :  ORIGIN = 0x20000000, LENGTH = 64K
 }
 
 SECTIONS

hal/spi/spi_drv_nrf52.c

@@ -0,0 +1,122 @@
+/* spi_drv_nrf52.c
+ *
+ * Driver for the SPI back-end of the SPI_FLASH module.
+ *
+ * Example implementation for nrf52F4.
+ *
+ * Pinout: see spi_drv_nrf52.h
+ *
+ * Copyright (C) 2020 wolfSSL Inc.
+ *
+ * This file is part of wolfBoot.
+ *
+ * wolfBoot is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfBoot is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
+ */
+#include <stdint.h>
+#include "spi_drv.h"
+#include "spi_drv_nrf52.h"
+
+#define SPI0 (0x40003000)
+#define SPI1 (0x40004000)
+#define SPI2 (0x40023000)
+
+#define SPI SPI0
+#define SPI_TASKS_START   *((volatile uint32_t *)(SPI + 0x10))
+#define SPI_TASKS_STOP    *((volatile uint32_t *)(SPI + 0x14))
+#define SPI_EVENTS_ENDRX  *((volatile uint32_t *)(SPI + 0x110))
+#define SPI_EVENTS_END    *((volatile uint32_t *)(SPI + 0x118))
+#define SPI_EVENTS_ENDTX  *((volatile uint32_t *)(SPI + 0x120))
+#define SPI_EV_RDY        *((volatile uint32_t *)(SPI + 0x108))
+#define SPI_INTENSET      *((volatile uint32_t *)(SPI + 0x304))
+#define SPI_INTENCLR      *((volatile uint32_t *)(SPI + 0x308))
+#define SPI_ENABLE        *((volatile uint32_t *)(SPI + 0x500))
+#define SPI_PSEL_SCK      *((volatile uint32_t *)(SPI + 0x508))
+#define SPI_PSEL_MOSI     *((volatile uint32_t *)(SPI + 0x50C))
+#define SPI_PSEL_MISO     *((volatile uint32_t *)(SPI + 0x510))
+#define SPI_RXDATA        *((volatile uint32_t *)(SPI + 0x518))
+#define SPI_TXDATA        *((volatile uint32_t *)(SPI + 0x51C))
+#define SPI_FREQUENCY     *((volatile uint32_t *)(SPI + 0x524))
+#define SPI_CONFIG        *((volatile uint32_t *)(SPI + 0x554))
+
+#define K125 0x02000000  
+#define K250 0x04000000  
+#define K500 0x08000000  
+#define M1   0x10000000  
+#define M2   0x20000000  
+#define M4   0x40000000  
+#define M8   0x80000000  
+
+void spi_cs_off(int pin)
+{
+    GPIO_OUTSET = (1 << pin);
+    while ((GPIO_OUT & (1 << pin)) == 0)
+        ;
+}
+
+void spi_cs_on(int pin)
+{
+    GPIO_OUTCLR = (1 << pin);
+    while ((GPIO_OUT & (1 << pin)) != 0)
+        ;
+
+}
+
+uint8_t spi_read(void)
+{
+    volatile uint32_t reg = SPI_EV_RDY;
+    while (!reg)
+        reg = SPI_EV_RDY;
+    reg = SPI_RXDATA;
+    SPI_EV_RDY = 0;
+    return reg;
+}
+
+void spi_write(const char byte)
+{
+    uint32_t reg;
+    SPI_EV_RDY = 0;
+    SPI_TXDATA = (uint32_t)byte;
+    while (!reg)
+        reg = SPI_EV_RDY;
+}
+
+
+void spi_init(int polarity, int phase)
+{
+    static int initialized = 0;
+    if (!initialized) {
+        initialized++;
+        GPIO_PIN_CNF[SPI_CS_PIN]   = GPIO_CNF_OUT;
+        GPIO_PIN_CNF[SPI_SCLK_PIN] = GPIO_CNF_OUT;
+        GPIO_PIN_CNF[SPI_MOSI_PIN] = GPIO_CNF_OUT;
+        GPIO_PIN_CNF[SPI_MISO_PIN] = GPIO_CNF_IN;
+        //GPIO_DIRSET = ((1 << SPI_CS_PIN) | (1 << SPI_SCLK_PIN) | (1 << SPI_MOSI_PIN));
+        GPIO_OUTSET = (1 << SPI_CS_PIN);
+        GPIO_OUTCLR = (1 << SPI_MOSI_PIN) | (1 << SPI_SCLK_PIN);
+
+        SPI_PSEL_MISO = SPI_MISO_PIN;
+        SPI_PSEL_MOSI = SPI_MOSI_PIN;
+        SPI_PSEL_SCK = SPI_SCLK_PIN;
+
+        SPI_FREQUENCY = M1;
+        SPI_CONFIG = 0; /* mode 0,0 default */
+        SPI_ENABLE = 1;
+    }
+}
+
+void spi_release(void)
+{
+
+}

hal/spi/spi_drv_nrf52.h

@@ -0,0 +1,54 @@
+/* spi_drv_nrf52.h
+ *
+ * wolfBoot is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfBoot is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
+ */
+
+#ifndef SPI_DRV_NRF52_H_INCLUDED
+#define SPI_DRV_NRF52_H_INCLUDED
+#include <stdint.h>
+/** SPI settings **/
+
+
+#define GPIO_BASE (0x50000000)
+#define GPIO_OUT        *((volatile uint32_t *)(GPIO_BASE + 0x504))
+#define GPIO_OUTSET     *((volatile uint32_t *)(GPIO_BASE + 0x508))
+#define GPIO_OUTCLR     *((volatile uint32_t *)(GPIO_BASE + 0x50C))
+#define GPIO_DIRSET     *((volatile uint32_t *)(GPIO_BASE + 0x518))
+#define GPIO_PIN_CNF     ((volatile uint32_t *)(GPIO_BASE + 0x700)) // Array
+
+#define GPIO_CNF_IN 0
+#define GPIO_CNF_OUT 3
+
+
+/* Pinout (P0.x) */
+#if 1
+#define SPI_CS_PIN 13
+#define SPI_MOSI_PIN 4
+#define SPI_MISO_PIN 5
+#define SPI_SCLK_PIN 30
+#endif
+#if 0
+#define SPI_SCLK_PIN 5
+#define SPI_MISO_PIN 6
+#define SPI_MOSI_PIN 7
+#define SPI_CS_PIN 8
+#endif
+
+
+#define SPI_CS_FLASH SPI_CS_PIN
+
+
+
+#endif

include/spi_drv.h

@@ -39,6 +39,10 @@
 #include "hal/spi/spi_drv_zynq.h"
 #endif
 
+#if defined(PLATFORM_nrf52)
+#include "hal/spi/spi_drv_nrf52.h"
+#endif
+
 void spi_init(int polarity, int phase);
 void spi_write(const char byte);
 uint8_t spi_read(void);

test-app/app_nrf52.c

@@ -40,7 +40,8 @@ static void gpiotoggle(uint32_t pin)
 
 void main(void)
 {
-    uint32_t pin = 19;
+    //uint32_t pin = 19;
+    uint32_t pin = 6;
     int i;
     GPIO_PIN_CNF[pin] = 1; /* Output */
     while(1) {

test-app/app_stm32f4.c

@@ -290,47 +290,5 @@ void main(void) {
     while(1)
         ;
 }
-#endif /** PLATFROM_stm32f4 **/
+#endif /** PLATFORM_stm32f4 **/
 
-#ifdef PLATFORM_nrf52
-#define GPIO_BASE (0x50000000)
-#define GPIO_OUT        *((volatile uint32_t *)(GPIO_BASE + 0x504))
-#define GPIO_OUTSET     *((volatile uint32_t *)(GPIO_BASE + 0x508))
-#define GPIO_OUTCLR     *((volatile uint32_t *)(GPIO_BASE + 0x50C))
-#define GPIO_PIN_CNF     ((volatile uint32_t *)(GPIO_BASE + 0x700)) // Array
-
-static void gpiotoggle(uint32_t pin)
-{
-    uint32_t reg_val = GPIO_OUT;
-    GPIO_OUTCLR = reg_val & (1 << pin);
-    GPIO_OUTSET = (~reg_val) & (1 << pin);
-}
-
-void main(void)
-{
-    uint32_t pin = 19;
-    int i;
-    GPIO_PIN_CNF[pin] = 1; /* Output */
-    while(1) {
-        gpiotoggle(pin);
-        for (i = 0; i < 800000; i++)  // Wait a bit.
-              asm volatile ("nop");
-    }
-}
-
-#endif
-
-#ifdef PLATFORM_samr21
-void main(void) {
-    asm volatile ("cpsie i");
-    while(1)
-        WFI();
-}
-#endif
-
-#ifdef PLATFORM_hifive1
-void main(void) {
-    while(1)
-        ;
-}
-#endif