mirror of https://github.com/wolfSSL/wolfBoot.git
Progress on NXP P1021 eLBC FCM driver for NAND flash.
David Garske
Daniele Lacamera
parent
c6983b8c42
commit
f91e82a452
164
hal/nxp_p1021.c
164
hal/nxp_p1021.c
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@ -26,6 +26,15 @@
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#define CCSRBAR (0xFF700000)
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#define SYS_CLK (400000000)
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/* Global Utilities (GUTS) */
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#define GUTS_PORPLLSR *((volatile uint32_t*)(CCSRBAR + 0x0UL)) /* POR PLL ratio status register */
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/* Local Bus Controller (LBC) */
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#define LBC_BASE (CCSRBAR + 0x5000)
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#define LBC_LBCR *((volatile uint32_t*)(LBC_BASE + 0xD0))
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#define LBC_LBCR_ABSWP (1 << 19) /* Address byte swap for 16-bit port size */
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/* P1021 PC16552D Dual UART */
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#define BAUD_RATE 115200
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#define UART_SEL 0 /* select UART 0 or 1 */
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@ -158,13 +167,21 @@ enum law_sizes {
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#define ELBC_BASE (CCSRBAR + 0x5000)
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#define ELBC_MAX_BANKS 8
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#define ELBC_BR(n) *((volatile uint32_t*)(ELBC_BASE + 0x0000 + (n * 0x8))) /* Base registers */
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#define ELBC_OR(n) *((volatile uint32_t*)(ELBC_BASE + 0x0000 + (n * 0x8))) /* Options registers */
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#define ELBC_MDR *((volatile uint32_t*)(ELBC_BASE + 0x88)) /* memory data register */
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#define ELBC_FIR *((volatile uint32_t*)(ELBC_BASE + 0xE4)) /* flash instruction register */
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#define ELBC_FCR *((volatile uint32_t*)(ELBC_BASE + 0xE8)) /* flash command register */
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#define ELBC_FBAR *((volatile uint32_t*)(ELBC_BASE + 0xEC)) /* flash address register - OR_PGS=0 (shift 5), OR_PGS=1 (shift 6) */
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#define ELBC_FPAR *((volatile uint32_t*)(ELBC_BASE + 0xF0)) /* flash page address register*/
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#define ELBC_BR(n) *((volatile uint32_t*)(ELBC_BASE + 0x0000 + (n * 0x8))) /* Base registers */
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#define ELBC_OR(n) *((volatile uint32_t*)(ELBC_BASE + 0x0000 + (n * 0x8))) /* Options registers */
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#define ELBC_MDR *((volatile uint32_t*)(ELBC_BASE + 0x88)) /* memory data register */
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#define ELBC_LSOR *((volatile uint32_t*)(ELBC_BASE + 0x90)) /* operation initiation register */
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#define ELBC_FMR *((volatile uint32_t*)(ELBC_BASE + 0xE0)) /* flash mode register */
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#define ELBC_FIR *((volatile uint32_t*)(ELBC_BASE + 0xE4)) /* flash instruction register */
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#define ELBC_FCR *((volatile uint32_t*)(ELBC_BASE + 0xE8)) /* flash command register */
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#define ELBC_FBAR *((volatile uint32_t*)(ELBC_BASE + 0xEC)) /* flash address register - OR_PGS=0 (shift 5), OR_PGS=1 (shift 6) */
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#define ELBC_FPAR *((volatile uint32_t*)(ELBC_BASE + 0xF0)) /* flash page address register */
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#define ELBC_FBCR *((volatile uint32_t*)(ELBC_BASE + 0xF4)) /* flash byte count register */
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#define ELBC_LTESR *((volatile uint32_t*)(ELBC_BASE + 0xB0)) /* transfer error status register */
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#define ELBC_LTEIR *((volatile uint32_t*)(ELBC_BASE + 0xB8)) /* transfer error interrupt enable register */
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#define ELBC_LTEATR *((volatile uint32_t*)(ELBC_BASE + 0xBC)) /* transfer error attributes register */
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#define ELBC_BR_ADDR(n) (((uint32_t)n) & 0xFFFF8000) /* Physical base address - upper 17-bits */
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#define ELBC_BR_PS(n) (((n) & 0x3) << 12) /* port size - 1=8-bit, 2=16-bit */
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@ -187,24 +204,31 @@ enum law_sizes {
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#define ELBC_OR_TRLX (1 << 2) /* timing related */
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#define ELBC_OR_EHTR (1 << 1) /* extended hold time - LRLX=0 (0=1 or 1=2), LRLX=1 (0=2 or 1=8) inserted idle clock cycles */
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#define ELBC_LSOR_BANK(n) ((n) & 0x7) /* flash bank 0-7 */
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#define ELBC_FMR_CWTO(n) /* command wait timeout */
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#define ELBC_FMR_BOOT (1 << 11) /* flash auto-boot lead mode 0=FCM is op normal, 1=eLBC autoload 4-Kbyte boot block */
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#define ELBC_FMR_ECCM (1 << 8) /* ECC mode 0=ECC is checked/calc 6/8 spare, 1=8/10 spare */
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#define ELBC_FMR_AL(n) (((n) & 0x3) << 4) /* address length */
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#define ELBC_FMR_OP(n) (((n) & 0x3) << 0) /* flash operation 0=normal, 1=sim auto-boot block load, 2=exe FIR cmd w/write protect enable, 3=exe FIR cmd */
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#define ELBC_FIR_OP(s,op) ((op) & 0xF) << (28 - ((s % 8) * 4)) /* up to 8 sequences of instructions */
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/* 0=NOP-No-operation and end of operation sequence,
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* 1=CA-Issue current column address as set in FPAR, with length set by ORx[PGS]
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* 2=PA-Issue current block+page address as set in FBAR and FPAR, with length set by FMR[AL]
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* 3=UA-Issue user-defined address byte from next AS field in MDR
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* 4=CM0-Issue command from FCR[CMD0]
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* 5=CM1-Issue command from FCR[CMD1]
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* 6=CM2-Issue command from FCR[CMD2]
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* 7=CM3-Issue command from FCR[CMD3]
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* 8=WB-Write FBCR bytes of data from current FCM buffer to Flash device
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* 9=WS-Write one byte (8b port) of data from next AS field of MDR to Flash device
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* 10=RB-Read FBCR bytes of data from Flash device into current FCM RAM buffer
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* 11=RS-Read one byte (8b port) of data from Flash device into next AS field of MDR
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* 12=CW0-Wait for LFRB to return high or time-out, then issue command from FCR[CMD0]
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* 13=CW1-Wait for LFRB to return high or time-out, then issue command from FCR[CMD1]
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* 14=RBW-Wait for LFRB to return high or time-out, then read FBCR bytes of data from Flash device into current FCM RAM buffer
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* 15=RSW-Wait for LFRB to return high or time-out, then read one byte (8b port) of data from Flash device into next AS field of MDR
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*/
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#define ELBC_FIR_OP_NOP 0 /* No-operation and end of operation sequence */
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#define ELBC_FIR_OP_CA 1 /* Issue current column address as set in FPAR, with length set by ORx[PGS] */
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#define ELBC_FIR_OP_PA 2 /* Issue current block+page address as set in FBAR and FPAR, with length set by FMR[AL] */
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#define ELBC_FIR_OP_UA 3 /* Issue user-defined address byte from next AS field in MDR */
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#define ELBC_FIR_OP_CM0 4 /* Issue command from FCR[CMD0] */
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#define ELBC_FIR_OP_CM1 5 /* Issue command from FCR[CMD1] */
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#define ELBC_FIR_OP_CM2 6 /* Issue command from FCR[CMD2] */
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#define ELBC_FIR_OP_CM3 7 /* Issue command from FCR[CMD3] */
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#define ELBC_FIR_OP_WB 8 /* Write FBCR bytes of data from current FCM buffer to Flash device */
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#define ELBC_FIR_OP_WS 9 /* Write one byte (8b port) of data from next AS field of MDR to Flash device */
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#define ELBC_FIR_OP_RB 10 /* Read FBCR bytes of data from Flash device into current FCM RAM buffer */
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#define ELBC_FIR_OP_RS 11 /* Read one byte (8b port) of data from Flash device into next AS field of MDR */
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#define ELBC_FIR_OP_CW0 12 /* Wait for LFRB to return high or time-out, then issue command from FCR[CMD0] */
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#define ELBC_FIR_OP_CW1 13 /* Wait for LFRB to return high or time-out, then issue command from FCR[CMD1] */
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#define ELBC_FIR_OP_RBW 14 /* Wait for LFRB to return high or time-out, then read FBCR bytes of data from Flash device into current FCM RAM buffer */
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#define ELBC_FIR_OP_RSW 15 /* Wait for LFRB to return high or time-out, then read one byte (8b port) of data from Flash device into next AS field of MDR */
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#define ELBC_FCR_CMD(s,cmd) (((cmd) & 0xFF) << (24 - ((s % 4) * 8))) /* up to 4 command opcodes */
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#define ELBC_FBAR_ADDR(n) (((n) >> 5) & 0xFFFFFF)
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@ -212,7 +236,11 @@ enum law_sizes {
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#define ELBC_FPAR_MS (1 << 9) /* main/spare region locator */
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#define ELBC_FPAR_CI(n) ((n) & 0x1FF)
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#define ELBC_LTESR_FCT (1 << 30) /* FCM command timeout */
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#define ELBC_LTESR_PAR (1 << 29) /* Parity of ECC error */
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#define ELBC_LTESR_CC (1 << 0) /* FCM command completion event */
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#define ELBC_NAND_MASK (ELBC_LTESR_FCT | ELBC_LTESR_PAR | ELBC_LTESR_CC)
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/* IFC AMASK - RM Table 12-6 - Count of MSB minus 1 */
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@ -239,7 +267,7 @@ enum elbc_amask_sizes {
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/* NAND Flash */
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#define FLASH_BASE 0xEC000000
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#define FLASH_BASE 0xFC000000 /* memory used for transfering block to/from NAND */
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#define FLASH_BANK_SIZE (64*1024*1024)
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#define FLASH_PAGE_SIZE (1024) /* program buffer */
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@ -251,6 +279,20 @@ enum elbc_amask_sizes {
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#define FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
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#define FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
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/* NAND Flash Commands */
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#define NAND_CMD_READ_ID 0x90
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#define NAND_CMD_STATUS 0x70
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#define NAND_CMD_READA 0x00
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#define NAND_CMD_READB 0x01
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#define NAND_CMD_READC 0x50
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#define NAND_CMD_PAGE_PROG1 0x80
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#define NAND_CMD_PAGE_PROG2 0x10
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#define NAND_CMD_BLOCK_ERASE1 0x60
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#define NAND_CMD_BLOCK_ERASE2 0xD0
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#define NAND_CMD_RESET 0xFF
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/* DDR */
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#if 1
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#define ENABLE_DDR
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@ -382,10 +424,6 @@ void uart_write(const char* buf, uint32_t sz)
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/* called from boot_ppc_start.S */
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void law_init(void)
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{
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/* IFC - NAND Flash */
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LAWAR (1) = 0; /* reset */
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LAWBAR(1) = FLASH_BASE;
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LAWAR (1) = LAWAR_ENABLE | LAWAR_TRGT_ID(LAW_TRGT_ELBC) | LAW_SIZE_64MB;
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}
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@ -407,8 +445,43 @@ void set_tlb(uint8_t tlb, uint8_t esel, uint32_t epn, uint64_t rpn,
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write_tlb(_mas0, _mas1, _mas2, _mas3, _mas7);
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}
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static void hal_flash_set_addr(int col, int page)
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{
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ELBC_FBAR = ELBC_FBAR_ADDR(page);
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ELBC_FPAR = ELBC_FPAR_PI(page) | ELBC_FPAR_CI(col);
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}
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static int hal_flash_command()
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{
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/* Read Flash ID */
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ELBC_FIR = ELBC_FIR_OP(0, ELBC_FIR_OP_CW0) |
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ELBC_FIR_OP(1, ELBC_FIR_OP_UA) |
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ELBC_FIR_OP(2, ELBC_FIR_OP_RBW);
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ELBC_FCR = ELBC_FCR_CMD(0, NAND_CMD_READ_ID);
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ELBC_FBCR = 5;
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hal_flash_set_addr(0, 0);
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ELBC_FMR = ELBC_FMR_OP(3); /* execure FIR with write support */
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ELBC_MDR = 0;
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ELBC_LSOR = ELBC_LSOR_BANK(0);
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/* wait for FCM complete flag */
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while (!(ELBC_LTESR & ELBC_LTESR_CC));
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/* clear interrupt */
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ELBC_LTESR &= ELBC_NAND_MASK;
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ELBC_LTEATR = 0;
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/* TODO: Download from correct base buffer page (8 - 1KB pages) */
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/* Example: FLASH_BASE + (0x400 * page) + */
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return 0;
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}
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static void hal_flash_init(void)
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{
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uint8_t flash_id[8];
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/* NAND Definitions (CS0) */
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/* FSM, 8-bit, ECC check/gen enable, valid */
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ELBC_BR(0) = ELBC_BR_ADDR(FLASH_BASE) |
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@ -419,6 +492,13 @@ static void hal_flash_init(void)
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ELBC_OR_CSCT | ELBC_OR_CST | ELBC_OR_CHT | ELBC_OR_SCY(1) |
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ELBC_OR_TRLX | ELBC_OR_EHTR;
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/* Clear event registers */
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ELBC_LTESR = ELBC_NAND_MASK;
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ELBC_LTEATR = 0;
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/* Enable interrupts */
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ELBC_LTEIR = ELBC_NAND_MASK;
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}
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void hal_ddr_init(void)
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@ -492,6 +572,8 @@ void hal_ddr_init(void)
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void hal_init(void)
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{
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LBC_LBCR |= LBC_LBCR_ABSWP; /* Enable LBC address byte swap */
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#ifdef DEBUG_UART
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uint32_t fw;
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@ -521,32 +603,12 @@ int hal_flash_erase(uint32_t address, int len)
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void hal_flash_unlock(void)
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{
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/* Disable all flash protection bits */
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/* enter Non-volatile protection mode (C0h) */
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*((volatile uint16_t*)(FLASH_BASE + 0xAAA)) = 0xAAAA;
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*((volatile uint16_t*)(FLASH_BASE + 0x554)) = 0x5555;
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*((volatile uint16_t*)(FLASH_BASE + 0xAAA)) = 0xC0C0;
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/* clear all protection bit (80h/30h) */
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*((volatile uint16_t*)(FLASH_BASE + 0x000)) = 0x8080;
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*((volatile uint16_t*)(FLASH_BASE + 0x000)) = 0x3030;
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/* exit Non-volatile protection mode (90h/00h) */
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*((volatile uint16_t*)(FLASH_BASE + 0x000)) = 0x9090;
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*((volatile uint16_t*)(FLASH_BASE + 0x000)) = 0x0000;
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}
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void hal_flash_lock(void)
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{
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/* Enable all flash protection bits */
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/* enter Non-volatile protection mode (C0h) */
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*((volatile uint16_t*)(FLASH_BASE + 0xAAA)) = 0xAAAA;
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*((volatile uint16_t*)(FLASH_BASE + 0x554)) = 0x5555;
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*((volatile uint16_t*)(FLASH_BASE + 0xAAA)) = 0xC0C0;
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/* set all protection bit (A0h/00h) */
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*((volatile uint16_t*)(FLASH_BASE + 0x000)) = 0xA0A0;
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*((volatile uint16_t*)(FLASH_BASE + 0x000)) = 0x0000;
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/* exit Non-volatile protection mode (90h/00h) */
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*((volatile uint16_t*)(FLASH_BASE + 0x000)) = 0x9090;
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*((volatile uint16_t*)(FLASH_BASE + 0x000)) = 0x0000;
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}
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void hal_prepare_boot(void)
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@ -1,6 +1,6 @@
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/* boot_ppc_start.S
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*
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* Copyright (C) 2021 wolfSSL Inc.
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* Copyright (C) 2022 wolfSSL Inc.
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*
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* This file is part of wolfBoot.
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*
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