Make `flush_dcache_range` available even with `USE_BUILTIN_STARTUP`. Remove unused variable.

hal/zynq.c

@@ -311,8 +311,6 @@ static inline int qspi_dmaisr_wait(uint32_t wait_mask, uint32_t wait_val)
 
 static int qspi_gen_fifo_write(uint32_t reg_genfifo)
 {
-    uint32_t reg_cfg;
-
     /* wait until the gen FIFO is not full to write */
     if (qspi_isr_wait(GQSPI_IXR_GEN_FIFO_NOT_FULL, 0)) {
         return GQSPI_CODE_TIMEOUT;

src/boot_aarch64_start.S

@@ -462,32 +462,6 @@ invalidatecaches_end:
     ret
 
 
-/*
- * void flush_dcache_range(start, end)
- *
- * clean & invalidate data cache in the range
- *
- * x0: start address
- * x1: end address
- */
-.global flush_dcache_range
-flush_dcache_range:
-    mrs    x3, ctr_el0
-    lsr    x3, x3, #16
-    and    x3, x3, #0xf
-    mov    x2, #4
-    lsl    x2, x2, x3  /* cache line size */
-
-    /* x2 <- minimal cache line size in cache system */
-    sub    x3, x2, #1
-    bic    x0, x0, x3
-1:  dc     civac, x0 /* clean & invalidate data or unified cache */
-    add    x0, x0, x2
-    cmp    x0, x1
-    b.lo   1b
-    dsb    sy
-    ret
-
 
 /*
 * Below is the static translation page table required by MMU for Cortex-A53.
@@ -1058,6 +1032,33 @@ FPUStatus:
 #endif /* !USE_BUILTIN_STARTUP */
 
 
+/*
+ * void flush_dcache_range(start, end)
+ *
+ * clean & invalidate data cache in the range
+ *
+ * x0: start address
+ * x1: end address
+ */
+.global flush_dcache_range
+flush_dcache_range:
+    mrs    x3, ctr_el0
+    lsr    x3, x3, #16
+    and    x3, x3, #0xf
+    mov    x2, #4
+    lsl    x2, x2, x3  /* cache line size */
+
+    /* x2 <- minimal cache line size in cache system */
+    sub    x3, x2, #1
+    bic    x0, x0, x3
+1:  dc     civac, x0 /* clean & invalidate data or unified cache */
+    add    x0, x0, x2
+    cmp    x0, x1
+    b.lo   1b
+    dsb    sy
+    ret
+
+
 /* Initialize GIC 400 (GICv2) */
 .global gicv2_init_secure
 gicv2_init_secure: