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wolfBoot
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5 Commits (dd113303e24daf9c5bcd6c1dfa94e1a7389c71eb)

Author SHA1 Message Date
David Garske 4103b8b5af Avoid redefinition when using USE_BUILTIN_STARTUP. 2025-01-20 16:39:18 +01:00
David Garske b8a23b1f81 Allow build-time adjustment of QSPI reference clock and divisor. Eliminate `ZCU102` macro (not needed). Add QSPI init message with ref clock, divisor, bus and IO mode (Poll or DMA). 2024-12-30 15:36:43 +01:00
David Garske f729e419e6 Fixes for QSPI DMA mode. For example reduces QSPI->DDR load of 154MB from 18,228ms to 2,607ms. Changed QSPI to use DMA by default (can force IO mode using `GQSPI_MODE_IO`). 2024-12-30 15:36:43 +01:00
David Garske 7205820afa Added QSPI DMA support. 2024-12-30 15:36:43 +01:00
David Garske acb9d832eb Fixes for Xilinx Zynq UltraScale+ MPSoC: 
* Fixes to support wolfBoot native make and gcc-arm cross compiler. ZD 18159
* Adjust wolfBoot linker script to not use 0 base, instead use end of DDR - 1MB.
* Fixed QSPI bare-metal driver for multi-sector and read return code.
* Fixed issue with Xilinx XMSS IMAGE_HEADER_SIZE in documentation. It should be 5000 bytes.
* Performance optimizations for QSPI:
  - Allow configuration of SPI clock.
  - Improve GSPI FIFO TX/RX fill.
* Added support for FAST_MEMCPY that supports an aligned 32-bit.
* Added Flattened uImage Tree (FIT) image (FDT format).
* Added Aarch64 support for FDT fixups.
* Added Aarch64 startup to support EL2 with cache/MMU.
* Added documentation about exception levels
* Moved zynqmp registers to header.
* Fix printf uart_writenum "buf" len.
* Updated fdt-parser to support saving off larger data images.
 2024-12-30 15:36:43 +01:00