Commit Graph

5 Commits (e8eb29962140bdbcc7c1643f28acff945eb9dcf0)

Author SHA1 Message Date
David Garske 0f00f8e700 SiFive HiFive (FE310) RISC-V support
* HiFive1 HAL Support for PLL Clock, UART, RTC and Flash QSPI Erase/Write.
* HiFive1 update demo application for accepting firmware updates over UART.
* Added test-update-server application for pushing firmware image over UART.
* Fixes for building with `make SIGN=ECC256`.
* Improvements to wolfCrypt `user_settings.h`.
* General library cleanup (license headers and formatting)
* Updated the wolfSSL submodule to latest.
* Documentation updates including new `Targets.md` section for hardare instructions.
2019-06-07 13:08:15 -07:00
Daniele Lacamera fc547e4a25 wolfBoot can update itself when compiled with RAM_CODE=1
- Added wolfBoot version
- Added extra 16bit header tag to identify the image type and authentication
- Implemented optional in-ram self-update of the bootloader, with version control
and authentication mechanism (not fail-safe)
2019-04-29 20:32:04 +02:00
Daniele Lacamera 630a10eafa Automated tests for EXT_FLASH/SPI_FLASH 2019-03-15 11:16:34 +01:00
Daniele Lacamera 503b008cf5 New feature: allow swapping from external memory (e.g. SPI flash) 2019-02-15 13:41:06 +01:00
Daniele Lacamera 62fcc55285 Simplified code structure, got rid of some configuration defines 2018-10-23 12:14:50 +02:00