mirror of https://github.com/wolfSSL/wolfBoot.git
444 lines
18 KiB
C
444 lines
18 KiB
C
/* stm32h5.h
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*
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* Copyright (C) 2024 wolfSSL Inc.
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*
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* This file is part of wolfBoot.
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*
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* wolfBoot is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* wolfBoot is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
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*/
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#ifndef STM32H5_DEF_INCLUDED
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#define STM32H5_DEF_INCLUDED
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/* Assembly helpers */
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#ifndef DMB
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#define DMB() __asm__ volatile ("dmb")
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#endif
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#define ISB() __asm__ volatile ("isb")
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#define DSB() __asm__ volatile ("dsb")
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#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) && !defined(NONSECURE_APP))
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# define TZ_SECURE() (1)
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#else
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# define TZ_SECURE() (0)
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#endif
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/* STM32 H5 register configuration */
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/*** RCC ***/
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#if TZ_SECURE()
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/*Secure */
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#define RCC_BASE (0x54020c00) /* RM0481 - Table 3 */
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#else
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/*Non-Secure */
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#define RCC_BASE (0x44020C00) /* RM0481 - Table 3 */
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#endif
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#define FLASH_SECURE_MMAP_BASE (0x0C000000)
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#define RCC_CR (*(volatile uint32_t *)(RCC_BASE + 0x00)) /* RM0481 - Table 108 */
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#define RCC_CR_PLL3RDY (1 << 29) /* RM0481 - Table 108 */
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#define RCC_CR_PLL3ON (1 << 28) /* RM0481 - Table 108 */
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#define RCC_CR_PLL2RDY (1 << 27) /* RM0481 - Table 108 */
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#define RCC_CR_PLL2ON (1 << 26) /* RM0481 - Table 108 */
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#define RCC_CR_PLL1RDY (1 << 25) /* RM0481 - Table 108 */
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#define RCC_CR_PLL1ON (1 << 24) /* RM0481 - Table 108 */
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#define RCC_CR_HSEEXT (1 << 20) /* RM0481 - Table 108 */
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#define RCC_CR_HSECSSON (1 << 19) /* RM0481 - Table 108 */
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#define RCC_CR_HSEBYP (1 << 18) /* RM0481 - Table 108 */
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#define RCC_CR_HSERDY (1 << 17) /* RM0481 - Table 108 */
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#define RCC_CR_HSEON (1 << 16) /* RM0481 - Table 108 */
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#define RCC_CR_HSI48RDY (1 << 13) /* RM0481 - Table 108 */
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#define RCC_CR_HSI48ON (1 << 12) /* RM0481 - Table 108 */
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#define RCC_CR_CSIKERON (1 << 10) /* RM0481 - Table 108 */
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#define RCC_CR_CSIRDY (1 << 9) /* RM0481 - Table 108 */
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#define RCC_CR_CSION (1 << 8) /* RM0481 - Table 108 */
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#define RCC_CR_HSIDIVF (1 << 5) /* RM0481 - Table 108 */
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#define RCC_CR_HSIDIV_SHIFT (3) /* RM0481 - Table 108 */
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#define RCC_CR_HSIKERON (1 << 2) /* RM0481 - Table 108 */
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#define RCC_CR_HSIRDY (1 << 1) /* RM0481 - Table 108 */
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#define RCC_CR_HSION (1 << 0) /* RM0481 - Table 108 */
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#define RCC_CFGR1 (*(volatile uint32_t *)(RCC_BASE + 0x1C)) /* RM0481 - 11.8.5 */
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#define RCC_CFGR2 (*(volatile uint32_t *)(RCC_BASE + 0x20)) /* RM0481 - 11.8.6 */
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/* CFGR1 - PLL Source selection */
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#define RCC_CFGR1_SW_SHIFT (0x0)
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#define RCC_CFGR1_SWS_SHIFT (0x3)
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#define RCC_CFGR1_SW_HSI (0x0) /* 00: HSI selected as system clock, default after reset */
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#define RCC_CFGR1_SW_CSI (0x1)
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#define RCC_CFGR1_SW_HSE (0x2)
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#define RCC_CFGR1_SW_PLL1 (0x3)
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#define RCC_CFGR1_SW_MASK (0x3)
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/* HPRE - PPRE1 - PPRE2 - PPRE3 */
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#define RCC_CFGR2_HPRE_SHIFT (0x0)
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#define RCC_CFGR2_PPRE1_SHIFT (0x4)
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#define RCC_CFGR2_PPRE2_SHIFT (0x8)
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#define RCC_CFGR2_PPRE3_SHIFT (0xC)
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/* PLL1 Configuration */
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#define RCC_PLL1CFGR (*(volatile uint32_t *)(RCC_BASE + 0x28)) /* RM0481 - Table 108 */
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#define RCC_PLL1DIVR (*(volatile uint32_t *)(RCC_BASE + 0x34)) /* RM0481 - Table 108 */
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#define RCC_PLL1FRACR (*(volatile uint32_t *)(RCC_BASE + 0x38)) /* RM0481 - Table 108 */
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/* PLL2 Configuration */
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#define RCC_PLL2CFGR (*(volatile uint32_t *)(RCC_BASE + 0x2C)) /* RM0481 - Table 108 */
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#define RCC_PLL2DIVR (*(volatile uint32_t *)(RCC_BASE + 0x3C)) /* RM0481 - Table 108 */
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#define RCC_PLL2FRACR (*(volatile uint32_t *)(RCC_BASE + 0x40)) /* RM0481 - Table 108 */
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#define RCC_PLLCFGR_PLLSRC_SHIFT (0x0)
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#define RCC_PLLCFGR_PLLSRC_HSI (0x1)
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#define RCC_PLLCFGR_PLLSRC_CSI (0x2)
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#define RCC_PLLCFGR_PLLSRC_HSE (0x3)
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#define RCC_PLLCFGR_PLLRGE_SHIFT (0x2)
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#define RCC_PLLCFGR_RGE_1_2 (0x0) /* Default at boot: 1-2 MHz */
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#define RCC_PLLCFGR_RGE_2_4 (0x1) /* 2-4 MHz */
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#define RCC_PLLCFGR_RGE_4_8 (0x2) /* 4-8 MHz */
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#define RCC_PLLCFGR_RGE_8_16 (0x3) /* 8-16 MHz */
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#define RCC_PLLCFGR_PLL1PEN (1 << 16)
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#define RCC_PLLCFGR_PLL1QEN (1 << 17)
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#define RCC_PLLCFGR_PLL1REN (1 << 18)
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#define RCC_PLLCFGR_PLLFRACEN (1 << 4)
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#define RCC_PLLCFGR_PLLVCOSEL (1 << 5)
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#define RCC_PLLCFGR_PLLM_SHIFT (0x8)
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#define RCC_PLLCFGR_PLLPEN (1 << 16)
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#define RCC_PLLCFGR_PLLQEN (1 << 17)
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#define RCC_PLLCFGR_PLLREN (1 << 18)
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#define RCC_PLLDIVR_DIVN_SHIFT (0)
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#define RCC_PLLDIVR_DIVP_SHIFT (9)
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#define RCC_PLLDIVR_DIVQ_SHIFT (16)
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#define RCC_PLLDIVR_DIVR_SHIFT (24)
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#define RCC_PLLFRACR_FRACN_SHIFT (3)
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#define RCC_APB_PRESCALER_DIV_NONE 0x0 /* 0xx: HCLK not divided */
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#define RCC_APB_PRESCALER_DIV_2 0x4 /* 100: HCLK divided by 2 */
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#define RCC_APB_PRESCALER_DIV_4 0x5 /* 101: HCLK divided by 4 */
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#define RCC_APB_PRESCALER_DIV_8 0x6 /* 110: HCLK divided by 8 */
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#define RCC_APB_PRESCALER_DIV_16 0x7 /* 111: HCLK divided by 16 */
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#define RCC_AHB_PRESCALER_DIV_NONE 0x0 /* 0xxx: SYSCLK not divided */
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#define RCC_AHB_PRESCALER_DIV_2 0x8 /* 1000: SYSCLK divided by 2 */
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#define RCC_AHB_PRESCALER_DIV_4 0x9 /* 1001: SYSCLK divided by 4 */
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#define RCC_AHB_PRESCALER_DIV_8 0xA /* 1010: SYSCLK divided by 8 */
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#define RCC_AHB_PRESCALER_DIV_16 0xB /* 1011: SYSCLK divided by 16 */
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#define RCC_AHB_PRESCALER_DIV_64 0xC /* 1100: SYSCLK divided by 64 */
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#define RCC_AHB_PRESCALER_DIV_128 0xD /* 1101: SYSCLK divided by 128 */
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#define RCC_AHB_PRESCALER_DIV_256 0xE /* 1110: SYSCLK divided by 256 */
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#define RCC_AHB_PRESCALER_DIV_512 0xF /* 1111: SYSCLK divided by 512 */
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#define RCC_CFGR_SW_MSI 0x0
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#define RCC_CFGR_SW_HSI16 0x1
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#define RCC_CFGR_SW_HSE 0x2
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#define RCC_CFGR_SW_PLL 0x3
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#define RCC_PLLCKSELR_PLLSRC_NONE 0x0
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#define RCC_PLLCKSELR_PLLSRC_MSI 0x1
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#define RCC_PLLCKSELR_PLLSRC_HSI16 0x2
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#define RCC_PLLCKSELR_PLLSRC_HSE 0x3
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#define RCC_CCIPR1 (*(volatile uint32_t *)(RCC_BASE + 0xD8))
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#define RCC_CCIPR3 (*(volatile uint32_t *)(RCC_BASE + 0xE0))
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#define RCC_CCIPR1_USART3SEL_SHIFT (6)
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#define RCC_CCIPR1_USART3SEL_MASK (0x7)
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#define RCC_CCIPR3_LPUART1SEL_SHIFT (24)
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#define RCC_CCIPR3_LPUART1SEL_MASK (0x7)
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#define RCC_CRRCR (*(volatile uint32_t *)(RCC_BASE + 0x98))
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#define RCC_CRRCR_HSI48ON (1 << 0)
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#define RCC_CRRCR_HSI48RDY (1 << 1)
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/*** PWR ***/
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/*!< Memory & Instance aliases and base addresses for Non-Secure/Secure peripherals */
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#if TZ_SECURE()
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/*Secure */
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#define PWR_BASE (0x54020800) //RM0481 - Table 3
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#else
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/*Non-Secure */
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#define PWR_BASE (0x44020800) //RM0481 - Table 3
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#endif
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#define PWR_VOSCR (*(volatile uint32_t *)(PWR_BASE + 0x10))
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#define PWR_VOSSR (*(volatile uint32_t *)(PWR_BASE + 0x14))
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#define PWR_VOS_SCALE_0 (0x3 << 4) //RM0481 - 10.11.3
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#define PWR_VOS_SCALE_3 (0x0 << 4) //RM0481 - 10.11.3 - Default on power up
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#define PWR_VOS_MASK (0x3 << 4) //RM0481 - 10.11.3
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#define PWR_VOSRDY (1 << 3) //RM0481 - 10.11.4 - Voltage scaling ready
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#define PWR_CR2 (*(volatile uint32_t *)(PWR_BASE + 0x04))
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#define PWR_CR2_IOSV (1 << 9)
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#define PWR_CR3 (*(volatile uint32_t *)(PWR_BASE + 0x08))
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#define PWR_CR3_UCPD_DBDIS (1 << 14)
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#define PWR_CR4 (*(volatile uint32_t *)(PWR_BASE + 0x0C))
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#define PWR_SR1 (*(volatile uint32_t *)(PWR_BASE + 0x10))
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#define PWR_SR2 (*(volatile uint32_t *)(PWR_BASE + 0x14))
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#define PWR_SR2_VOSF (1 << 10)
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#if TZ_SECURE()
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/*Secure*/
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#define FLASH_BASE (0x50022000) //RM0481 - Table 75
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#define FLASH_KEYR (*(volatile uint32_t *)(FLASH_BASE + 0x08))
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#define FLASH_OPTKEYR (*(volatile uint32_t *)(FLASH_BASE + 0x0C))
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#define FLASH_SR (*(volatile uint32_t *)(FLASH_BASE + 0x24))
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#define FLASH_CR (*(volatile uint32_t *)(FLASH_BASE + 0x2C))
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#define FLASH_SECBB1 ((volatile uint32_t *)(FLASH_BASE + 0x0A0)) /* Array */
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#define FLASH_SECBB2 ((volatile uint32_t *)(FLASH_BASE + 0x1A0)) /* Array */
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#define FLASH_SECBB_NREGS 4 /* Array length for the two above */
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#define FLASH_NS_BASE (0x40022000) //RM0481 - Table 3
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#define FLASH_NS_KEYR (*(volatile uint32_t *)(FLASH_NS_BASE + 0x08))
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#define FLASH_NS_OPTKEYR (*(volatile uint32_t *)(FLASH_NS_BASE + 0x0C))
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#define FLASH_NS_SR (*(volatile uint32_t *)(FLASH_NS_BASE + 0x20))
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#define FLASH_NS_CR (*(volatile uint32_t *)(FLASH_NS_BASE + 0x28))
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#define TZSC_SECCFGR1 *((volatile uint32_t *)(0x50036410))
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#define TZSC_SECCFGR1_USART3SEC (1 << 14) /* USART3 */
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#define TZSC_SECCFGR2 *((volatile uint32_t *)(0x50036414))
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#define TZSC_SECCFGR2_LPUART1SEC (1 << 25) /* LPUART1 */
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/* Mapping FLASH_SECCR for bank swapping */
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#define FLASH_CCR (*(volatile uint32_t *)(FLASH_BASE + 0x34))
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#else
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/* Non-Secure only */
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#define FLASH_BASE (0x40022000) //RM0481 - Table 3
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#define FLASH_KEYR (*(volatile uint32_t *)(FLASH_BASE + 0x04))
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#define FLASH_OPTKEYR (*(volatile uint32_t *)(FLASH_BASE + 0x0C))
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#define FLASH_SR (*(volatile uint32_t *)(FLASH_BASE + 0x20))
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#define FLASH_CR (*(volatile uint32_t *)(FLASH_BASE + 0x28))
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/* Mapping FLASH_NSCCR for bank swapping */
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#define FLASH_CCR (*(volatile uint32_t *)(FLASH_BASE + 0x30))
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#endif
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/* Both secure + non secure */
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#define FLASH_OPTCR (*(volatile uint32_t *)(FLASH_BASE + 0x1C))
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#define FLASH_OPSR (*(volatile uint32_t *)(FLASH_BASE + 0x18))
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#define FLASH_OTPBLR_CUR (*(volatile uint32_t *)(FLASH_BASE + 0x90))
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#define FLASH_OTPBLR_PRG (*(volatile uint32_t *)(FLASH_BASE + 0x94))
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#define FLASH_OPSR_DATA_OP (1 << 21)
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#define FLASH_OPSR_BK_OP (1 << 22)
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#define FLASH_OPSR_SYSF_OP (1 << 23)
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#define FLASH_OPSR_OTP_OP (1 << 24)
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#define FLASH_OPSR_CODE_MASK (0x7 << 29)
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#define FLASH_OPSR_CODE_WRITE (0x1 << 29)
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#define FLASH_OPSR_CODE_OBK_ALT_ERASE (0x2 << 29)
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#define FLASH_OPSR_CODE_SEC_ERASE (0x3 << 29)
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#define FLASH_OPSR_CODE_BANK_ERASE (0x4 << 29)
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#define FLASH_OPSR_CODE_MASS_ERASE (0x5 << 29)
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#define FLASH_OPSR_CODE_OPT_CHANGE (0x6 << 29)
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#define FLASH_OPSR_CODE_OBK_SWAP (0x7 << 29)
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#define FLASH_OPTSR_CUR (*(volatile uint32_t *)(FLASH_BASE + 0x50))
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#define FLASH_OPTSR_PRG (*(volatile uint32_t *)(FLASH_BASE + 0x54))
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#define FLASH_OPTSR_SWAP_BANK (1 << 31)
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/* Register values (for both secure and non secure registers)
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* RM0481 Table 75 */
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#define FLASH_SR_BSY (1 << 0)
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#define FLASH_SR_WBNE (1 << 1)
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#define FLASH_SR_DBNE (1 << 3)
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#define FLASH_SR_EOP (1 << 16)
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#define FLASH_SR_WRPE (1 << 17)
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#define FLASH_SR_PGSE (1 << 18)
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#define FLASH_SR_STRBE (1 << 19)
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#define FLASH_SR_INCE (1 << 20)
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#define FLASH_SR_OPTE (1 << 21)
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#define FLASH_SR_OPTWE (1 << 22)
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#define FLASH_CCR_CLR_BUSY (1 << 0)
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#define FLASH_CCR_CLR_WBNE (1 << 1)
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#define FLASH_CCR_CLR_DBNE (1 << 3)
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#define FLASH_CCR_CLR_EOP (1 << 16)
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#define FLASH_CCR_CLR_WRPE (1 << 17)
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#define FLASH_CCR_CLR_PGSE (1 << 18)
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#define FLASH_CCR_CLR_STRBE (1 << 19)
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#define FLASH_CCR_CLR_INCE (1 << 20)
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#define FLASH_CCR_CLR_OPTE (1 << 21)
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#define FLASH_CCR_CLR_OPTWE (1 << 22)
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#define FLASH_CR_LOCK (1 << 0)
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#define FLASH_CR_PG (1 << 1)
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#define FLASH_CR_SER (1 << 2)
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#define FLASH_CR_BER (1 << 3)
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#define FLASH_CR_FW (1 << 4)
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#define FLASH_CR_STRT (1 << 5)
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#define FLASH_CR_PNB_SHIFT 6
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#define FLASH_CR_PNB_MASK 0x7F
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#define FLASH_CR_MER (1 << 15)
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#define FLASH_CR_EOPIE (1 << 16)
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#define FLASH_CR_WRPERRIE (1 << 17)
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#define FLASH_CR_PGSERRIE (1 << 18)
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#define FLASH_CR_STRBERRIE (1 << 19)
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#define FLASH_CR_INCERRIE (1 << 20)
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#define FLASH_CR_OBKIE (1 << 21)
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#define FLASH_CR_OBKWIE (1 << 22)
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#define FLASH_CR_OPTCHANGEERRIE (1 << 23)
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#define FLASH_CR_BKSEL (1 << 31)
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#define FLASH_ACR (*(volatile uint32_t *)(FLASH_BASE + 0x00))
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#define FLASH_ACR_LATENCY_MASK (0x0F)
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#define FLASH_ACR_WRHIGHFREQ_MASK (0x03)
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#define FLASH_ACR_WRHIGHFREQ_SHIFT (4)
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#define FLASH_OPTCR (*(volatile uint32_t *)(FLASH_BASE + 0x1C))
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#define FLASH_OPTCR_OPTSTRT (1 << 1)
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#define FLASH_OPTCR_OPTLOCK (1 << 0)
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#define FLASH_OPTCR_SWAP_BANK (1 << 31)
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#define FLASHMEM_ADDRESS_SPACE (0x08000000)
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#define FLASH_PAGE_SIZE (0x2000) /* 8KB */
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#define FLASH_BANK2_BASE (0x08100000) /*!< Base address of Flash Bank2 */
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#define BOOTLOADER_SIZE (WOLFBOOT_PARTITION_BOOT_ADDRESS - FLASHMEM_ADDRESS_SPACE)
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#define FLASH_TOP (0x081FFFFF) /*!< FLASH end address (sector 127) */
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#define FLASH_KEY1 (0x45670123U)
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#define FLASH_KEY2 (0xCDEF89ABU)
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#define FLASH_OPTKEY1 (0x08192A3BU)
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#define FLASH_OPTKEY2 (0x4C5D6E7FU)
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/* GPIO*/
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#if (TZ_SECURE())
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#define GPIOA_BASE 0x52020000
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#define GPIOB_BASE 0x52020400
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#define GPIOC_BASE 0x52020800
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#define GPIOD_BASE 0x52020C00
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#define GPIOF_BASE 0x52021400
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#define GPIOG_BASE 0x52021800
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#else
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#define GPIOA_BASE 0x42020000
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#define GPIOB_BASE 0x42020400
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#define GPIOC_BASE 0x42020800
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#define GPIOD_BASE 0x42020C00
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#define GPIOF_BASE 0x42021400
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#define GPIOG_BASE 0x42021800
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#endif
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/* RCC AHB2 Clock Enable Register */
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#define RCC_AHB2_CLOCK_ER (*(volatile uint32_t *)(RCC_BASE + 0x8C ))
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#define GPIOA_AHB2_CLOCK_ER (1 << 0)
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#define GPIOB_AHB2_CLOCK_ER (1 << 1)
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#define GPIOC_AHB2_CLOCK_ER (1 << 2)
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#define GPIOD_AHB2_CLOCK_ER (1 << 3)
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#define GPIOF_AHB2_CLOCK_ER (1 << 5)
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#define GPIOG_AHB2_CLOCK_ER (1 << 6)
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#define TRNG_AHB2_CLOCK_ER (1 << 18)
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#define PKA_AHB2_CLOCK_ER (1 << 19)
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#define SAES_AHB2_CLOCK_ER (1 << 20)
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#define SRAM2_AHB2_CLOCK_ER (1 << 30)
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#define SRAM3_AHB2_CLOCK_ER (1 << 31)
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/* RCC: APB1 and APB2 */
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#define RCC_APB2_CLOCK_ER (*(volatile uint32_t *)(RCC_BASE + 0xA4))
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#define UART1_APB2_CLOCK_ER_VAL (1 << 14)
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#define RCC_APB1L_CLOCK_ER (*(volatile uint32_t *)(RCC_BASE + 0x9C))
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#define UART3_APB1L_CLOCK_ER_VAL (1 << 18)
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/* UART1 */
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#if (TZ_SECURE())
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#define UART1 (0x54002400) /* Using LPUART1 */
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#define UART3 (0x50005800) /* Using USART3 */
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#else
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#define UART1 (0x44002400)
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#define UART3 (0x40004800)
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#endif
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#define UART1_CR1 (*(volatile uint32_t *)(UART1 + 0x00))
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#define UART1_CR2 (*(volatile uint32_t *)(UART1 + 0x04))
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#define UART1_CR3 (*(volatile uint32_t *)(UART1 + 0x08))
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#define UART1_BRR (*(volatile uint32_t *)(UART1 + 0x0c))
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#define UART1_ISR (*(volatile uint32_t *)(UART1 + 0x1c))
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#define UART1_ICR (*(volatile uint32_t *)(UART1 + 0x20))
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#define UART1_RDR (*(volatile uint32_t *)(UART1 + 0x24))
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#define UART1_TDR (*(volatile uint32_t *)(UART1 + 0x28))
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#define UART1_PRE (*(volatile uint32_t *)(UART1 + 0x2C))
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#define UART3_CR1 (*(volatile uint32_t *)(UART3 + 0x00))
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#define UART3_CR2 (*(volatile uint32_t *)(UART3 + 0x04))
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#define UART3_CR3 (*(volatile uint32_t *)(UART3 + 0x08))
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#define UART3_BRR (*(volatile uint32_t *)(UART3 + 0x0c))
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#define UART3_ISR (*(volatile uint32_t *)(UART3 + 0x1c))
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#define UART3_ICR (*(volatile uint32_t *)(UART3 + 0x20))
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#define UART3_RDR (*(volatile uint32_t *)(UART3 + 0x24))
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#define UART3_TDR (*(volatile uint32_t *)(UART3 + 0x28))
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#define UART3_PRE (*(volatile uint32_t *)(UART3 + 0x2C))
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#define UART_CR1_UART_ENABLE (1 << 0)
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#define UART_CR1_OVER8 (1 << 15)
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#define UART_CR1_SYMBOL_LEN (1 << 12)
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#define UART_CR1_PARITY_ENABLED (1 << 10)
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#define UART_CR1_PARITY_ODD (1 << 9)
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#define UART_CR1_TX_ENABLE (1 << 3)
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#define UART_CR1_RX_ENABLE (1 << 2)
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#define UART_CR2_STOPBITS (3 << 12)
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#define UART_CR2_LINEN (1 << 14)
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#define UART_CR2_CLKEN (1 << 11)
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#define UART_CR3_HDSEL (1 << 3)
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#define UART_CR3_DEM (1 << 14)
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#define UART_CR3_IREN (1 << 1)
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#define UART_CR3_RXFTIE (1 << 28)
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#define UART_ISR_TX_EMPTY (1 << 7)
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#define UART_ISR_RX_NOTEMPTY (1 << 5)
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#define UART_EPE (1 << 0) /* Parity error */
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#define UART_EFE (1 << 1) /* Framing error */
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#define UART_ENE (1 << 2) /* Noise error */
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#define UART_ORE (1 << 3) /* Overrun error */
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/* OTP FLASH AREA */
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#define FLASH_OTP_BASE 0x08FFF000
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#define FLASH_OTP_END 0x08FFF7FF
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#define OTP_SIZE 2048
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#define OTP_BLOCKS 32
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/* UART1 pin configuration */
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#define UART1_PIN_AF 7
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#define UART1_RX_PIN 7
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#define UART1_TX_PIN 6
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#define UART3_PIN_AF 7
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#define UART3_RX_PIN 9
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#define UART3_TX_PIN 8
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/* GPIO secure configuration */
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#define GPIO_SECCFGR(base) (*(volatile uint32_t *)(base + 0x30))
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#define LED_AHB2_ENABLE (GPIOG_AHB2_CLOCK_ER | GPIOB_AHB2_CLOCK_ER | \
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GPIOF_AHB2_CLOCK_ER)
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#define LED_BOOT_PIN (4) /* PG4 - Nucleo board - Orange Led */
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#define LED_USR_PIN (0) /* PB0 - Nucleo board - Green Led */
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#define LED_EXTRA_PIN (4) /* PF4 - Nucleo board - Blue Led */
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#endif /* STM32H5_DEF_INCLUDED */
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