mirror of https://github.com/wolfSSL/wolfBoot.git
59 lines
1.6 KiB
Plaintext
59 lines
1.6 KiB
Plaintext
# wolfBoot configuration for NXP S32K142
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#
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# S32K142: Cortex-M4F, 256KB Flash, 32KB SRAM
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# Flash sector size: 2KB
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# Default: RUN mode at 48 MHz (FIRC - internal RC oscillator)
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#
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# Build: cp config/examples/nxp-s32k142.config .config && make
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ARCH?=ARM
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CORTEX_M4?=1
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NO_MPU=1
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TARGET?=s32k1xx
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SIGN?=ECC256
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HASH?=SHA256
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VTOR?=1
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NO_ASM?=0
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EXT_FLASH?=0
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SPI_FLASH?=0
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ALLOW_DOWNGRADE?=0
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# S32K1xx flash requires erase before write (cannot re-program same location)
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# This is required for sector swap trailer flag updates to work correctly
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NVM_FLASH_WRITEONCE?=1
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WOLFBOOT_VERSION?=0
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V?=0
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SPMATH?=1
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RAM_CODE?=1
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DUALBANK_SWAP?=0
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# 2KB sectors (S32K142 only - larger variants use 4KB sectors)
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WOLFBOOT_SECTOR_SIZE?=0x800
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# Memory layout for S32K142 (256KB Flash):
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# Bootloader: 0x00000000 - 0x0000BFFF (48 KB)
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# Boot Partition: 0x0000C000 - 0x00024FFF (100 KB)
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# Update Partition: 0x00025000 - 0x0003DFFF (100 KB)
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# Swap Sector: 0x0003E000 - 0x0003E7FF (2 KB)
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WOLFBOOT_PARTITION_SIZE?=0x19000
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WOLFBOOT_PARTITION_BOOT_ADDRESS?=0xC000
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WOLFBOOT_PARTITION_UPDATE_ADDRESS?=0x25000
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WOLFBOOT_PARTITION_SWAP_ADDRESS?=0x3E000
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# Clock mode: Default is RUN mode with FIRC (48 MHz internal RC)
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# To enable HSRUN mode (112 MHz), uncomment below (requires SOSC + SPLL, not fully implemented):
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#CFLAGS_EXTRA+=-DS32K1XX_CLOCK_HSRUN
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# Optionally enable watchdog
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#CFLAGS_EXTRA+=-DWATCHDOG
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# Flash Option Byte (FOPT) override (default 0xFF)
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# Example: disable RESET_PIN_CFG (use PTA5 as GPIO instead of RESET)
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#CFLAGS_EXTRA+=-DWOLFBOOT_FOPT=0xF7
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# Debugging options (uncomment as needed)
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DEBUG?=0
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DEBUG_SYMBOLS?=0
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DEBUG_UART?=0
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#CFLAGS_EXTRA+=-DDEBUG_HARDFAULT |