mirror of https://github.com/wolfSSL/wolfBoot.git
52 lines
1.7 KiB
Plaintext
52 lines
1.7 KiB
Plaintext
ARCH?=ARM
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TARGET?=psoc_c3
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SIGN?=ECC256
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HASH?=SHA256
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DEBUG?=0
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VTOR?=1
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CORTEX_M33?=1
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TZEN?=0
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NO_ASM?=0
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NO_MPU=1
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EXT_FLASH?=0
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SPI_FLASH?=0
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ALLOW_DOWNGRADE?=0
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# Flags rewrite in place: write_row erases before programming and the HAL does
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# a read-modify-write, so the two-sector write-once scheme is not needed.
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NVM_FLASH_WRITEONCE?=0
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# This family erases flash to 0x00, not 0xFF. Without the inverted polarity
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# the state written by wolfBoot_update_trigger() is indistinguishable from
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# erased flash and no update is ever taken.
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FLAGS_INVERT?=1
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WOLFBOOT_VERSION?=1
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V?=0
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SPMATH?=1
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RAM_CODE?=1
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DUALBANK_SWAP?=0
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DEBUG_UART=1
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# PSOC Control C3, 512 KB internal flash, 512-byte rows. Addresses are in the
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# Secure CBUS alias, which is where code executes; the HAL translates to the
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# Secure SBUS alias for the BootROM flash API.
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#
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# 0x12000000 - 0x1200FFFF wolfBoot (64 KB)
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# 0x12010000 - 0x12026FFF BOOT (0x17000)
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# 0x12027000 - 0x1203DFFF UPDATE (0x17000)
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# 0x1203E000 - 0x1203E1FF SWAP (512 B)
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# 0x12040000 - 0x1207FFFF free for the application
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#
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# The layout stays inside the low 256 KB because the debugger flash algorithms
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# published for this family stop there, so an image staged above it cannot be
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# provisioned. A 128 KB part uses 0xB000 partitions at 0x12008000 / 0x12013000
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# / 0x1201E000.
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#
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# Board wiring is set by make options defaulted in arch.mk for the evaluation
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# kit: PSOC_C3_UART_*, PSOC_C3_SPI_*, PSOC_C3_I2C_* and PSOC_C3_PCLK_HZ. See
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# docs/Targets.md for the full table.
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WOLFBOOT_SECTOR_SIZE?=0x200
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WOLFBOOT_PARTITION_SIZE?=0x17000
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WOLFBOOT_PARTITION_BOOT_ADDRESS?=0x12010000
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WOLFBOOT_PARTITION_UPDATE_ADDRESS?=0x12027000
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WOLFBOOT_PARTITION_SWAP_ADDRESS?=0x1203E000
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