mirror of https://github.com/wolfSSL/wolfBoot.git
222 lines
9.3 KiB
C
222 lines
9.3 KiB
C
/* m2354.h
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*
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* Register definitions for the Nuvoton NuMicro M2354 (Cortex-M23).
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*
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* Copyright (C) 2026 wolfSSL Inc.
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*
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* This file is part of wolfBoot.
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*
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* wolfBoot is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 3 of the License, or
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* (at your option) any later version.
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*
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* wolfBoot is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
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*/
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/* Register definitions transcribed from the M2354 reference manual.
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* wolfBoot does not build against the Nuvoton BSP. */
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#ifndef M2354_DEF_INCLUDED
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#define M2354_DEF_INCLUDED
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#include <stdint.h>
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/* Non-secure alias bit. The FMC ISP engine takes the physical address, so
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* this must be masked off before it reaches ISPADDR. */
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#define NS_OFFSET (0x10000000UL)
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/* Peripheral base addresses */
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#define SYS_BASE (0x40000000UL)
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#define CLK_BASE (0x40000200UL)
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#define FMC_BASE (0x4000C000UL)
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#define SCU_BASE (0x4002F000UL)
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/* UART0 is handed to the non-secure world at boot, where it is only
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* reachable through its non-secure alias. */
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#define UART0_BASE_S (0x40070000UL)
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#ifdef NONSECURE_APP
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# define UART0_BASE (UART0_BASE_S + NS_OFFSET)
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#else
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# define UART0_BASE (UART0_BASE_S)
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#endif
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/* Flash geometry (APROM) */
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#define FLASH_APROM_BASE (0x00000000UL)
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#define FLASH_APROM_END (0x00100000UL)
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#define FLASH_APROM_BANK0_END (0x00080000UL)
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#define FLASH_PAGE_SIZE (0x800UL) /* 2048 byte erase unit */
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/* TrustZone secure/non-secure flash boundary. NSCBA is a flash config
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* word, not a register: this is the address the provisioning script
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* programs. wolfBoot never touches it, and validates the boundary
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* through the live SCU->FNSADDR view instead. */
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#define FMC_NSCBA_BASE (0x00210800UL)
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/* SRAM. TrustZone split follows the Nuvoton default: 96 KB secure, the
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* rest non-secure at its alias. */
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#define SRAM_BASE (0x20000000UL)
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#define SRAM_SIZE (0x00040000UL) /* 256 KB */
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#define SRAM_SECURE_SIZE (0x00018000UL) /* 96 KB */
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#define SRAM_NS_BASE (SRAM_BASE + NS_OFFSET + SRAM_SECURE_SIZE)
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#define SRAM_NS_END (SRAM_BASE + NS_OFFSET + SRAM_SIZE - 1UL)
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/* Non-secure alias of the peripheral space */
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#define PERIPH_NS_BASE (0x50000000UL)
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#define PERIPH_NS_END (0x5FFFFFFFUL)
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/*** SYS ***/
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#define SYS_GPA_MFPL (*(volatile uint32_t *)(SYS_BASE + 0x030))
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#define SYS_REGLCTL (*(volatile uint32_t *)(SYS_BASE + 0x100))
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#define SYS_PLCTL (*(volatile uint32_t *)(SYS_BASE + 0x1F8))
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#define SYS_PLSTS (*(volatile uint32_t *)(SYS_BASE + 0x1FC))
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/* PL0 is the only power level supporting 96 MHz; PL1 tops out at 84 MHz. */
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#define SYS_PLCTL_PLSEL_Msk (0x3UL << 0)
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#define SYS_PLCTL_PLSEL_PL0 (0x0UL << 0)
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#define SYS_PLCTL_WRBUSY (1UL << 7)
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#define SYS_PLSTS_PLCBUSY (1UL << 0)
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/* NuMaker-M2354 routes the Nu-Link2-Me virtual COM port to PA6/PA7. */
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#define SYS_GPA_MFPL_PA6MFP_Pos (24)
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#define SYS_GPA_MFPL_PA6MFP_Msk (0xFUL << SYS_GPA_MFPL_PA6MFP_Pos)
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#define SYS_GPA_MFPL_PA6MFP_UART0_RXD (0x7UL << SYS_GPA_MFPL_PA6MFP_Pos)
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#define SYS_GPA_MFPL_PA7MFP_Pos (28)
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#define SYS_GPA_MFPL_PA7MFP_Msk (0xFUL << SYS_GPA_MFPL_PA7MFP_Pos)
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#define SYS_GPA_MFPL_PA7MFP_UART0_TXD (0x7UL << SYS_GPA_MFPL_PA7MFP_Pos)
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/*** CLK ***/
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#define CLK_PWRCTL (*(volatile uint32_t *)(CLK_BASE + 0x000))
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#define CLK_AHBCLK (*(volatile uint32_t *)(CLK_BASE + 0x004))
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#define CLK_APBCLK0 (*(volatile uint32_t *)(CLK_BASE + 0x008))
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#define CLK_CLKSEL0 (*(volatile uint32_t *)(CLK_BASE + 0x010))
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#define CLK_CLKSEL2 (*(volatile uint32_t *)(CLK_BASE + 0x018))
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#define CLK_CLKDIV0 (*(volatile uint32_t *)(CLK_BASE + 0x020))
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#define CLK_PLLCTL (*(volatile uint32_t *)(CLK_BASE + 0x040))
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#define CLK_STATUS (*(volatile uint32_t *)(CLK_BASE + 0x050))
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#define CLK_PWRCTL_HXTEN (1UL << 0)
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#define CLK_PWRCTL_HIRCEN (1UL << 2)
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#define CLK_STATUS_HXTSTB (1UL << 0)
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#define CLK_STATUS_HIRCSTB (1UL << 4)
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#define CLK_STATUS_PLLSTB (1UL << 2)
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#define CLK_CLKSEL0_HCLKSEL_Pos (0)
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#define CLK_CLKSEL0_HCLKSEL_Msk (0x7UL << CLK_CLKSEL0_HCLKSEL_Pos)
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#define CLK_CLKSEL0_HCLKSEL_PLL (0x2UL << CLK_CLKSEL0_HCLKSEL_Pos)
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#define CLK_CLKSEL0_HCLKSEL_HIRC (0x7UL << CLK_CLKSEL0_HCLKSEL_Pos)
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#define CLK_CLKSEL2_UART0SEL_Pos (16)
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#define CLK_CLKSEL2_UART0SEL_Msk (0x7UL << CLK_CLKSEL2_UART0SEL_Pos)
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#define CLK_CLKSEL2_UART0SEL_HIRC (0x3UL << CLK_CLKSEL2_UART0SEL_Pos)
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#define CLK_CLKDIV0_HCLKDIV_Msk (0xFUL << 0)
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#define CLK_CLKDIV0_UART0DIV_Msk (0xFUL << 8)
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#define CLK_APBCLK0_UART0CKEN (1UL << 16)
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/* Only bank 0 (32 KB) is clocked out of reset. Writes to an unclocked
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* bank are silently discarded, not faulted. */
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#define CLK_AHBCLK_SRAM0CKEN (1UL << 20)
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#define CLK_AHBCLK_SRAM1CKEN (1UL << 21)
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#define CLK_AHBCLK_SRAM2CKEN (1UL << 22)
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/* SRAM bank 0 is the only bank guaranteed live at reset, so wolfBoot links
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* itself entirely within it. */
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/* PLL: 12 MHz HXT to 96 MHz. NR=2, NF=16, NO=2, encoded as NR-1 in
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* [13:9], NF-2 in [8:0], divider 2 as 0x4000, HXT source as 0 in bit 19. */
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#define CLK_PLLCTL_96MHZ_HXT (0x4000UL | ((2UL - 1UL) << 9) | (16UL - 2UL))
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#define CLK_HXT_FREQ (12000000UL)
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#define CLK_HIRC_FREQ (12000000UL)
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/*** UART0 ***/
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#define UART0_DAT (*(volatile uint32_t *)(UART0_BASE + 0x000))
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#define UART0_FIFO (*(volatile uint32_t *)(UART0_BASE + 0x008))
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#define UART0_LINE (*(volatile uint32_t *)(UART0_BASE + 0x00C))
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#define UART0_FIFOSTS (*(volatile uint32_t *)(UART0_BASE + 0x018))
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#define UART0_BAUD (*(volatile uint32_t *)(UART0_BASE + 0x024))
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#define UART0_FUNCSEL (*(volatile uint32_t *)(UART0_BASE + 0x030))
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#define UART_FIFO_RXRST (1UL << 1)
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#define UART_FIFO_TXRST (1UL << 2)
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#define UART_LINE_WLS_8BIT (0x3UL << 0) /* 8 data bits */
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#define UART_LINE_NSB_1BIT (0x0UL << 2) /* 1 stop bit */
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#define UART_LINE_PBE_NONE (0x0UL << 3) /* no parity */
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#define UART_FIFOSTS_TXFULL (1UL << 23)
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#define UART_FIFOSTS_TXEMPTYF (1UL << 28)
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#define UART_BAUD_BAUDM0 (1UL << 28)
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#define UART_BAUD_BAUDM1 (1UL << 29)
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/* Baud mode 2: BRD = ((src + baud/2) / baud) - 2 */
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#define UART_BAUD_MODE2_DIVIDER(src, baud) \
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(((((src) + ((baud) / 2UL)) / (baud)) - 2UL))
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/*** FMC (flash ISP) ***/
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#define FMC_ISPCTL (*(volatile uint32_t *)(FMC_BASE + 0x00))
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#define FMC_ISPADDR (*(volatile uint32_t *)(FMC_BASE + 0x04))
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#define FMC_ISPDAT (*(volatile uint32_t *)(FMC_BASE + 0x08))
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#define FMC_ISPCMD (*(volatile uint32_t *)(FMC_BASE + 0x0C))
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#define FMC_ISPTRG (*(volatile uint32_t *)(FMC_BASE + 0x10))
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#define FMC_CYCCTL (*(volatile uint32_t *)(FMC_BASE + 0x4C))
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/* Flash access cycles: 4 is the setting for HCLK at or above 75 MHz. */
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#define FMC_CYCCTL_CYCLE_Msk (0xFUL << 0)
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#define FMC_CYCCTL_CYCLE_96MHZ (4UL)
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#define FMC_ISPCTL_ISPEN (1UL << 0)
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#define FMC_ISPCTL_APUEN (1UL << 3)
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#define FMC_ISPCTL_ISPFF (1UL << 6)
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#define FMC_ISPTRG_ISPGO (1UL << 0)
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#define FMC_ISPCMD_PROGRAM (0x21UL)
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#define FMC_ISPCMD_PAGE_ERASE (0x22UL)
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#define FMC_ISPCMD_PROGRAM_MUL (0x27UL)
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/* Multi-word program: 16 bytes per ISP command instead of four. */
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#define FMC_MPDAT0 (*(volatile uint32_t *)(FMC_BASE + 0x80))
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#define FMC_MPDAT1 (*(volatile uint32_t *)(FMC_BASE + 0x84))
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#define FMC_MPDAT2 (*(volatile uint32_t *)(FMC_BASE + 0x88))
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#define FMC_MPDAT3 (*(volatile uint32_t *)(FMC_BASE + 0x8C))
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#define FMC_MULTI_WORD_ALIGN (16UL)
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/*** SCU (TrustZone peripheral/SRAM attribution) ***/
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#define SCU_PNSSET(n) (*(volatile uint32_t *)(SCU_BASE + 0x000 + ((n) * 4)))
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#define SCU_SRAMNSSET (*(volatile uint32_t *)(SCU_BASE + 0x024))
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#define SCU_IONSSET(n) (*(volatile uint32_t *)(SCU_BASE + 0x140 + ((n) * 4)))
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/* Read-only live view of NSCBA, as a plain size. */
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#define SCU_FNSADDR (*(volatile uint32_t *)(SCU_BASE + 0x028))
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/* SCU peripheral attribution index for UART0: PNSSET[3] bit 16 */
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#define SCU_UART0_ATTR (96 + 16)
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/* IONSSET is indexed per GPIO port; port A is index 0 */
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#define SCU_PORTA_INDEX (0)
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#define SCU_SRAM_BLOCK_SIZE (16384UL)
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#define SCU_SRAM_BLOCKS (16)
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/* System reset, used by the test application */
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#define AIRCR (*(volatile uint32_t *)(0xE000ED0CUL))
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#define AIRCR_VKEY (0x05FAUL << 16)
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#define AIRCR_SYSRESETREQ (1UL << 2)
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/* ARMv8-M NVIC interrupt target non-secure registers */
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#define NVIC_ITNS(n) (*(volatile uint32_t *)(0xE000E380UL + ((n) * 4)))
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#define UART0_IRQn (36)
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/* Register write-protection key sequence */
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#define SYS_UNLOCK() do { \
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SYS_REGLCTL = 0x59UL; \
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SYS_REGLCTL = 0x16UL; \
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SYS_REGLCTL = 0x88UL; \
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} while (SYS_REGLCTL == 0UL)
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#define SYS_LOCK() do { SYS_REGLCTL = 0UL; } while (0)
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#endif /* M2354_DEF_INCLUDED */
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