mirror of https://github.com/wolfSSL/wolfBoot.git
103 lines
3.9 KiB
C
103 lines
3.9 KiB
C
/* nrf52.h
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*
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* Copyright (C) 2024 wolfSSL Inc.
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*
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* This file is part of wolfBoot.
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*
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* wolfBoot is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 3 of the License, or
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* (at your option) any later version.
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*
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* wolfBoot is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
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*/
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#ifndef _HAL_NRF52_H_
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#define _HAL_NRF52_H_
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/* Assembly helpers */
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#define DMB() __asm__ volatile ("dmb")
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/* Instantiation */
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#define CLOCK_CONTROL_BASE (0x40000000)
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#define NVMC_BASE (0x4001E000)
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/* Flash write/erase control */
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#define NVMC_CONFIG *((volatile uint32_t *)(NVMC_BASE + 0x504))
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#define NVMC_ERASEPAGE *((volatile uint32_t *)(NVMC_BASE + 0x508))
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#define NVMC_READY *((volatile uint32_t *)(NVMC_BASE + 0x400))
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#define NVMC_CONFIG_REN 0
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#define NVMC_CONFIG_WEN 1
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#define NVMC_CONFIG_EEN 2
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#define FLASH_PAGE_SIZE (4096)
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/* Clock control */
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#define TASKS_HFCLKSTART *((volatile uint32_t *)(CLOCK_CONTROL_BASE + 0x000))
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#define TASKS_HFCLKSTOP *((volatile uint32_t *)(CLOCK_CONTROL_BASE + 0x004))
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#define TASKS_HFCLKSTARTED *((volatile uint32_t *)(CLOCK_CONTROL_BASE + 0x100))
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/* GPIO */
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#define GPIO_BASE (0x50000000)
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#define GPIO_OUT *((volatile uint32_t *)(GPIO_BASE + 0x504))
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#define GPIO_OUTSET *((volatile uint32_t *)(GPIO_BASE + 0x508))
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#define GPIO_OUTCLR *((volatile uint32_t *)(GPIO_BASE + 0x50C))
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#define GPIO_DIRSET *((volatile uint32_t *)(GPIO_BASE + 0x518))
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#define GPIO_PIN_CNF ((volatile uint32_t *)(GPIO_BASE + 0x700)) /* Array */
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#define GPIO_CNF_IN 0
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#define GPIO_CNF_OUT 3
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/* UART */
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#define UART0_BASE (0x40002000)
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#define UART0_TASK_STARTTX *((volatile uint32_t *)(UART0_BASE + 0x008))
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#define UART0_TASK_STOPTX *((volatile uint32_t *)(UART0_BASE + 0x00C))
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#define UART0_EVENT_ENDTX *((volatile uint32_t *)(UART0_BASE + 0x120))
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#define UART0_ENABLE *((volatile uint32_t *)(UART0_BASE + 0x500))
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#define UART0_TXD_PTR *((volatile uint32_t *)(UART0_BASE + 0x544))
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#define UART0_TXD_MAXCOUNT *((volatile uint32_t *)(UART0_BASE + 0x548))
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#define UART0_BAUDRATE *((volatile uint32_t *)(UART0_BASE + 0x524))
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#define BAUD_115200 0x01D7E000
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/* SPI */
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#define SPI0 (0x40003000)
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#define SPI1 (0x40004000)
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#define SPI2 (0x40023000)
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#define SPI SPI0
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#define SPI_TASKS_START *((volatile uint32_t *)(SPI + 0x10))
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#define SPI_TASKS_STOP *((volatile uint32_t *)(SPI + 0x14))
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#define SPI_EVENTS_ENDRX *((volatile uint32_t *)(SPI + 0x110))
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#define SPI_EVENTS_END *((volatile uint32_t *)(SPI + 0x118))
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#define SPI_EVENTS_ENDTX *((volatile uint32_t *)(SPI + 0x120))
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#define SPI_EV_RDY *((volatile uint32_t *)(SPI + 0x108))
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#define SPI_INTENSET *((volatile uint32_t *)(SPI + 0x304))
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#define SPI_INTENCLR *((volatile uint32_t *)(SPI + 0x308))
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#define SPI_ENABLE *((volatile uint32_t *)(SPI + 0x500))
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#define SPI_PSEL_SCK *((volatile uint32_t *)(SPI + 0x508))
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#define SPI_PSEL_MOSI *((volatile uint32_t *)(SPI + 0x50C))
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#define SPI_PSEL_MISO *((volatile uint32_t *)(SPI + 0x510))
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#define SPI_RXDATA *((volatile uint32_t *)(SPI + 0x518))
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#define SPI_TXDATA *((volatile uint32_t *)(SPI + 0x51C))
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#define SPI_FREQUENCY *((volatile uint32_t *)(SPI + 0x524))
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#define SPI_CONFIG *((volatile uint32_t *)(SPI + 0x554))
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#define K125 0x02000000
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#define K250 0x04000000
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#define K500 0x08000000
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#define M1 0x10000000
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#define M2 0x20000000
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#define M4 0x40000000
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#define M8 0x80000000
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#endif /* !_HAL_NRF52_H_ */
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