mirror of https://github.com/wolfSSL/wolfBoot.git
526 lines
24 KiB
C
526 lines
24 KiB
C
/* nxp_t2080.h
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*
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* Copyright (C) 2026 wolfSSL Inc.
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*
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* This file is part of wolfBoot.
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*
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* wolfBoot is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 3 of the License, or
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* (at your option) any later version.
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*
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* wolfBoot is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
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*
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* Board support:
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* Default: T2080 RDB (66.66 MHz oscillator, DDR3L SODIMM)
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* BOARD_CW_VPX3152: Curtiss-Wright VPX3-152 (66.667 MHz oscillator,
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* 4GB DDR3L single-rank, 256MB NOR flash at 0xF0000000)
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* BOARD_NAII_68PPC2: NAII 68PPC2 (100 MHz oscillator, 8GB DDR3)
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*
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* NXP T2080E Rev 1.1, e6500 core 2.0, PVR=0x80400120 SVR=0x85380011
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* (confirmed on CW VPX3-152 via U-Boot: md.l 0xfe0e00a0 2)
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*/
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#ifndef NXP_T2080_H
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#define NXP_T2080_H
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#include "nxp_ppc.h"
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/* Uncomment to enable verbose DDR debugging output */
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/* #define DEBUG_DDR */
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/* T2080 System Clock — oscillator input frequency.
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* hal_get_plat_clk() / hal_get_bus_clk() compute the actual frequencies
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* from the CLOCKING registers (PLL ratio × SYS_CLK) when
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* ENABLE_BUS_CLK_CALC is defined. */
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#ifdef BOARD_NAII_68PPC2
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#define SYS_CLK (100000000) /* 100 MHz oscillator (NAII 68PPC2) */
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#else
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#define SYS_CLK (66666667) /* 66.66 MHz oscillator (T2080 RDB / CW VPX3-152) */
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#endif
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/* ---- UART (PC16552D Dual UART) ---- */
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#define BAUD_RATE 115200
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#define UART_SEL 0 /* select UART 0 or 1 */
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#define UART_BASE(n) (CCSRBAR + 0x11C500 + (n * 0x1000))
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#define UART_RBR(n) ((volatile uint8_t*)(UART_BASE(n) + 0)) /* receiver buffer register */
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#define UART_THR(n) ((volatile uint8_t*)(UART_BASE(n) + 0)) /* transmitter holding register */
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#define UART_IER(n) ((volatile uint8_t*)(UART_BASE(n) + 1)) /* interrupt enable register */
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#define UART_IIR(n) ((volatile uint8_t*)(UART_BASE(n) + 2)) /* interrupt ID register */
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#define UART_FCR(n) ((volatile uint8_t*)(UART_BASE(n) + 2)) /* FIFO control register */
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#define UART_LCR(n) ((volatile uint8_t*)(UART_BASE(n) + 3)) /* line control register */
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#define UART_MCR(n) ((volatile uint8_t*)(UART_BASE(n) + 4)) /* modem control register */
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#define UART_LSR(n) ((volatile uint8_t*)(UART_BASE(n) + 5)) /* line status register */
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/* enabled when UART_LCR_DLAB set */
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#define UART_DLB(n) ((volatile uint8_t*)(UART_BASE(n) + 0)) /* divisor least significant byte register */
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#define UART_DMB(n) ((volatile uint8_t*)(UART_BASE(n) + 1)) /* divisor most significant byte register */
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#define UART_FCR_TFR (0x04) /* Transmitter FIFO reset */
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#define UART_FCR_RFR (0x02) /* Receiver FIFO reset */
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#define UART_FCR_FEN (0x01) /* FIFO enable */
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#define UART_LCR_DLAB (0x80) /* Divisor latch access bit */
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#define UART_LCR_WLS (0x03) /* Word length select: 8-bits */
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#define UART_LSR_TEMT (0x40) /* Transmitter empty */
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#define UART_LSR_THRE (0x20) /* Transmitter holding register empty */
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/* ---- IFC (Integrated Flash Controller) - T2080RM 13.3 ---- */
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#define IFC_BASE (CCSRBAR + 0x00124000)
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#define IFC_MAX_BANKS 8
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#define IFC_CSPR_EXT(n) ((volatile uint32_t*)(IFC_BASE + 0x000C + (n * 0xC))) /* Extended Base Address */
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#define IFC_CSPR(n) ((volatile uint32_t*)(IFC_BASE + 0x0010 + (n * 0xC))) /* Chip-select Property */
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#define IFC_AMASK(n) ((volatile uint32_t*)(IFC_BASE + 0x00A0 + (n * 0xC)))
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#define IFC_CSOR(n) ((volatile uint32_t*)(IFC_BASE + 0x0130 + (n * 0xC)))
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#define IFC_CSOR_EXT(n) ((volatile uint32_t*)(IFC_BASE + 0x0134 + (n * 0xC)))
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#define IFC_FTIM0(n) ((volatile uint32_t*)(IFC_BASE + 0x01C0 + (n * 0x30)))
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#define IFC_FTIM1(n) ((volatile uint32_t*)(IFC_BASE + 0x01C4 + (n * 0x30)))
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#define IFC_FTIM2(n) ((volatile uint32_t*)(IFC_BASE + 0x01C8 + (n * 0x30)))
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#define IFC_FTIM3(n) ((volatile uint32_t*)(IFC_BASE + 0x01CC + (n * 0x30)))
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#define IFC_CSPR_PHYS_ADDR(x) (((uint32_t)x) & 0xFFFF0000) /* Physical base address */
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#define IFC_CSPR_PORT_SIZE_8 0x00000080 /* Port Size 8 */
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#define IFC_CSPR_PORT_SIZE_16 0x00000100 /* Port Size 16 */
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#define IFC_CSPR_WP 0x00000040 /* Write Protect */
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#define IFC_CSPR_MSEL_NOR 0x00000000 /* Mode Select - NOR */
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#define IFC_CSPR_MSEL_NAND 0x00000002 /* Mode Select - NAND */
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#define IFC_CSPR_MSEL_GPCM 0x00000004 /* Mode Select - GPCM (General-purpose chip-select machine) */
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#define IFC_CSPR_V 0x00000001 /* Bank Valid */
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/* NOR Timings (IFC clocks) */
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#define IFC_FTIM0_NOR_TACSE(n) (((n) & 0x0F) << 28) /* After address hold cycle */
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#define IFC_FTIM0_NOR_TEADC(n) (((n) & 0x3F) << 16) /* External latch address delay cycles */
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#define IFC_FTIM0_NOR_TAVDS(n) (((n) & 0x3F) << 8) /* Delay between CS assertion */
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#define IFC_FTIM0_NOR_TEAHC(n) (((n) & 0x3F) << 0) /* External latch address hold cycles */
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#define IFC_FTIM1_NOR_TACO(n) (((n) & 0xFF) << 24) /* CS assertion to output enable */
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#define IFC_FTIM1_NOR_TRAD(n) (((n) & 0x3F) << 8) /* read access delay */
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#define IFC_FTIM1_NOR_TSEQ(n) (((n) & 0x3F) << 0) /* sequential read access delay */
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#define IFC_FTIM2_NOR_TCS(n) (((n) & 0x0F) << 24) /* Chip-select assertion setup time */
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#define IFC_FTIM2_NOR_TCH(n) (((n) & 0x0F) << 18) /* Chip-select hold time */
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#define IFC_FTIM2_NOR_TWPH(n) (((n) & 0x3F) << 10) /* Chip-select hold time */
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#define IFC_FTIM2_NOR_TWP(n) (((n) & 0xFF) << 0) /* Write enable pulse width */
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/* GPCM Timings (IFC clocks) */
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#define IFC_FTIM0_GPCM_TACSE(n) (((n) & 0x0F) << 28) /* After address hold cycle */
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#define IFC_FTIM0_GPCM_TEADC(n) (((n) & 0x3F) << 16) /* External latch address delay cycles */
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#define IFC_FTIM0_GPCM_TEAHC(n) (((n) & 0x3F) << 0) /* External latch address hold cycles */
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#define IFC_FTIM1_GPCM_TACO(n) (((n) & 0xFF) << 24) /* CS assertion to output enable */
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#define IFC_FTIM1_GPCM_TRAD(n) (((n) & 0x3F) << 8) /* read access delay */
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#define IFC_FTIM2_GPCM_TCS(n) (((n) & 0x0F) << 24) /* Chip-select assertion setup time */
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#define IFC_FTIM2_GPCM_TCH(n) (((n) & 0x0F) << 18) /* Chip-select hold time */
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#define IFC_FTIM2_GPCM_TWP(n) (((n) & 0xFF) << 0) /* Write enable pulse width */
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/* IFC AMASK - RM Table 13-3 - Count of MSB minus 1 */
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enum ifc_amask_sizes {
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IFC_AMASK_64KB = 0xFFFF0000,
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IFC_AMASK_128KB = 0xFFFE0000,
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IFC_AMASK_256KB = 0xFFFC0000,
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IFC_AMASK_512KB = 0xFFF80000,
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IFC_AMASK_1MB = 0xFFF00000,
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IFC_AMASK_2MB = 0xFFE00000,
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IFC_AMASK_4MB = 0xFFC00000,
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IFC_AMASK_8MB = 0xFF800000,
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IFC_AMASK_16MB = 0xFF000000,
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IFC_AMASK_32MB = 0xFE000000,
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IFC_AMASK_64MB = 0xFC000000,
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IFC_AMASK_128MB = 0xF8000000,
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IFC_AMASK_256MB = 0xF0000000,
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IFC_AMASK_512MB = 0xE0000000,
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IFC_AMASK_1GB = 0xC0000000,
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IFC_AMASK_2GB = 0x80000000,
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IFC_AMASK_4GB = 0x00000000,
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};
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/* ---- NOR Flash ---- */
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#ifdef BOARD_CW_VPX3152
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#define FLASH_BANK_SIZE (256*1024*1024) /* 256MB NOR flash (IFC CS0 AMASK=0xF0000000) */
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#else
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#define FLASH_BANK_SIZE (128*1024*1024) /* 128MB NOR flash */
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#endif
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#define FLASH_PAGE_SIZE (512) /* program buffer (256 bytes per chip x 2 chips) */
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#define FLASH_SECTOR_SIZE (128*1024)
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#define FLASH_SECTORS (FLASH_BANK_SIZE / FLASH_SECTOR_SIZE)
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#define FLASH_CFI_WIDTH 16 /* 8 or 16 */
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/* ---- CPLD ---- */
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/* CPLD is not populated on the NAII 68PPC2 board; define ENABLE_CPLD to enable */
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#define CPLD_BASE 0xFFDF0000
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#define CPLD_BASE_PHYS_HIGH 0xFULL
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#define CPLD_SPARE 0x00
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#define CPLD_SATA_MUX_SEL 0x02
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#define CPLD_BANK_SEL 0x04
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#define CPLD_FW_REV 0x06
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#define CPLD_TTL_RW 0x08
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#define CPLD_TTL_LPBK 0x0A
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#define CPLD_TTL_DATA 0x0C
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#define CPLD_PROC_STATUS 0x0E /* write 1 to enable proc reset function, reset default value is 0 */
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#define CPLD_FPGA_RDY 0x10 /* read only when reg read 0x0DB1 then fpga is ready */
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#define CPLD_PCIE_SW_RESET 0x12 /* write 1 to reset the PCIe switch */
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#define CPLD_WR_TTL_INT_EN 0x14
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#define CPLD_WR_TTL_INT_DIR 0x16
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#define CPLD_INT_STAT 0x18
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#define CPLD_WR_TEMP_ALM_OVRD 0x1A /* write 0 to enable temp shutdown. reset default value is 1 */
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#define CPLD_PWR_DWN_CMD 0x1C
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#define CPLD_TEMP_ALM_INT_STAT 0x1E
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#define CPLD_WR_TEMP_ALM_INT_EN 0x20
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#define CPLD_FLASH_BANK_0 0x00
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#define CPLD_FLASH_BANK_1 0x01
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#define CPLD_DATA(n) ((volatile uint8_t*)(CPLD_BASE + n))
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/* ---- SATA ---- */
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#define SATA_ENBL ((volatile uint32_t*)0xB1003F4C) /* also saw 0xB4003F4C */
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/* ---- Boot Page Translation - T2080RM 4.4.9 ---- */
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#define LCC_BSTRH ((volatile uint32_t*)(CCSRBAR + 0x20)) /* Boot space translation register high */
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#define LCC_BSTRL ((volatile uint32_t*)(CCSRBAR + 0x24)) /* Boot space translation register low */
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#define LCC_BSTAR ((volatile uint32_t*)(CCSRBAR + 0x28)) /* Boot space translation attribute register */
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#define LCC_BSTAR_EN 0x80000000
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#define LCC_BSTAR_LAWTRGT(n) ((n) << 20)
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#define LCC_BSTAR_LAWSZ(n) ((n) & 0x3F)
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/* ---- DCFG (Device Configuration) - T2080RM 6.3 ---- */
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#define DCFG_BASE (CCSRBAR + 0xE0000)
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#define DCFG_DCSR ((volatile uint32_t*)(DCFG_BASE + 0x704)) /* Debug Configuration and Status */
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#define DCFG_DEVDISR1 ((volatile uint32_t*)(DCFG_BASE + 0x070)) /* Device Disable Control 1 */
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#define DCFG_DEVDISR2 ((volatile uint32_t*)(DCFG_BASE + 0x074)) /* Device Disable Control 2 */
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#define DCFG_DEVDISR3 ((volatile uint32_t*)(DCFG_BASE + 0x078)) /* Device Disable Control 3 */
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#define DCFG_DEVDISR4 ((volatile uint32_t*)(DCFG_BASE + 0x07C)) /* Device Disable Control 4 */
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#define DCFG_DEVDISR5 ((volatile uint32_t*)(DCFG_BASE + 0x080)) /* Device Disable Control 5 */
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#define DCFG_BRR ((volatile uint32_t*)(DCFG_BASE + 0xE4)) /* Boot Release Register */
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/* ---- RCPM (Run Control and Power Management) - T2080RM 6.4 ---- */
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#define RCPM_BASE (CCSRBAR + 0xE2000)
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#define RCPM_PCTBENR ((volatile uint32_t*)(RCPM_BASE + 0x1A0)) /* Physical Core Timebase Enable */
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/* ---- Clocking - T2080RM 5.3 ---- */
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#define CLOCKING_BASE (CCSRBAR + 0xE1000)
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#define CLOCKING_CLKCCSR(n) ((volatile uint32_t*)(CLOCKING_BASE + 0x000UL + ((n) * 0x20)))
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#define CLOCKING_PLLCNGSR(n) ((volatile uint32_t*)(CLOCKING_BASE + 0x800UL + ((n) * 0x20))) /* PLL cluster n general status */
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#define CLOCKING_PLLPGSR ((volatile uint32_t*)(CLOCKING_BASE + 0xC00UL)) /* Platform PLL general status */
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#define CLOCKING_PLLDGSR ((volatile uint32_t*)(CLOCKING_BASE + 0xC20UL)) /* DDR PLL general status */
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/* ---- MPIC - T2080RM 24.3 ---- */
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#define PIC_BASE (CCSRBAR + 0x40000)
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#define PIC_WHOAMI ((volatile uint32_t*)(PIC_BASE + 0x0090UL))
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/* ---- DDR (T2080RM 12.4) ---- */
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#ifdef BOARD_NAII_68PPC2
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/* NAII 68PPC2: 8GB discrete DDR3 IM8G08D3EBDG-15E */
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/* 1333.333 MT/s data rate 8 GiB (DDR3, 64-bit, CL=9, ECC on) */
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#define DDR_N_RANKS 2
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#define DDR_RANK_DENS 0x100000000
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#define DDR_SDRAM_WIDTH 64
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#define DDR_EC_SDRAM_W 8
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#define DDR_N_ROW_ADDR 16
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#define DDR_N_COL_ADDR 10
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#define DDR_N_BANKS 8
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#define DDR_EDC_CONFIG 2
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#define DDR_BURSTL_MASK 0x0c
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#define DDR_TCKMIN_X_PS 1500
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#define DDR_TCMMAX_PS 3000
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#define DDR_CASLAT_X 0x000007E0
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#define DDR_TAA_PS 13500
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#define DDR_TRCD_PS 13500
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#define DDR_TRP_PS 13500
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#define DDR_TRAS_PS 36000
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#define DDR_TRC_PS 49500
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#define DDR_TFAW_PS 30000
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#define DDR_TWR_PS 15000
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#define DDR_TRFC_PS 260000
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#define DDR_TRRD_PS 6000
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#define DDR_TWTR_PS 7500
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#define DDR_TRTP_PS 7500
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#define DDR_REF_RATE_PS 7800000
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#elif defined(BOARD_CW_VPX3152)
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/* CW VPX3-152: 4 GB single-rank DDR3L
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* Confirmed from U-Boot: CS0_BNDS=0x000000FF (4GB), CS1_CONFIG bit31=0 (disabled) */
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#define DDR_N_RANKS 1 /* CS0 only; CS1 disabled (CS1_CONFIG=0x00014402) */
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#define DDR_RANK_DENS 0x100000000 /* 4 GB per rank */
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#define DDR_SDRAM_WIDTH 64
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#define DDR_EC_SDRAM_W 8
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#define DDR_N_ROW_ADDR 16
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#define DDR_N_COL_ADDR 10
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#define DDR_N_BANKS 8
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#define DDR_EDC_CONFIG 2
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#define DDR_BURSTL_MASK 0x0c
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#define DDR_TCKMIN_X_PS 1500 /* DDR3-1333 (from TIMING_CFG_3=0x020E1100) */
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#define DDR_TCMMAX_PS 3000
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#define DDR_CASLAT_X 0x000007E0
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#define DDR_TAA_PS 13500
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#define DDR_TRCD_PS 13500
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#define DDR_TRP_PS 13500
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#define DDR_TRAS_PS 36000
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#define DDR_TRC_PS 49500
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#define DDR_TFAW_PS 30000
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#define DDR_TWR_PS 15000
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#define DDR_TRFC_PS 260000
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#define DDR_TRRD_PS 6000
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#define DDR_TWTR_PS 7500
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#define DDR_TRTP_PS 7500
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#define DDR_REF_RATE_PS 7800000
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#else
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/* T2080 RDB: DDR3L SODIMM */
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#define DDR_N_RANKS 2
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#define DDR_RANK_DENS 0x80000000
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#define DDR_SDRAM_WIDTH 64
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#define DDR_EC_SDRAM_W 8
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#define DDR_N_ROW_ADDR 15
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#define DDR_N_COL_ADDR 10
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#define DDR_N_BANKS 8
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#define DDR_EDC_CONFIG 2
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#define DDR_BURSTL_MASK 0x0c
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#define DDR_TCKMIN_X_PS 1125
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#define DDR_TCMMAX_PS 3000
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#define DDR_CASLAT_X 0x000002FC
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#define DDR_TAA_PS 13125
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#define DDR_TRCD_PS 13125
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#define DDR_TRP_PS 13125
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#define DDR_TRAS_PS 34000
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#define DDR_TRC_PS 47125
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#define DDR_TFAW_PS 27000
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#define DDR_TWR_PS 15000
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#define DDR_TRFC_PS 160000
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#define DDR_TRRD_PS 5000
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#define DDR_TWTR_PS 7500
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#define DDR_TRTP_PS 7500
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#define DDR_REF_RATE_PS 7800000
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#endif
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#ifdef BOARD_NAII_68PPC2
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/* DDR register values from working U-Boot on NAII 68PPC2 board */
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#define DDR_CS0_BNDS_VAL 0x000000FF
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#define DDR_CS1_BNDS_VAL 0x010001FF
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#define DDR_CS2_BNDS_VAL 0x0300033F
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#define DDR_CS3_BNDS_VAL 0x0340037F
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#define DDR_CS0_CONFIG_VAL 0x80044402
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#define DDR_CS1_CONFIG_VAL 0x80044402
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#define DDR_CS2_CONFIG_VAL 0x00000202
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#define DDR_CS3_CONFIG_VAL 0x00040202
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#define DDR_CS_CONFIG_2_VAL 0x00000000
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#define DDR_TIMING_CFG_0_VAL 0xFF530004
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#define DDR_TIMING_CFG_1_VAL 0x98906345
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#define DDR_TIMING_CFG_2_VAL 0x0040A114
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#define DDR_TIMING_CFG_3_VAL 0x010A1100
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#define DDR_TIMING_CFG_4_VAL 0x00000001
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#define DDR_TIMING_CFG_5_VAL 0x04402400
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#define DDR_SDRAM_MODE_VAL 0x00441C70
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#define DDR_SDRAM_MODE_2_VAL 0x00980000
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#define DDR_SDRAM_MODE_3_8_VAL 0x00000000
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#define DDR_SDRAM_MODE_3_VAL DDR_SDRAM_MODE_3_8_VAL
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#define DDR_SDRAM_MODE_4_VAL DDR_SDRAM_MODE_3_8_VAL
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#define DDR_SDRAM_MODE_5_VAL DDR_SDRAM_MODE_3_8_VAL
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#define DDR_SDRAM_MODE_6_VAL DDR_SDRAM_MODE_3_8_VAL
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#define DDR_SDRAM_MODE_7_VAL DDR_SDRAM_MODE_3_8_VAL
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#define DDR_SDRAM_MODE_8_VAL DDR_SDRAM_MODE_3_8_VAL
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#define DDR_SDRAM_MD_CNTL_VAL 0x00000000
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#define DDR_SDRAM_CFG_VAL 0xE7040000
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#define DDR_SDRAM_CFG_2_VAL 0x00401000
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#define DDR_SDRAM_INTERVAL_VAL 0x0C300100
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#define DDR_DATA_INIT_VAL 0xDEADBEEF
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#define DDR_SDRAM_CLK_CNTL_VAL 0x02400000
|
||
#define DDR_ZQ_CNTL_VAL 0x89080600
|
||
|
||
/* Write leveling - CRITICAL: board-specific values from U-Boot */
|
||
#define DDR_WRLVL_CNTL_VAL 0x8675F604
|
||
#define DDR_WRLVL_CNTL_2_VAL 0x05060607
|
||
#define DDR_WRLVL_CNTL_3_VAL 0x080A0A0B
|
||
|
||
#define DDR_SDRAM_RCW_1_VAL 0x00000000
|
||
#define DDR_SDRAM_RCW_2_VAL 0x00000000
|
||
|
||
#define DDR_DDRCDR_1_VAL 0x80040000
|
||
#define DDR_DDRCDR_2_VAL 0x00000001
|
||
|
||
#define DDR_ERR_INT_EN_VAL 0x0000001D
|
||
#define DDR_ERR_SBE_VAL 0x00010000
|
||
#elif defined(BOARD_CW_VPX3152)
|
||
/* CW VPX3-152: DDR register values from U-Boot hardware dump */
|
||
#define DDR_CS0_BNDS_VAL 0x000000FF /* CS0: 0-4GB (4GB rank) */
|
||
#define DDR_CS1_BNDS_VAL 0x00000000 /* CS1: disabled */
|
||
#define DDR_CS0_CONFIG_VAL 0x80014402 /* CS0 enabled */
|
||
#define DDR_CS1_CONFIG_VAL 0x00014402 /* CS1 disabled (bit31=0) */
|
||
#define DDR_CS2_BNDS_VAL 0x00000000
|
||
#define DDR_CS3_BNDS_VAL 0x00000000
|
||
#define DDR_CS2_CONFIG_VAL 0x00000000
|
||
#define DDR_CS3_CONFIG_VAL 0x00000000
|
||
#define DDR_CS_CONFIG_2_VAL 0x00000000
|
||
|
||
#define DDR_TIMING_CFG_3_VAL 0x020E1100
|
||
#define DDR_TIMING_CFG_0_VAL 0x8066000F
|
||
#define DDR_TIMING_CFG_1_VAL 0xD0D8B067
|
||
#define DDR_TIMING_CFG_2_VAL 0x0049315A
|
||
#define DDR_TIMING_CFG_4_VAL 0x00000001
|
||
#define DDR_TIMING_CFG_5_VAL 0x05401400
|
||
|
||
#define DDR_SDRAM_MODE_VAL 0x00461014
|
||
#define DDR_SDRAM_MODE_2_VAL 0x00A00000
|
||
#define DDR_SDRAM_MODE_3_8_VAL 0x00000000
|
||
#define DDR_SDRAM_MODE_3_VAL DDR_SDRAM_MODE_3_8_VAL
|
||
#define DDR_SDRAM_MODE_4_VAL DDR_SDRAM_MODE_3_8_VAL
|
||
#define DDR_SDRAM_MODE_5_VAL DDR_SDRAM_MODE_3_8_VAL
|
||
#define DDR_SDRAM_MODE_6_VAL DDR_SDRAM_MODE_3_8_VAL
|
||
#define DDR_SDRAM_MODE_7_VAL DDR_SDRAM_MODE_3_8_VAL
|
||
#define DDR_SDRAM_MODE_8_VAL DDR_SDRAM_MODE_3_8_VAL
|
||
#define DDR_SDRAM_MD_CNTL_VAL 0x00000000
|
||
|
||
#define DDR_SDRAM_CFG_VAL 0xE7240000 /* MEM_EN|SREN|ECC_EN, DDR3 */
|
||
#define DDR_SDRAM_CFG_2_VAL 0x00401000 /* ODT_CFG, NUM_PR=1 */
|
||
|
||
#define DDR_SDRAM_INTERVAL_VAL 0x0E3C071C
|
||
/* ECC scrub pattern. CW U-Boot sets this to 0 (TRACE32 PER capture
|
||
* confirms DDR_DATA_INIT=0 at VxWorks entry); wolfBoot previously
|
||
* used 0xDEADBEEF as a debug "uninitialized" sentinel, which left
|
||
* 0xDEADBEEF in every word VxWorks never touches. VxWorks's _sysInit
|
||
* reads uninitialized memory and uses portions of it as pointers --
|
||
* resulting in unaligned floating-point stores to addresses like
|
||
* 0xFFFFFFFF_FFFFBEEF and a DSI(FP|ST) trap. Match U-Boot: scrub to 0. */
|
||
#define DDR_DATA_INIT_VAL 0x00000000
|
||
#define DDR_SDRAM_CLK_CNTL_VAL 0x01400000
|
||
#define DDR_ZQ_CNTL_VAL 0x8A090700
|
||
|
||
/* Write leveling - board-specific PCB trace delays */
|
||
#define DDR_WRLVL_CNTL_VAL 0x8655F604
|
||
#define DDR_WRLVL_CNTL_2_VAL 0x05030709
|
||
#define DDR_WRLVL_CNTL_3_VAL 0x0E090D08
|
||
|
||
#define DDR_SDRAM_RCW_1_VAL 0x00000000 /* unbuffered DDR3L */
|
||
#define DDR_SDRAM_RCW_2_VAL 0x00000000
|
||
|
||
#define DDR_DDRCDR_1_VAL 0x80000000
|
||
#define DDR_DDRCDR_2_VAL 0x00000001
|
||
|
||
#define DDR_ERR_INT_EN_VAL 0x0000001D
|
||
#define DDR_ERR_SBE_VAL 0x00010000
|
||
#else
|
||
/* T2080 RDB DDR register values from U-Boot register dump.
|
||
* T2080 RDB (default CCSRBAR = 0xFE000000, DDR_BASE = 0xFE008000):
|
||
* md.l 0xfe008000 4; md.l 0xfe008010 4 (CS BNDS)
|
||
* md.l 0xfe008080 4; md.l 0xfe0080c0 4 (CS CONFIG)
|
||
* md.l 0xfe008100 4; md.l 0xfe008160 3 (TIMING)
|
||
* md.l 0xfe008110 8; md.l 0xfe008130 1 (CONFIG/MODE/CLK)
|
||
* md.l 0xfe008170 3; md.l 0xfe008190 2 (WRLVL)
|
||
* md.l 0xfe008200 6; md.l 0xfe008b28 2 (MODE3-8/CDR) */
|
||
#define DDR_CS0_BNDS_VAL 0x000000FF
|
||
#define DDR_CS1_BNDS_VAL 0x000000FF
|
||
#define DDR_CS2_BNDS_VAL 0x00000000
|
||
#define DDR_CS3_BNDS_VAL 0x00000000
|
||
#define DDR_CS0_CONFIG_VAL 0x80044302
|
||
#define DDR_CS1_CONFIG_VAL 0x80004302
|
||
#define DDR_CS2_CONFIG_VAL 0x00000000
|
||
#define DDR_CS3_CONFIG_VAL 0x00000000
|
||
#define DDR_CS_CONFIG_2_VAL 0x00000000
|
||
|
||
#define DDR_TIMING_CFG_3_VAL 0x02081000
|
||
#define DDR_TIMING_CFG_0_VAL 0x9011000E
|
||
#define DDR_TIMING_CFG_1_VAL 0xD0D8EE57
|
||
#define DDR_TIMING_CFG_2_VAL 0x0048E15A
|
||
#define DDR_TIMING_CFG_4_VAL 0x00000001
|
||
#define DDR_TIMING_CFG_5_VAL 0x05401400
|
||
|
||
#define DDR_SDRAM_MODE_VAL 0x00441E14
|
||
#define DDR_SDRAM_MODE_2_VAL 0x00A00000
|
||
#define DDR_SDRAM_MODE_3_VAL 0x00001E14
|
||
#define DDR_SDRAM_MODE_4_VAL 0x00A00000
|
||
#define DDR_SDRAM_MODE_5_VAL 0x00001E14
|
||
#define DDR_SDRAM_MODE_6_VAL 0x00A00000
|
||
#define DDR_SDRAM_MODE_7_VAL 0x00001E14
|
||
#define DDR_SDRAM_MODE_8_VAL 0x00A00000
|
||
#define DDR_SDRAM_MD_CNTL_VAL 0x00000000
|
||
|
||
#define DDR_SDRAM_CFG_VAL 0xE7044000
|
||
#define DDR_SDRAM_CFG_2_VAL 0x00401100
|
||
|
||
#define DDR_SDRAM_INTERVAL_VAL 0x0E38038E
|
||
#define DDR_DATA_INIT_VAL 0xDEADBEEF
|
||
#define DDR_SDRAM_CLK_CNTL_VAL 0x02800000
|
||
#define DDR_ZQ_CNTL_VAL 0x89080600
|
||
|
||
/* Write leveling - board-specific values from U-Boot register dump */
|
||
#define DDR_WRLVL_CNTL_VAL 0x8675F607
|
||
#define DDR_WRLVL_CNTL_2_VAL 0x0808080C
|
||
#define DDR_WRLVL_CNTL_3_VAL 0x0B0C0C09
|
||
|
||
#define DDR_SDRAM_RCW_1_VAL 0x00000000
|
||
#define DDR_SDRAM_RCW_2_VAL 0x00000000
|
||
|
||
#define DDR_DDRCDR_1_VAL 0x80040000
|
||
#define DDR_DDRCDR_2_VAL 0x00000001
|
||
|
||
#define DDR_ERR_INT_EN_VAL 0x0000001D
|
||
#define DDR_ERR_SBE_VAL 0x00010000
|
||
#endif
|
||
|
||
|
||
/* 12.4 DDR Memory Map */
|
||
#define DDR_BASE (CCSRBAR + 0x8000)
|
||
|
||
#define DDR_CS_BNDS(n) ((volatile uint32_t*)(DDR_BASE + 0x000 + (n * 8))) /* Chip select n memory bounds */
|
||
#define DDR_CS_CONFIG(n) ((volatile uint32_t*)(DDR_BASE + 0x080 + (n * 4))) /* Chip select n configuration */
|
||
#define DDR_CS_CONFIG_2(n) ((volatile uint32_t*)(DDR_BASE + 0x0C0 + (n * 4))) /* Chip select n configuration 2 */
|
||
#define DDR_TIMING_CFG_3 ((volatile uint32_t*)(DDR_BASE + 0x100)) /* DDR SDRAM timing configuration 3 */
|
||
#define DDR_TIMING_CFG_0 ((volatile uint32_t*)(DDR_BASE + 0x104)) /* DDR SDRAM timing configuration 0 */
|
||
#define DDR_TIMING_CFG_1 ((volatile uint32_t*)(DDR_BASE + 0x108)) /* DDR SDRAM timing configuration 1 */
|
||
#define DDR_TIMING_CFG_2 ((volatile uint32_t*)(DDR_BASE + 0x10C)) /* DDR SDRAM timing configuration 2 */
|
||
#define DDR_SDRAM_CFG ((volatile uint32_t*)(DDR_BASE + 0x110)) /* DDR SDRAM control configuration */
|
||
#define DDR_SDRAM_CFG_2 ((volatile uint32_t*)(DDR_BASE + 0x114)) /* DDR SDRAM control configuration 2 */
|
||
#define DDR_SDRAM_MODE ((volatile uint32_t*)(DDR_BASE + 0x118)) /* DDR SDRAM mode configuration */
|
||
#define DDR_SDRAM_MODE_2 ((volatile uint32_t*)(DDR_BASE + 0x11C)) /* DDR SDRAM mode configuration 2 */
|
||
#define DDR_SDRAM_MD_CNTL ((volatile uint32_t*)(DDR_BASE + 0x120)) /* DDR SDRAM mode control */
|
||
#define DDR_SDRAM_INTERVAL ((volatile uint32_t*)(DDR_BASE + 0x124)) /* DDR SDRAM interval configuration */
|
||
#define DDR_DATA_INIT ((volatile uint32_t*)(DDR_BASE + 0x128)) /* DDR training initialization value */
|
||
#define DDR_SDRAM_CLK_CNTL ((volatile uint32_t*)(DDR_BASE + 0x130)) /* DDR SDRAM clock control */
|
||
#define DDR_INIT_ADDR ((volatile uint32_t*)(DDR_BASE + 0x148)) /* DDR training initialization address */
|
||
#define DDR_INIT_EXT_ADDR ((volatile uint32_t*)(DDR_BASE + 0x14C)) /* DDR training initialization extended address */
|
||
#define DDR_TIMING_CFG_4 ((volatile uint32_t*)(DDR_BASE + 0x160)) /* DDR SDRAM timing configuration 4 */
|
||
#define DDR_TIMING_CFG_5 ((volatile uint32_t*)(DDR_BASE + 0x164)) /* DDR SDRAM timing configuration 5 */
|
||
#define DDR_TIMING_CFG_6 ((volatile uint32_t*)(DDR_BASE + 0x168)) /* DDR SDRAM timing configuration 6 */
|
||
#define DDR_ZQ_CNTL ((volatile uint32_t*)(DDR_BASE + 0x170)) /* DDR ZQ calibration control */
|
||
#define DDR_WRLVL_CNTL ((volatile uint32_t*)(DDR_BASE + 0x174)) /* DDR write leveling control */
|
||
#define DDR_SR_CNTR ((volatile uint32_t*)(DDR_BASE + 0x17C)) /* DDR Self Refresh Counter */
|
||
#define DDR_SDRAM_RCW_1 ((volatile uint32_t*)(DDR_BASE + 0x180)) /* DDR Register Control Word 1 */
|
||
#define DDR_SDRAM_RCW_2 ((volatile uint32_t*)(DDR_BASE + 0x184)) /* DDR Register Control Word 2 */
|
||
#define DDR_WRLVL_CNTL_2 ((volatile uint32_t*)(DDR_BASE + 0x190)) /* DDR write leveling control 2 */
|
||
#define DDR_WRLVL_CNTL_3 ((volatile uint32_t*)(DDR_BASE + 0x194)) /* DDR write leveling control 3 */
|
||
#define DDR_SDRAM_MODE_3 ((volatile uint32_t*)(DDR_BASE + 0x200)) /* DDR SDRAM mode configuration 3 */
|
||
#define DDR_SDRAM_MODE_4 ((volatile uint32_t*)(DDR_BASE + 0x204)) /* DDR SDRAM mode configuration 4 */
|
||
#define DDR_SDRAM_MODE_5 ((volatile uint32_t*)(DDR_BASE + 0x208)) /* DDR SDRAM mode configuration 5 */
|
||
#define DDR_SDRAM_MODE_6 ((volatile uint32_t*)(DDR_BASE + 0x20C)) /* DDR SDRAM mode configuration 6 */
|
||
#define DDR_SDRAM_MODE_7 ((volatile uint32_t*)(DDR_BASE + 0x210)) /* DDR SDRAM mode configuration 7 */
|
||
#define DDR_SDRAM_MODE_8 ((volatile uint32_t*)(DDR_BASE + 0x214)) /* DDR SDRAM mode configuration 8 */
|
||
#define DDR_DDRCDR_1 ((volatile uint32_t*)(DDR_BASE + 0xB28)) /* DDR Control Driver Register 1 */
|
||
#define DDR_DDRCDR_2 ((volatile uint32_t*)(DDR_BASE + 0xB2C)) /* DDR Control Driver Register 2 */
|
||
#define DDR_DDRDSR_1 ((volatile uint32_t*)(DDR_BASE + 0xB20)) /* DDR Debug Status Register 1 */
|
||
#define DDR_DDRDSR_2 ((volatile uint32_t*)(DDR_BASE + 0xB24)) /* DDR Debug Status Register 2 */
|
||
#define DDR_ERR_DETECT ((volatile uint32_t*)(DDR_BASE + 0xE40)) /* Memory error detect */
|
||
#define DDR_ERR_DISABLE ((volatile uint32_t*)(DDR_BASE + 0xE44)) /* Memory error disable */
|
||
#define DDR_ERR_INT_EN ((volatile uint32_t*)(DDR_BASE + 0xE48)) /* Memory error interrupt enable */
|
||
#define DDR_ERR_SBE ((volatile uint32_t*)(DDR_BASE + 0xE58)) /* Single-Bit ECC memory error management */
|
||
|
||
#define DDR_SDRAM_CFG_MEM_EN 0x80000000 /* SDRAM interface logic is enabled */
|
||
#define DDR_SDRAM_CFG_BI 0x00000001 /* Bypass initialization */
|
||
#define DDR_SDRAM_CFG_2_D_INIT 0x00000010 /* data initialization in progress */
|
||
|
||
#endif /* NXP_T2080_H */
|