mirror of https://github.com/wolfSSL/wolfBoot.git
109 lines
2.5 KiB
C
109 lines
2.5 KiB
C
/* pic32cz.c
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*
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* Copyright (C) 2021 wolfSSL Inc.
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*
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* This file is part of wolfBoot.
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*
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* wolfBoot is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 3 of the License, or
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* (at your option) any later version.
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*
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* wolfBoot is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
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*/
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#include "image.h"
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#include <stdint.h>
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#include <string.h>
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#include <hal/pic32c.h>
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#define SUPC_BASE (0x44020000U)
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#define SUPC_VREGCTRL (*(volatile uint32_t *)(SUPC_BASE + 0x1CU))
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#define SUPC_STATUS (*(volatile uint32_t *)(SUPC_BASE + 0x0CU))
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#define SUPC_VREGCTRL_AVREGEN_PLLREG_EN (4)
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#define SUPC_VREGCTRL_AVREGEN_SHIFT (16)
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#define SUPC_STATUS_ADDVREGRDY_PLL (4)
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#define SUPC_STATUS_ADDVREGRDY_SHIFT (8)
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static void pic32_supc_vreg_pll_enable(void)
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{
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uint32_t reg;
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SUPC_VREGCTRL |= SUPC_VREGCTRL_AVREGEN_PLLREG_EN
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<< SUPC_VREGCTRL_AVREGEN_SHIFT;
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/* wait for the vreg to be ready */
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while (!(SUPC_STATUS &
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(SUPC_STATUS_ADDVREGRDY_PLL << SUPC_STATUS_ADDVREGRDY_SHIFT))) {}
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}
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#ifdef DUALBANK_SWAP
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void hal_flash_dualbank_swap(void)
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{
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pic32_flash_dualbank_swap();
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}
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#endif /* DUALBANK_SWAP */
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int hal_flash_write(uint32_t address, const uint8_t *data, int len)
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{
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return pic32_flash_write(address, data, len);
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}
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void hal_flash_unlock(void)
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{
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pic32_fcw_grab();
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}
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void hal_flash_lock(void)
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{
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pic32_fcw_release();
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}
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int hal_flash_erase(uint32_t addr, int len)
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{
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return pic32_flash_erase(addr, len);
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}
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static void pic32_delay_cnt(uint32_t ticks)
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{
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uint32_t i = 0;
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for (i = 0; i < ticks; i++) {
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__asm__("nop");
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}
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}
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void hal_init(void)
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{
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#if defined(TEST_CLOCK)
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pic32_clock_test(48000000);
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#endif
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pic32_supc_vreg_pll_enable();
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pic32_clock_pll0_init(12, 225, 1, 3);
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pic32_clock_gclk_gen0(2, 1);
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pic32_delay_cnt(700);
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#if defined(TEST_FLASH)
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pic32_flash_test();
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while (1) {}
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#endif
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#if defined(TEST_CLOCK)
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pic32_clock_test(300000000);
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pic32_clock_reset();
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pic32_clock_test(48000000);
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while (1) {};
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#endif
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}
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void hal_prepare_boot(void)
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{
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pic32_clock_reset();
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}
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