mirror of https://github.com/wolfSSL/wolfBoot.git
332 lines
15 KiB
C
332 lines
15 KiB
C
/* psoc_e8.h
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*
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* Register definitions for Infineon PSOC Edge E8 (CAT1D, Cortex-M33).
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*
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* Copyright (C) 2026 wolfSSL Inc.
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*
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* This file is part of wolfBoot.
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*
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* wolfBoot is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 3 of the License, or
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* (at your option) any later version.
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*
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* wolfBoot is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
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*/
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#ifndef PSOC_E8_H_INCLUDED
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#define PSOC_E8_H_INCLUDED
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#include <stdint.h>
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/* A host-built unit test cannot assemble the barriers; the compiler barrier
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* alone stands in there. */
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#if defined(__arm__) || defined(__ARM_ARCH)
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#define ISB() __asm__ volatile ("isb" ::: "memory")
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#define DSB() __asm__ volatile ("dsb" ::: "memory")
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#else
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#define ISB() __asm__ volatile ("" ::: "memory")
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#define DSB() __asm__ volatile ("" ::: "memory")
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#endif
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/* Each memory has four aliases (S/NS x code/system bus). Within an SMIF
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* window the low 26 bits are the device offset. */
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#define PSOC_E8_SMIF_WINDOW (0x04000000UL)
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#define PSOC_E8_RRAM_SBUS_S (0x32000000UL)
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#define PSOC_E8_RRAM_SIZE (0x00080000UL)
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/* Build options, defaulted for KIT_PSE84_AI. The console is SCB2 on P6.5 (RX)
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* / P6.7 (TX), the KitProg3 COM port; its clock destination is
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* PCLK_SCB2_CLOCK_SCB_EN (group 1, index 1). wolfBoot leaves the clocks as
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* extended boot sets them: CLK_HF0 (CM33) 200 MHz, CLK_HF10 100 MHz. */
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#ifndef PSOC_E8_UART_SCB
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#define PSOC_E8_UART_SCB 2
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#endif
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#ifndef PSOC_E8_UART_PORT
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#define PSOC_E8_UART_PORT 6
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#endif
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#ifndef PSOC_E8_UART_RX_PIN
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#define PSOC_E8_UART_RX_PIN 5
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#endif
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#ifndef PSOC_E8_UART_TX_PIN
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#define PSOC_E8_UART_TX_PIN 7
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#endif
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#ifndef PSOC_E8_UART_HSIOM_SEL
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#define PSOC_E8_UART_HSIOM_SEL 20
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#endif
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#ifndef PSOC_E8_UART_PCLK_GR
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#define PSOC_E8_UART_PCLK_GR 1
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#endif
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#ifndef PSOC_E8_UART_PCLK_IDX
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#define PSOC_E8_UART_PCLK_IDX 1
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#endif
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#ifndef PSOC_E8_UART_PCLK_DIV
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#define PSOC_E8_UART_PCLK_DIV 0
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#endif
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#ifndef PSOC_E8_UART_BAUD
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#define PSOC_E8_UART_BAUD 115200UL
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#endif
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#define PSOC_E8_UART_OVS 8UL
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#ifndef PSOC_E8_PCLK_HZ
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#define PSOC_E8_PCLK_HZ 100000000UL
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#endif
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#ifndef PSOC_E8_CPU_HZ
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#define PSOC_E8_CPU_HZ 200000000UL
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#endif
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/* QSPI NOR erase sector. */
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#ifndef PSOC_E8_QSPI_SECTOR_SIZE
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#define PSOC_E8_QSPI_SECTOR_SIZE (0x40000UL)
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#endif
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#ifndef PSOC_E8_RRAM_TIMEOUT
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#define PSOC_E8_RRAM_TIMEOUT (1000000UL)
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#endif
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/* Peripherals, Secure alias. */
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#define PERI0_BASE (0x52000000UL)
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#define PERI_PCLK0_BASE (0x52040000UL)
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#define HSIOM_BASE (0x52800000UL)
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#define GPIO_BASE (0x52810000UL)
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/* A slave in a gated PERI group bus-faults on access. */
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#define PSOC_E8_PERI_GR_SCB 1
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#define PERI_GR_SL_CTL(g) \
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(*(volatile uint32_t *)(PERI0_BASE + 0x4000UL + \
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((uint32_t)(g) * 0x40UL) + 0x10UL))
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#define PERI_GR_SL_CTL2(g) \
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(*(volatile uint32_t *)(PERI0_BASE + 0x4000UL + \
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((uint32_t)(g) * 0x40UL) + 0x14UL))
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/* PERI_PCLK: 0x2000 per group; dividers by number, CLOCK_CTL by destination. */
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#define PERI_PCLK_GR(g) (PERI_PCLK0_BASE + ((uint32_t)(g) * 0x2000UL))
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#define PERI_PCLK_DIV_CMD(g) (*(volatile uint32_t *)(PERI_PCLK_GR(g)))
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#define PERI_PCLK_CLOCK_CTL(g,i) \
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(*(volatile uint32_t *)(PERI_PCLK_GR(g) + 0xC00UL + ((uint32_t)(i) * 4UL)))
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#define PERI_PCLK_DIV_16_5_CTL(g,d) \
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(*(volatile uint32_t *)(PERI_PCLK_GR(g) + 0x1800UL + ((uint32_t)(d) * 4UL)))
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#define PERI_PCLK_DIV_16_5_EN (1UL << 0)
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#define PERI_PCLK_DIV_16_5_FRAC_Pos (3U)
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#define PERI_PCLK_DIV_16_5_INT_Pos (8U)
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#define PERI_PCLK_DIV_TYPE_16_5 (2UL)
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#define PERI_PCLK_CLOCK_CTL_TYPE_Pos (8U)
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/* A divider's EN bit is status only; DIV_CMD starts it. PA_TYPE 3 with
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* PA_DIV 0xFF selects no phase alignment. */
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#define PERI_PCLK_DIV_CMD_ENABLE (1UL << 31)
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#define PERI_PCLK_DIV_CMD_PA_NONE ((3UL << 24) | (0xFFUL << 16))
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#define PERI_PCLK_DIV_CMD_TYPE_Pos (8U)
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#ifndef PSOC_E8_PERI_TIMEOUT
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#define PSOC_E8_PERI_TIMEOUT (1000000UL)
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#endif
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/* HSIOM: 0x10 per port, one mux byte per pin (pins 4-7 in PORT_SEL1). */
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#define HSIOM_PORT_SEL(p, pin) \
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(*(volatile uint32_t *)(HSIOM_BASE + ((uint32_t)(p) * 0x10UL) + \
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(((uint32_t)(pin) < 4U) ? 0x00UL : 0x04UL)))
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#define HSIOM_SEL_SHIFT(pin) ((((uint32_t)(pin)) & 3U) * 8U)
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/* 1 marks a pin non-secure, and secure writes to its HSIOM/GPIO are then
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* ignored, so it is cleared first. */
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#define HSIOM_SECURE_PRT_NSMASK(p) \
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(*(volatile uint32_t *)(HSIOM_BASE + 0x1000UL + ((uint32_t)(p) * 0x10UL)))
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/* GPIO: 0x80 per port, 4 drive-mode bits per pin in CFG. */
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#define GPIO_PRT_CFG(p) \
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(*(volatile uint32_t *)(GPIO_BASE + ((uint32_t)(p) * 0x80UL) + 0x44UL))
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#define GPIO_CFG_DM_HIGHZ (0x8UL) /* input buffer on, no drive */
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#define GPIO_CFG_DM_STRONG (0x6UL) /* strong drive, input buffer off */
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#define GPIO_CFG_DM_MASK (0xFUL)
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/* SCB2-SCB11 are contiguous; SCB0 and SCB1 are not. */
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#define PSOC_E8_SCB_BASE(n) \
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((n) == 0 ? 0x52990000UL : (n) == 1 ? 0x52D00000UL : \
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(0x52980000UL + ((uint32_t)(n) * 0x10000UL)))
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#define SCB_CTRL(b) (*(volatile uint32_t *)((b) + 0x000UL))
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#define SCB_UART_CTRL(b) (*(volatile uint32_t *)((b) + 0x040UL))
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#define SCB_UART_TX_CTRL(b) (*(volatile uint32_t *)((b) + 0x044UL))
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#define SCB_UART_RX_CTRL(b) (*(volatile uint32_t *)((b) + 0x048UL))
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#define SCB_TX_CTRL(b) (*(volatile uint32_t *)((b) + 0x200UL))
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#define SCB_TX_FIFO_CTRL(b) (*(volatile uint32_t *)((b) + 0x204UL))
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#define SCB_TX_FIFO_STATUS(b) (*(volatile uint32_t *)((b) + 0x208UL))
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#define SCB_TX_FIFO_WR(b) (*(volatile uint32_t *)((b) + 0x240UL))
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#define SCB_RX_CTRL(b) (*(volatile uint32_t *)((b) + 0x300UL))
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#define SCB_RX_FIFO_CTRL(b) (*(volatile uint32_t *)((b) + 0x304UL))
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#define SCB_CTRL_ENABLED (1UL << 31)
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#define SCB_CTRL_MODE_UART (2UL << 24)
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#define SCB_CTRL_OVS_MASK (0xFUL)
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#define SCB_DATA_WIDTH(n) ((uint32_t)((n) - 1))
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#define SCB_TX_FIFO_USED_Msk (0x1FFUL)
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#define SCB_TX_FIFO_SR_VALID_Msk (1UL << 15)
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#define SCB_TX_FIFO_SAFE_DEPTH (8UL)
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/* SMIF0: MMIO command FIFOs and per-device XIP setup in the core block, the
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* XIP line cache in its own block. */
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#define SMIF0_CACHE_BASE (0x54450000UL)
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#define SMIF0_CORE_BASE (0x54460000UL)
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#define SMIF_STATUS (*(volatile uint32_t *)(SMIF0_CORE_BASE + 0x004UL))
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#define SMIF_TX_CMD_STATUS (*(volatile uint32_t *)(SMIF0_CORE_BASE + 0x048UL))
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#define SMIF_TX_CMD_WR (*(volatile uint32_t *)(SMIF0_CORE_BASE + 0x050UL))
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#define SMIF_TX_DATA_STATUS (*(volatile uint32_t *)(SMIF0_CORE_BASE + 0x088UL))
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#define SMIF_TX_DATA_WR1 (*(volatile uint32_t *)(SMIF0_CORE_BASE + 0x090UL))
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#define SMIF_RX_DATA_STATUS (*(volatile uint32_t *)(SMIF0_CORE_BASE + 0x0C4UL))
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#define SMIF_RX_DATA_RD1 (*(volatile uint32_t *)(SMIF0_CORE_BASE + 0x0D0UL))
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#define SMIF_SLOW_CA_CMD (*(volatile uint32_t *)(SMIF0_CORE_BASE + 0x108UL))
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#define SMIF_FAST_CA_CMD (*(volatile uint32_t *)(SMIF0_CORE_BASE + 0x188UL))
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#define SMIF_DEVICE_CTL(n) \
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(*(volatile uint32_t *)(SMIF0_CORE_BASE + 0x800UL + ((n) * 0x80UL)))
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#define SMIF_DEVICE_ADDR_CTL(n) \
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(*(volatile uint32_t *)(SMIF0_CORE_BASE + 0x820UL + ((n) * 0x80UL)))
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#define SMIF_DEVICES 4
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#define SMIF_DEVICE_CTL_ENABLED (1UL << 31)
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#define SMIF_STATUS_BUSY (1UL << 31)
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#define SMIF_CA_CMD_INV (1UL << 0)
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#define SMIF_FIFO_USED_Msk (0xFUL)
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#define SMIF_FIFO_DEPTH (8UL)
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/* TX_CMD_MMIO_FIFO_WR: MODE[26:24], one-hot SS[23:20], LAST_BYTE[19] (release
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* select), WIDTH[17:16], byte[7:0]; count entries hold count - 1 in [15:0]. */
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#define SMIF_CMD_MODE_TX (0UL << 24)
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#define SMIF_CMD_MODE_TX_COUNT (1UL << 24)
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#define SMIF_CMD_MODE_RX_COUNT (2UL << 24)
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#define SMIF_CMD_SS(dev) ((1UL << (dev)) << 20)
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#define SMIF_CMD_LAST (1UL << 19)
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#define SMIF_CACHE_MAINT_ALL \
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(*(volatile uint32_t *)(SMIF0_CACHE_BASE + 0x20UL))
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#define SMIF_CACHE_MAINT_STATUS \
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(*(volatile uint32_t *)(SMIF0_CACHE_BASE + 0x28UL))
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#define SMIF_CACHE_INVALIDATE_ALL (1UL << 1)
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#define SMIF_CACHE_MAINT_ONGOING (1UL << 2)
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/* CM33 instruction cache. */
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#define ICACHE0_CMD (*(volatile uint32_t *)(0x52223008UL))
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#define ICACHE_CMD_INV (1UL << 0)
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/* RRAM indirect write: select the 16-byte block in NVM_ADDR, write its four
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* words at the mapped address, then STARTOP. */
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#define RRAMC_PC_MASK (*(volatile uint32_t *)(0x52210020UL))
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#define RRAMC_NVM_STATUS (*(volatile uint32_t *)(0x52213000UL))
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#define RRAMC_NVM_PROG (*(volatile uint32_t *)(0x52213004UL))
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#define RRAMC_NVM_ADDR (*(volatile uint32_t *)(0x52213008UL))
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#define RRAMC_PC_MASK_PC_LOCK_Msk (0xFUL << 28)
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#define RRAMC_NVM_STATUS_BUSY (1UL << 0)
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#define RRAMC_NVM_STATUS_VERR_Pos (2U)
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#define RRAMC_NVM_STATUS_VERR_Msk (0x7UL << 2)
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#define RRAMC_NVM_STATUS_ECC4MRD (1UL << 19)
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#define RRAMC_NVM_PROG_ACTION_Msk (0xFUL)
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#define RRAMC_NVM_PROG_IDLE (0UL)
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#define RRAMC_NVM_PROG_IND_WRITE (1UL)
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#define RRAMC_NVM_PROG_STARTOP (0x3UL << 14)
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#define RRAM_BLOCK_SIZE (16U)
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#define RRAM_WRITE_TRIALS (3U)
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/* IPC channel 2 serialises RRAM writers (vendor erratum workaround); reading
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* ACQUIRE attempts the lock. */
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#define IPC0_RRAM_ACQUIRE (*(volatile uint32_t *)(0x522A0040UL))
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#define IPC0_RRAM_RELEASE (*(volatile uint32_t *)(0x522A0044UL))
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#define IPC_ACQUIRE_SUCCESS (1UL << 31)
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#define AIRCR (*(volatile uint32_t *)(0xE000ED0CUL))
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#define AIRCR_VKEY (0x05FAUL << 16)
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#define AIRCR_SYSRESETREQ (1UL << 2)
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/* CM33 cycle counter, the time base for hal_get_timer_us(). */
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#define DEMCR (*(volatile uint32_t *)(0xE000EDFCUL))
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#define DEMCR_TRCENA (1UL << 24)
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#define DWT_CTRL (*(volatile uint32_t *)(0xE0001000UL))
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#define DWT_CTRL_CYCCNTENA (1UL << 0)
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#define DWT_CYCCNT (*(volatile uint32_t *)(0xE0001004UL))
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/* SPI NOR commands. */
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#define NOR_CMD_RDSR (0x05U)
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#define NOR_CMD_CLPEF (0x82U) /* clear program/erase failure */
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#define NOR_SR_E_ERR (1U << 5)
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#define NOR_SR_P_ERR (1U << 6)
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/* Memory protection controllers, ROT view. Each LUT word holds eight 4-bit
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* entries per block: bit 0 Non-secure, bit 1 read, bit 2 write. */
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#define RAMC1_MPC_BASE (0x52244000UL)
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#define SMIF0_AHB_MPC_BASE (0x54454000UL)
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#define MPC_ROT_CTRL(b) (*(volatile uint32_t *)((b) + 0x200UL))
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#define MPC_ROT_BLK_MAX(b) (*(volatile uint32_t *)((b) + 0x208UL))
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#define MPC_ROT_BLK_CFG(b) (*(volatile uint32_t *)((b) + 0x20CUL))
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#define MPC_ROT_BLK_IDX(b) (*(volatile uint32_t *)((b) + 0x210UL))
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#define MPC_ROT_BLK_PC(b) (*(volatile uint32_t *)((b) + 0x214UL))
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#define MPC_ROT_BLK_LUT(b) (*(volatile uint32_t *)((b) + 0x218UL))
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#define MPC_ROT_CTRL_AUTO_INC (1UL << 8)
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#define MPC_ROT_BLK_CFG_SIZE_Msk (0xFUL)
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#define MPC_ROT_BLK_CFG_INIT_BUSY (1UL << 31)
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#define MPC_ROT_BLKS_PER_IDX (8U)
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#define MPC_ROT_NS_RW (0x7UL)
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/* Protection context of the CM33, Secure and Non-secure alike. */
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#define PSOC_E8_PC_CM33 (2U)
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/* SAU */
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#define SAU_CTRL (*(volatile uint32_t *)(0xE000EDD0UL))
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#define SAU_RNR (*(volatile uint32_t *)(0xE000EDD8UL))
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#define SAU_RBAR (*(volatile uint32_t *)(0xE000EDDCUL))
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#define SAU_RLAR (*(volatile uint32_t *)(0xE000EDE0UL))
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#define SAU_CTRL_ENABLE (1UL << 0)
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#define SAU_RLAR_ENABLE (1UL << 0)
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#define SAU_RLAR_NSC (1UL << 1)
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/* Crypto block TRNG, used to seed the Secure world's DRBG. */
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#define CRYPTO_BASE (0x52440000UL)
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#define CRYPTO_CTL (*(volatile uint32_t *)(CRYPTO_BASE + 0x000UL))
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#define CRYPTO_INTR (*(volatile uint32_t *)(CRYPTO_BASE + 0x100UL))
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/* INTR flags are write-one-to-clear. */
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#define CRYPTO_INTR_CLR(m) (CRYPTO_INTR = (m))
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#define CRYPTO_TR_CTL0 (*(volatile uint32_t *)(CRYPTO_BASE + 0x280UL))
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#define CRYPTO_TR_CTL1 (*(volatile uint32_t *)(CRYPTO_BASE + 0x284UL))
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#define CRYPTO_TR_CTL2 (*(volatile uint32_t *)(CRYPTO_BASE + 0x288UL))
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#define CRYPTO_TR_CMD (*(volatile uint32_t *)(CRYPTO_BASE + 0x290UL))
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#define CRYPTO_TR_RESULT (*(volatile uint32_t *)(CRYPTO_BASE + 0x298UL))
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#define CRYPTO_TR_GARO_CTL (*(volatile uint32_t *)(CRYPTO_BASE + 0x2A0UL))
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#define CRYPTO_TR_FIRO_CTL (*(volatile uint32_t *)(CRYPTO_BASE + 0x2A4UL))
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#define CRYPTO_TR_MON_CTL (*(volatile uint32_t *)(CRYPTO_BASE + 0x2C0UL))
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#define CRYPTO_TR_MON_CMD (*(volatile uint32_t *)(CRYPTO_BASE + 0x2C8UL))
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#define CRYPTO_TR_MON_RC_CTL (*(volatile uint32_t *)(CRYPTO_BASE + 0x2D0UL))
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#define CRYPTO_TR_MON_AP_CTL (*(volatile uint32_t *)(CRYPTO_BASE + 0x2E0UL))
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#define CRYPTO_STATUS (*(volatile uint32_t *)(CRYPTO_BASE + 0x1004UL))
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#define CRYPTO_CTL_ENABLED (1UL << 31)
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#define CRYPTO_INTR_TR_INITIALIZED (1UL << 2)
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#define CRYPTO_INTR_TR_DATA_AVAILABLE (1UL << 3)
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#define CRYPTO_INTR_TR_AP_ERROR (1UL << 19)
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#define CRYPTO_INTR_TR_RC_ERROR (1UL << 20)
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#define CRYPTO_INTR_TR_ALL (CRYPTO_INTR_TR_INITIALIZED | \
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CRYPTO_INTR_TR_DATA_AVAILABLE | \
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CRYPTO_INTR_TR_AP_ERROR | \
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CRYPTO_INTR_TR_RC_ERROR)
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/* TR_CTL0: init delay 3, von Neumann correction, stop on either health test
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* failure. TR_CTL1: all six ring oscillators. */
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#define CRYPTO_TR_CTL0_DEFAULT ((3UL << 16) | (1UL << 24) | (1UL << 28) | \
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(1UL << 29))
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#define CRYPTO_TR_CTL1_ALL_RO (0x3FUL)
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#define CRYPTO_TR_POLY (0x04C11DB7UL)
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#define CRYPTO_TR_MON_BS_TR (2UL) /* monitor the TRNG bit stream */
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#define CRYPTO_TR_MON_START_AP_RC (0x3UL)
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#define CRYPTO_TR_RC_CUTOFF (255UL)
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#define CRYPTO_TR_AP_CTL ((65535UL << 16) | 65535UL)
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/* HAL services also used by the application. */
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void psoc_e8_peri_init(void);
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void psoc_e8_pin_setup(int port, int pin, uint32_t sel, uint32_t drive);
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int psoc_e8_pclk_setup(uint32_t gr, uint32_t idx, uint32_t div,
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uint32_t pclk_hz, uint32_t target_hz);
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void psoc_e8_delay_us(uint32_t us);
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uint64_t hal_get_timer_us(void);
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/* Console gateway for the Non-secure application. */
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#define PSOC_E8_NSC_UART_MAX (256U)
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void psoc_e8_nsc_uart_write(const char *buf, uint32_t len);
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#endif /* PSOC_E8_H_INCLUDED */
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