mirror of https://github.com/wolfSSL/wolfBoot.git
182 lines
7.6 KiB
C
182 lines
7.6 KiB
C
/* stm32g4.h
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*
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* Copyright (C) 2026 wolfSSL Inc.
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*
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* This file is part of wolfBoot.
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*
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* wolfBoot is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 3 of the License, or
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* (at your option) any later version.
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*
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* wolfBoot is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
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*/
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/* STM32G4 family (e.g. STM32G491RE on NUCLEO-G491RE).
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* Cortex-M4F, no TrustZone. Single-bank 512 KB flash, 2 KB pages.
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* Reference: RM0440. Shared register map for the wolfBoot HAL and
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* the test-app -- both pull in the same definitions so wire-up
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* doesn't drift between them. */
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#ifndef _STM32G4_H_
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#define _STM32G4_H_
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#include <stdint.h>
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/* Assembly helpers. The "memory" clobber tells the compiler not to
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* reorder loads/stores across the barrier; without it the asm only
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* orders hardware accesses, not the compiler's own scheduling. */
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#define DMB() __asm__ volatile ("dmb" ::: "memory")
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#define ISB() __asm__ volatile ("isb" ::: "memory")
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#define DSB() __asm__ volatile ("dsb" ::: "memory")
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/* -------- RCC (AHB1 + 0x1000 = 0x40021000) -------- RM0440 - 7.4 -------- */
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#define RCC_BASE (0x40021000)
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#define RCC_CR (*(volatile uint32_t *)(RCC_BASE + 0x00))
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#define RCC_CFGR (*(volatile uint32_t *)(RCC_BASE + 0x08))
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#define RCC_PLLCFGR (*(volatile uint32_t *)(RCC_BASE + 0x0C))
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#define RCC_CRRCR (*(volatile uint32_t *)(RCC_BASE + 0x98))
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#define RCC_CCIPR (*(volatile uint32_t *)(RCC_BASE + 0x88))
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#define RCC_AHB2ENR (*(volatile uint32_t *)(RCC_BASE + 0x4C))
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#define RCC_APB1ENR1 (*(volatile uint32_t *)(RCC_BASE + 0x58))
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#define RCC_APB1ENR2 (*(volatile uint32_t *)(RCC_BASE + 0x5C))
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#define RCC_APB2ENR (*(volatile uint32_t *)(RCC_BASE + 0x60))
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#define RCC_CR_PLLRDY (1 << 25)
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#define RCC_CR_PLLON (1 << 24)
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#define RCC_CR_HSIRDY (1 << 10)
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#define RCC_CR_HSION (1 << 8)
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#define RCC_CFGR_SW_HSI 0x1
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#define RCC_CFGR_SW_PLL 0x3
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#define RCC_CFGR_SW_MASK 0x3
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#define RCC_CFGR_SWS_SHIFT 2
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#define RCC_PLLCFGR_PLLREN (1 << 24)
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#define RCC_PLLCFGR_PLLR_SHIFT 25
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#define RCC_PLLCFGR_PLLN_SHIFT 8
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#define RCC_PLLCFGR_PLLM_SHIFT 4
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#define RCC_PLLCFGR_PLLSRC_HSI16 0x2
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#define RCC_CRRCR_HSI48ON (1 << 0)
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#define RCC_CRRCR_HSI48RDY (1 << 1)
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#define RCC_AHB2ENR_GPIOAEN (1 << 0)
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#define RCC_APB1ENR1_PWREN (1 << 28)
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#define RCC_APB1ENR2_LPUART1EN (1 << 0)
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#define RCC_APB2ENR_SYSCFGEN (1 << 0)
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/* -------- PWR (APB1 = 0x40007000) -------- RM0440 - 6.4 -------- */
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#define PWR_BASE (0x40007000)
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#define PWR_CR1 (*(volatile uint32_t *)(PWR_BASE + 0x00))
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#define PWR_CR5 (*(volatile uint32_t *)(PWR_BASE + 0x80))
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#define PWR_SR2 (*(volatile uint32_t *)(PWR_BASE + 0x14))
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#define PWR_CR1_VOS_SHIFT 9
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#define PWR_CR1_VOS_MASK (0x3 << PWR_CR1_VOS_SHIFT)
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#define PWR_CR1_VOS_RANGE1 (0x1 << PWR_CR1_VOS_SHIFT)
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#define PWR_CR5_R1MODE (1 << 0) /* 0 = Range 1 Boost */
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#define PWR_SR2_VOSF (1 << 10)
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/* -------- FLASH (AHB1 + 0x2000 = 0x40022000) -------- RM0440 - 3.7 -------- */
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#define FLASH_BASE (0x40022000)
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#define FLASH_ACR (*(volatile uint32_t *)(FLASH_BASE + 0x00))
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#define FLASH_KEY (*(volatile uint32_t *)(FLASH_BASE + 0x08))
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#define FLASH_SR (*(volatile uint32_t *)(FLASH_BASE + 0x10))
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#define FLASH_CR (*(volatile uint32_t *)(FLASH_BASE + 0x14))
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#define FLASHMEM_ADDRESS_SPACE (0x08000000)
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#define FLASH_PAGE_SIZE (0x800) /* 2KB */
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#define FLASH_ACR_LATENCY_MASK (0x7)
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#define FLASH_ACR_PRFTEN (1 << 8)
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#define FLASH_ACR_ICEN (1 << 9)
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#define FLASH_ACR_DCEN (1 << 10)
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#define FLASH_ACR_ICRST (1 << 11)
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#define FLASH_ACR_DCRST (1 << 12)
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#define FLASH_ACR_LATENCY_4WS (0x4)
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/* G4 has a single BSY at bit 16 (no BSY1/BSY2 like G0). */
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#define FLASH_SR_BSY (1 << 16)
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#define FLASH_SR_OPTVERR (1 << 15)
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#define FLASH_SR_RDERR (1 << 14)
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#define FLASH_SR_FASTERR (1 << 9)
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#define FLASH_SR_MISERR (1 << 8)
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#define FLASH_SR_PGSERR (1 << 7)
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#define FLASH_SR_SIZERR (1 << 6)
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#define FLASH_SR_PGAERR (1 << 5)
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#define FLASH_SR_WRPERR (1 << 4)
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#define FLASH_SR_PROGERR (1 << 3)
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#define FLASH_SR_OPERR (1 << 1)
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#define FLASH_SR_EOP (1 << 0)
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/* G491 (Cat 3) is single-bank: PNB is 8 bits at [10:3], no BKER. */
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#define FLASH_CR_LOCK (1UL << 31)
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#define FLASH_CR_STRT (1 << 16)
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#define FLASH_CR_PER (1 << 1)
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#define FLASH_CR_PG (1 << 0)
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#define FLASH_CR_PNB_SHIFT 3
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#define FLASH_CR_PNB_MASK 0xFF
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#define FLASH_KEY1 (0x45670123)
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#define FLASH_KEY2 (0xCDEF89AB)
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/* -------- GPIOA (AHB2 = 0x48000000) -------- RM0440 - 9.4 -------- */
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#define GPIOA_BASE (0x48000000)
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#define GPIOA_MODER (*(volatile uint32_t *)(GPIOA_BASE + 0x00))
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#define GPIOA_OTYPER (*(volatile uint32_t *)(GPIOA_BASE + 0x04))
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#define GPIOA_OSPEEDR (*(volatile uint32_t *)(GPIOA_BASE + 0x08))
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#define GPIOA_PUPDR (*(volatile uint32_t *)(GPIOA_BASE + 0x0C))
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#define GPIOA_ODR (*(volatile uint32_t *)(GPIOA_BASE + 0x14))
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#define GPIOA_BSRR (*(volatile uint32_t *)(GPIOA_BASE + 0x18))
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#define GPIOA_AFRL (*(volatile uint32_t *)(GPIOA_BASE + 0x20))
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#define GPIOA_AFRH (*(volatile uint32_t *)(GPIOA_BASE + 0x24))
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/* -------- LPUART1 (APB1 = 0x40008000) -------- RM0440 - 38.7 -------- */
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#define LPUART1_BASE (0x40008000)
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#define LPUART1_CR1 (*(volatile uint32_t *)(LPUART1_BASE + 0x00))
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#define LPUART1_BRR (*(volatile uint32_t *)(LPUART1_BASE + 0x0C))
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#define LPUART1_ISR (*(volatile uint32_t *)(LPUART1_BASE + 0x1C))
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#define LPUART1_TDR (*(volatile uint32_t *)(LPUART1_BASE + 0x28))
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#define USART_CR1_UE (1 << 0)
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#define USART_CR1_RE (1 << 2)
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#define USART_CR1_TE (1 << 3)
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#define USART_ISR_TEACK (1 << 21)
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#define USART_ISR_TXE (1 << 7)
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/* -------- SYSCLK / boot defaults -------- */
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#define STM32G4_SYSCLK_HZ (170000000UL)
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#define STM32G4_UART_BAUD (115200UL)
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/* LPUART_BRR = (256 * f_LPUART) / baud. PCLK1 = SYSCLK on default prescalers. */
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#define STM32G4_LPUART1_BRR(baud) \
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((uint32_t)(((uint64_t)256u * STM32G4_SYSCLK_HZ) / (baud)))
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/* -------- NUCLEO-G491RE board specifics -------- */
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#define NUCLEO_G491_LED_LD2_PIN (5) /* PA5 */
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#define NUCLEO_G491_UART_TX_PIN (2) /* PA2 - LPUART1_TX */
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#define NUCLEO_G491_UART_RX_PIN (3) /* PA3 - LPUART1_RX */
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#define NUCLEO_G491_UART_AF (12)
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/* Public helpers implemented in hal/stm32g4.c. Available to wolfBoot when
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* DEBUG_UART is set, and to the test-app at all times. */
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void uart_init(void);
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void uart_write(const char *buf, unsigned int len);
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#endif /* _STM32G4_H_ */
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