mirror of https://github.com/wolfSSL/wolfBoot.git
180 lines
5.8 KiB
C
180 lines
5.8 KiB
C
/* ahci.h
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*
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* Copyright (C) 2023 wolfSSL Inc.
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*
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* This file is part of wolfBoot.
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*
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* wolfBoot is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 3 of the License, or
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* (at your option) any later version.
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*
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* wolfBoot is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
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*/
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#ifndef AHCI_H
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#define AHCI_H
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#include <stdint.h>
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#define AHCI_CLASS_ID 0x01
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#define AHCI_SUBCLASS_ID 0x06
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#define AHCI_CLASS_CODE 0x0601
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#define AHCI_PROG_IF 0x01
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#define AHCI_ID_OFFSET 0x00
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#define AHCI_CMD_OFFSET 0x04
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#define AHCI_STS_OFFSET 0x06
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#define AHCI_AIDPBA_OFFSET 0x20
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#define AHCI_ABAR_OFFSET 0x24
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#define AHCI_MAX_PORTS 32
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#define AHCI_HBA_CAP(base) (base + 0x00)
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#define AHCI_HBA_GHC(base) (base + 0x04)
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#define AHCI_HBA_IS(base) (base + 0x08)
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#define AHCI_HBA_PI(base) (base + 0x0C)
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#define AHCI_HBA_VS(base) (base + 0x10)
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#define AHCI_HBA_CCC_CTL(base) (base + 0x14)
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#define AHCI_HBA_CCC_PORTS (base + 0x18)
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#define AHCI_HBA_EM_LOC (base + 0x1C)
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#define AHCI_HBA_EM_CTL (base + 0x20)
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#define AHCI_HBA_CAP2 (base + 0x24)
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#define AHCI_HBA_BOHC (base + 0x28)
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#define AHCI_PORT_START 0x100
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#define AHCI_PORT_SIZE 0x80
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#define AHCI_PORT_CLB_OFFSET 0x00
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#define AHCI_PORT_CLBH_OFFSET 0x04
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#define AHCI_PORT_FB_OFFSET 0x08
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#define AHCI_PORT_FBH_OFFSET 0x0C
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#define AHCI_PORT_IS_OFFSET 0x10
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#define AHCI_PORT_IE_OFFSET 0x14
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#define AHCI_PORT_CMD_OFFSET 0x18
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#define AHCI_PORT_TFD_OFFSET 0x20
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#define AHCI_PORT_SIG_OFFSET 0x24
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#define AHCI_PORT_SSTS_OFFSET 0x28
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#define AHCI_PORT_SCTL_OFFSET 0x2C
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#define AHCI_PORT_SERR_OFFSET 0x30
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#define AHCI_PORT_SACT_OFFSET 0x34
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#define AHCI_PORT_CI_OFFSET 0x38
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#define AHCI_PORT_REG_START(base, port) \
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((base + AHCI_PORT_START + (port * AHCI_PORT_SIZE)))
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#define AHCI_PxSSTS(base, port) \
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(base + AHCI_PORT_START + \
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(port * AHCI_PORT_SIZE) + AHCI_PORT_SSTS_OFFSET)
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#define AHCI_PxFB(base, port) (base + AHCI_PORT_START + \
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(port * AHCI_PORT_SIZE) + AHCI_PORT_FB_OFFSET)
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#define AHCI_PxFBH(base, port) (base + AHCI_PORT_START + \
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(port * AHCI_PORT_SIZE) + AHCI_PORT_FBH_OFFSET)
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#define AHCI_PxCLB(base, port) (base + AHCI_PORT_START + \
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(port * AHCI_PORT_SIZE) + AHCI_PORT_CLB_OFFSET)
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#define AHCI_PxCLBH(base, port) (base + AHCI_PORT_START + \
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(port * AHCI_PORT_SIZE) + AHCI_PORT_CLBH_OFFSET)
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#define AHCI_PxCMD(base, port) (base + AHCI_PORT_START + \
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(port * AHCI_PORT_SIZE) + AHCI_PORT_CMD_OFFSET)
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#define AHCI_PxIE(base, port) (base + AHCI_PORT_START + \
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(port * AHCI_PORT_SIZE) + AHCI_PORT_IE_OFFSET)
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#define AHCI_PxIS(base, port) (base + AHCI_PORT_START + \
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(port * AHCI_PORT_SIZE) + AHCI_PORT_IS_OFFSET)
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#define AHCI_PxSCTL(base, port) (base + AHCI_PORT_START + \
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(port * AHCI_PORT_SIZE) + AHCI_PORT_SCTL_OFFSET)
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#define AHCI_PxSERR(base, port) (base + AHCI_PORT_START + \
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(port * AHCI_PORT_SIZE) + AHCI_PORT_SERR_OFFSET)
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#define AHCI_PxTFD(base, port) (base + AHCI_PORT_START + \
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(port * AHCI_PORT_SIZE) + AHCI_PORT_TFD_OFFSET)
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#define AHCI_PxSIG(base, port) \
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(base + AHCI_PORT_START + \
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(port * AHCI_PORT_SIZE) + AHCI_PORT_SIG_OFFSET)
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#define AHCI_PxSACT(base, port) (base + AHCI_PORT_START + \
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(port * AHCI_PORT_SIZE) + AHCI_PORT_SACT_OFFSET)
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#define AHCI_PxCI(base, port) (base + AHCI_PORT_START + \
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(port * AHCI_PORT_SIZE) + AHCI_PORT_CI_OFFSET)
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#define HBA_GHC_AE (1 << 31) /* AHCI ENABLE */
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#define HBA_GHC_HR (1 << 0) /* HARD RESET */
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#define HBA_GHC_IE (1 << 1) /* INT ENABLE */
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#define AHCI_CAP_SSS (1 << 27) /* Staggered spin-up mode supported */
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#define AHCI_CAP_SAM (1 << 18)
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#define AHCI_PORT_CMD_CPD (1 << 20) /* Cold-presence detection */
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#define AHCI_PORT_CMD_POD (1 << 2) /* Power On Device */
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#define AHCI_PORT_CMD_SUD (1 << 1) /* Spin-up device */
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#define AHCI_PORT_CMD_FR (1 << 14) /* FR */
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#define AHCI_PORT_CMD_FRE (1 << 4) /* FIS receive enabled */
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#define AHCI_PORT_CMD_START (1 << 0) /* Start processing the command list */
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#define AHCI_PORT_CMD_CR (1 << 15) /* CR */
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#define AHCI_PORT_CMD_ALPE (1 << 26) /* Aggressive link power management enable */
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#define AHCI_PORT_CMD_ICC_ACTIVE (0x1 << 28)
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#define AHCI_PORT_CMD_ICC_MASK (0xf << 28)
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#define AHCI_SSTS_DET_MASK 0xf
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#define AHCI_PORT_SSTS_DET 0x01
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#define AHCI_PORT_SSTS_DET_PCE 0x03
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#define AHCI_PORT_TFD_BSY (1 << 7)
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#define AHCI_PORT_TFD_DRQ (1 << 3)
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#define AHCI_PORT_TFD_ERR (1 << 0)
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#define AHCI_PORT_SIG_SATA 0x00000101
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#define AHCI_PORT_SIG_ATAPI 0xEB140101
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#define AHCI_PORT_SIG_SEMB 0xC33C0101
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#define AHCI_PORT_SIG_PM 0x96690101
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#define AHCI_PORT_IS_TFES (1 << 30)
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struct ahci_received_fis {
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/* 0x00 */
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uint8_t ahci_dma_setup_fis[0x1C];
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uint8_t _res0[0x04];
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/* 0x20 */
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uint8_t ahci_pio_setup_fis[0x14];
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uint8_t _res1[0x0C];
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/* 0x40 */
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uint8_t ahci_d2h_reg_fis[0x14];
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uint8_t _res2[0x04];
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/* 0x58 */
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uint64_t ahci_set_device_bits_fis;
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/* 0x60 */
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uint8_t ahci_unk_fis[0x40];
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/* 0xA0 */
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uint8_t _res_f[0x60];
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};
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uint32_t ahci_enable(uint32_t bus, uint32_t dev, uint32_t fun);
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void sata_enable(uint32_t base);
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void sata_disable(uint32_t base);
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int sata_unlock_disk(int drv, int freeze);
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#endif /* AHCI_H */
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