mirror of https://github.com/wolfSSL/wolfBoot.git
91 lines
2.8 KiB
Plaintext
91 lines
2.8 KiB
Plaintext
/* tc3tc_app.ld */
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/* Example application linker script using bare-metal startup */
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OUTPUT_FORMAT("elf32-tricore")
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OUTPUT_ARCH(tricore)
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/* This is defined global in tc3tc_crt.S */
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ENTRY(tc3tc_crt_entry)
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/* Include TC3mem linker script */
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INCLUDE tc3_mem.ld
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/* Reallocate regions */
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INCLUDE tc3_layout.ld
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MEMORY {
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TEST_APP (rx) : ORIGIN = @WOLFBOOT_TEST_APP_ADDRESS@, LENGTH = @WOLFBOOT_TEST_APP_SIZE@
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}
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ASSERT(ORIGIN(TEST_APP) >= ORIGIN(app_flash), "test app not located within app_flash")
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ASSERT((ORIGIN(TEST_APP) + LENGTH(TEST_APP)) <= (ORIGIN(app_flash) + LENGTH(app_flash)), "test app memory region overflows app_flash")
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/* BMHD sections */
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REGION_ALIAS("BMHD_ORIG", ucb_bmhd_orig)
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REGION_ALIAS("BMHD_COPY", ucb_bmhd_copy)
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/* CRT0 Boot Code Start */
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REGION_ALIAS("BOOT", TEST_APP)
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/* Shared code and data */
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REGION_ALIAS("CODE", TEST_APP)
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REGION_ALIAS("RODATA", TEST_APP)
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REGION_ALIAS("DATA", dlmu_cpu0)
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REGION_ALIAS("RAM_CODE", pspr_cpu0)
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/* CPU0: Output sections to memory region mapping */
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REGION_ALIAS("CODE_CPU0_", TEST_APP)
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REGION_ALIAS("RODATA_CPU0_", TEST_APP)
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REGION_ALIAS("RAMCODE_CPU0_", pspr_cpu0)
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REGION_ALIAS("DATA_DSPR_CPU0_", dspr_cpu0)
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REGION_ALIAS("DATA_DLMU_CPU0_", dlmu_cpu0)
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/* CPU1: Output sections to memory region mapping */
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REGION_ALIAS("CODE_CPU1_", TEST_APP)
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REGION_ALIAS("RODATA_CPU1_", TEST_APP)
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REGION_ALIAS("RAMCODE_CPU1_", pspr_cpu1)
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REGION_ALIAS("DATA_DSPR_CPU1_", dspr_cpu1)
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REGION_ALIAS("DATA_DLMU_CPU1_", dlmu_cpu1)
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/* CPU2: Output sections to memory region mapping */
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REGION_ALIAS("CODE_CPU2_", TEST_APP)
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REGION_ALIAS("RODATA_CPU2_", TEST_APP)
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REGION_ALIAS("RAMCODE_CPU2_", pspr_cpu2)
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REGION_ALIAS("DATA_DSPR_CPU2_", dspr_cpu2)
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REGION_ALIAS("DATA_DLMU_CPU2_", dlmu_cpu2)
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/* CPU3: Output sections to memory region mapping */
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REGION_ALIAS("CODE_CPU3_", TEST_APP)
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REGION_ALIAS("RODATA_CPU3_", TEST_APP)
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REGION_ALIAS("RAMCODE_CPU3_", pspr_cpu3)
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REGION_ALIAS("DATA_DSPR_CPU3_", dspr_cpu3)
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REGION_ALIAS("DATA_DLMU_CPU3_", dlmu_cpu3)
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/* CPU4: Output sections to memory region mapping */
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REGION_ALIAS("CODE_CPU4_", TEST_APP)
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REGION_ALIAS("RODATA_CPU4_", TEST_APP)
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REGION_ALIAS("RAMCODE_CPU4_", pspr_cpu4)
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REGION_ALIAS("DATA_DSPR_CPU4_", dspr_cpu4)
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REGION_ALIAS("DATA_DLMU_CPU4_", dlmu_cpu4)
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/* CPU5: Output sections to memory region mapping */
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REGION_ALIAS("CODE_CPU5_", TEST_APP)
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REGION_ALIAS("RODATA_CPU5_", TEST_APP)
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REGION_ALIAS("RAMCODE_CPU5_", pspr_cpu5)
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REGION_ALIAS("DATA_DSPR_CPU5_", dspr_cpu5)
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REGION_ALIAS("DATA_DLMU_CPU5_", dlmu_cpu5)
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/* Local CSA per CPU. 256 max number, 64 byte entries */
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CSA_SIZE = 256 * 64;
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/* Local stack per CPU. */
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STACK_SIZE = 4K;
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/* Shared heap. Only use in a pinch for compatibility with stdlib */
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__HEAP_SIZE = DEFINED (__HEAP_SIZE) ? __HEAP_SIZE : 4K;
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/* Pickup the common sections */
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INCLUDE tc3tc_sections.ld
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