mirror of https://github.com/wolfSSL/wolfBoot.git
217 lines
6.0 KiB
C
217 lines
6.0 KiB
C
/* app_stm32l0.c
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*
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* Test bare-metal boot-led-on application
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*
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* Copyright (C) 2021 wolfSSL Inc.
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*
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* This file is part of wolfBoot.
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*
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* wolfBoot is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 3 of the License, or
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* (at your option) any later version.
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*
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* wolfBoot is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
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*/
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#include <stdlib.h>
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#include <stdint.h>
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#include <string.h>
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#include "led.h"
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#include "wolfboot/wolfboot.h"
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#ifdef SPI_FLASH
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#include "spi_flash.h"
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#endif
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#ifdef PLATFORM_stm32l0
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#define UART2 (0x40004400)
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#define UART2_CR1 (*(volatile uint32_t *)(UART2 + 0x00))
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#define UART2_CR2 (*(volatile uint32_t *)(UART2 + 0x04))
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#define UART2_CR3 (*(volatile uint32_t *)(UART2 + 0x08))
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#define UART2_BRR (*(volatile uint32_t *)(UART2 + 0x0c))
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#define UART2_ISR (*(volatile uint32_t *)(UART2 + 0x1c))
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#define UART2_ICR (*(volatile uint32_t *)(UART2 + 0x20))
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#define UART2_RDR (*(volatile uint32_t *)(UART2 + 0x24))
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#define UART2_TDR (*(volatile uint32_t *)(UART2 + 0x28))
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#define UART_CR1_UART_ENABLE (1 << 0)
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#define UART_CR1_SYMBOL_LEN (1 << 12)
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#define UART_CR1_PARITY_ENABLED (1 << 10)
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#define UART_CR1_OVER8 (1 << 15)
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#define UART_CR1_PARITY_ODD (1 << 9)
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#define UART_CR1_TX_ENABLE (1 << 3)
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#define UART_CR1_RX_ENABLE (1 << 2)
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#define UART_CR2_STOPBITS (3 << 12)
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#define UART_CR2_LINEN (1 << 14)
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#define UART_CR2_CLKEN (1 << 11)
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#define UART_CR3_HDSEL (1 << 3)
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#define UART_CR3_SCEN (1 << 5)
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#define UART_CR3_IREN (1 << 1)
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#define UART_ISR_TX_EMPTY (1 << 7)
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#define UART_ISR_RX_NOTEMPTY (1 << 5)
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#define RCC_IOPENR (*(volatile uint32_t *)(0x4002102C))
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#define APB1_CLOCK_ER (*(volatile uint32_t *)(0x40021038))
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#define IOPAEN (1 << 0)
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#define IOPCEN (1 << 2)
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#define UART2_APB1_CLOCK_ER_VAL (1 << 17)
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#define GPIOA_BASE 0x50000000
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#define GPIOA_MODE (*(volatile uint32_t *)(GPIOA_BASE + 0x00))
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#define GPIOA_OTYPE (*(volatile uint32_t *)(GPIOA_BASE + 0x04))
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#define GPIOA_OSPD (*(volatile uint32_t *)(GPIOA_BASE + 0x08))
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#define GPIOA_PUPD (*(volatile uint32_t *)(GPIOA_BASE + 0x0c))
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#define GPIOA_ODR (*(volatile uint32_t *)(GPIOA_BASE + 0x14))
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#define GPIOA_BSRR (*(volatile uint32_t *)(GPIOA_BASE + 0x18))
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#define GPIOA_AFL (*(volatile uint32_t *)(GPIOA_BASE + 0x20))
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#define GPIOA_AFH (*(volatile uint32_t *)(GPIOA_BASE + 0x24))
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#define GPIO_MODE_AF (2)
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#define UART2_PIN_AF 4
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#define UART2_RX_PIN 2
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#define UART2_TX_PIN 3
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#ifndef CPU_FREQ
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#define CPU_FREQ (24000000)
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#endif
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static void uart2_pins_setup(void)
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{
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uint32_t reg;
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RCC_IOPENR |= IOPAEN;
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/* Set mode = AF */
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reg = GPIOA_MODE & ~ (0x03 << (UART2_RX_PIN * 2));
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GPIOA_MODE = reg | (2 << (UART2_RX_PIN * 2));
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reg = GPIOA_MODE & ~ (0x03 << (UART2_TX_PIN * 2));
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GPIOA_MODE = reg | (2 << (UART2_TX_PIN * 2));
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/* Alternate function: use low pins (2 and 3) */
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reg = GPIOA_AFL & ~(0xf << (UART2_TX_PIN * 4));
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GPIOA_AFL = reg | (UART2_PIN_AF << (UART2_TX_PIN * 4));
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reg = GPIOA_AFL & ~(0xf << (UART2_RX_PIN * 4));
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GPIOA_AFL = reg | (UART2_PIN_AF << (UART2_RX_PIN * 4));
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}
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int uart_setup(uint32_t bitrate)
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{
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uint32_t reg;
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/* Enable pins and configure for AF */
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uart2_pins_setup();
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/* Turn on the device */
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APB1_CLOCK_ER |= UART2_APB1_CLOCK_ER_VAL;
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/* Enable 16-bit oversampling */
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UART2_CR1 &= (~UART_CR1_OVER8);
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/* Configure clock */
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UART2_BRR |= (uint16_t)(CPU_FREQ / bitrate);
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/* Configure data bits to 8 */
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UART2_CR1 &= ~UART_CR1_SYMBOL_LEN;
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/* Disable parity */
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UART2_CR1 &= ~(UART_CR1_PARITY_ENABLED | UART_CR1_PARITY_ODD);
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/* Set stop bits */
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UART2_CR2 = UART2_CR2 & ~UART_CR2_STOPBITS;
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/* Clear flags for async mode */
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UART2_CR2 &= ~(UART_CR2_LINEN | UART_CR2_CLKEN);
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UART2_CR3 &= ~(UART_CR3_SCEN | UART_CR3_HDSEL | UART_CR3_IREN);
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/* Configure for RX+TX, turn on. */
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UART2_CR1 |= UART_CR1_TX_ENABLE | UART_CR1_RX_ENABLE | UART_CR1_UART_ENABLE;
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return 0;
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}
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int uart_write(const uint8_t c)
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{
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volatile uint32_t reg;
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do {
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reg = UART2_ISR;
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} while ((reg & UART_ISR_TX_EMPTY) == 0);
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UART2_TDR = c;
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return 1;
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}
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int uart_read(uint8_t *c, int len)
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{
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volatile uint32_t reg;
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int i = 0;
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reg = UART2_ISR;
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if (reg & UART_ISR_RX_NOTEMPTY) {
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*c = (uint8_t)UART2_RDR;
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return 1;
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}
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return 0;
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}
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void uart_print(const char *s)
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{
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int i = 0;
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while (s[i]) {
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uart_write(s[i++]);
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}
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}
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/* Matches all keys:
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* - chacha (32 + 12)
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* - aes128 (16 + 16)
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* - aes256 (32 + 16)
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*/
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/* Longest key possible: AES256 (32 key + 16 IV = 48) */
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char enc_key[] = "0123456789abcdef0123456789abcdef"
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"0123456789abcdef";
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void main(void)
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{
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uint32_t version;
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volatile uint32_t i, j;
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uart_setup(115200);
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uart_print("STM32L0 Test Application\n\r");
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#ifdef SPI_FLASH
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spi_flash_probe();
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#endif
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version = wolfBoot_current_firmware_version();
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if ((version % 2) == 1) {
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uint32_t sz;
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#if EXT_ENCRYPTED
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wolfBoot_set_encrypt_key((uint8_t *)enc_key,(uint8_t *)(enc_key + 32));
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#endif
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wolfBoot_update_trigger();
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} else {
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wolfBoot_success();
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}
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for (i = 0; i < version; i++) {
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boot_led_on();
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for (j = 0; j < 200000; j++)
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;
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boot_led_off();
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for (j = 0; j < 200000; j++)
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;
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}
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boot_led_on();
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/* Wait for reboot */
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while(1)
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;
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}
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#endif /** PLATFROM_stm32l0 **/
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