mirror of https://github.com/wolfSSL/wolfBoot.git
115 lines
3.8 KiB
C
115 lines
3.8 KiB
C
/* app_nxp_p1021.c
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*
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* Copyright (C) 2022 wolfSSL Inc.
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*
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* This file is part of wolfBoot.
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*
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* wolfBoot is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* wolfBoot is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
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*/
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#include <stdint.h>
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/* P1021 */
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#define CCSRBAR (0xFF700000)
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#define SYS_CLK (400000000)
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/* P1021 PC16552D Dual UART */
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#define BAUD_RATE 115200
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#define UART_SEL 0 /* select UART 0 or 1 */
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#define UART_BASE(n) (CCSRBAR + 0x4500 + (n * 0x100))
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#define UART_RBR(n) *((volatile uint8_t*)(UART_BASE(n) + 0)) /* receiver buffer register */
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#define UART_THR(n) *((volatile uint8_t*)(UART_BASE(n) + 0)) /* transmitter holding register */
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#define UART_IER(n) *((volatile uint8_t*)(UART_BASE(n) + 1)) /* interrupt enable register */
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#define UART_IIR(n) *((volatile uint8_t*)(UART_BASE(n) + 2)) /* interrupt ID register */
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#define UART_FCR(n) *((volatile uint8_t*)(UART_BASE(n) + 2)) /* FIFO control register */
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#define UART_LCR(n) *((volatile uint8_t*)(UART_BASE(n) + 3)) /* line control register */
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#define UART_MCR(n) *((volatile uint8_t*)(UART_BASE(n) + 4)) /* modem control register */
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#define UART_LSR(n) *((volatile uint8_t*)(UART_BASE(n) + 5)) /* line status register */
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/* enabled when UART_LCR_DLAB set */
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#define UART_DLB(n) *((volatile uint8_t*)(UART_BASE(n) + 0)) /* divisor least significant byte register */
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#define UART_DMB(n) *((volatile uint8_t*)(UART_BASE(n) + 1)) /* divisor most significant byte register */
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#define UART_FCR_TFR (0x04) /* Transmitter FIFO reset */
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#define UART_FCR_RFR (0x02) /* Receiver FIFO reset */
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#define UART_FCR_FEN (0x01) /* FIFO enable */
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#define UART_LCR_DLAB (0x80) /* Divisor latch access bit */
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#define UART_LCR_WLS (0x03) /* Word length select: 8-bits */
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#define UART_LSR_TEMT (0x40) /* Transmitter empty */
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#define UART_LSR_THRE (0x20) /* Transmitter holding register empty */
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static void uart_init(void)
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{
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/* calc divisor for UART
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* example config values:
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* clock_div, baud, base_clk 163 115200 300000000
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* +0.5 to round up
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*/
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uint32_t div = (((SYS_CLK / 2.0) / (16 * BAUD_RATE)) + 0.5);
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while (!(UART_LSR(UART_SEL) & UART_LSR_TEMT))
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;
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/* set ier, fcr, mcr */
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UART_IER(UART_SEL) = 0;
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UART_FCR(UART_SEL) = (UART_FCR_TFR | UART_FCR_RFR | UART_FCR_FEN);
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/* enable baud rate access (DLAB=1) - divisor latch access bit*/
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UART_LCR(UART_SEL) = (UART_LCR_DLAB | UART_LCR_WLS);
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/* set divisor */
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UART_DLB(UART_SEL) = (div & 0xff);
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UART_DMB(UART_SEL) = ((div>>8) & 0xff);
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/* disable rate access (DLAB=0) */
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UART_LCR(UART_SEL) = (UART_LCR_WLS);
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}
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static void uart_write(const char* buf, uint32_t sz)
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{
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uint32_t pos = 0;
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while (sz-- > 0) {
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while (!(UART_LSR(UART_SEL) & UART_LSR_THRE))
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;
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UART_THR(UART_SEL) = buf[pos++];
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}
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}
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static const char* hex_lut = "0123456789abcdef";
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void main(void)
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{
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int i = 0;
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int j = 0;
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int k = 0;
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char snum[8];
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uart_write("Test App\n", 9);
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/* Wait for reboot */
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while(1) {
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for (j=0; j<1000000; j++)
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;
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i++;
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uart_write("\r\n0x", 4);
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for (k=0; k<8; k++) {
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snum[7 - k] = hex_lut[(i >> 4*k) & 0xf];
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}
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uart_write(snum, 8);
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}
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}
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