mirror of https://github.com/wolfSSL/wolfBoot.git
168 lines
6.6 KiB
Plaintext
168 lines
6.6 KiB
Plaintext
# NXP T2080 wolfBoot Configuration
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# Default board: T2080 RDB (66.66 MHz oscillator, DDR3L SODIMM)
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#
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# Board selection:
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# Default (no define): T2080 RDB (66.66 MHz oscillator, DDR3L SODIMM)
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# BOARD_NAII_68PPC2: NAII 68PPC2 (100 MHz oscillator, 8 GB DDR3)
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# BOARD_CW_VPX3152: CW VPX3-152 (66.667 MHz oscillator, 4 GB DDR3L)
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#
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# For NAII 68PPC2, uncomment the line below (addresses are the same as RDB):
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#CFLAGS_EXTRA+=-DBOARD_NAII_68PPC2
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#
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# For CW VPX3-152 (256 MB NOR flash at 0xF0000000), uncomment the BOARD
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# define below AND the entire address-override block at the bottom of this
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# file. That block includes OS_64BIT=1, which is REQUIRED to boot a 64-bit
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# RTOS (VxWorks 7 / Green Hills INTEGRITY-178 tuMP) -- it gates the e6500 SMP
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# spin-table + DDR-LAW handoff in hal/nxp_t2080.c; without it the loader runs
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# but the OS hangs silently right after "do_boot: jumping".
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#CFLAGS_EXTRA+=-DBOARD_CW_VPX3152
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ARCH=PPC
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TARGET=nxp_t2080
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SIGN?=ECC384
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HASH?=SHA384
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IMAGE_HEADER_SIZE?=512
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DEBUG?=0
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DEBUG_SYMBOLS?=1
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DEBUG_UART?=1
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VTOR?=1
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CORTEX_M0?=0
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NO_ASM?=0
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EXT_FLASH?=0
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SPI_FLASH?=0
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NO_XIP?=0
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UART_FLASH?=0
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ALLOW_DOWNGRADE?=0
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NVM_FLASH_WRITEONCE?=0
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WOLFBOOT_VERSION?=0
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NO_MPU?=0
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SPMATH?=1
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SPMATHALL?=0
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RAM_CODE?=1
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DUALBANK_SWAP?=0
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WOLFTPM?=0
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OPTIMIZATION_LEVEL?=1
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ELF?=1
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DEBUG_ELF=0
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# -----------------------------------------------------------------------------
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# Default addresses: T2080 RDB / NAII 68PPC2 (128 MB NOR flash @ 0xE8000000)
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# -----------------------------------------------------------------------------
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# NOR Base Address: wolfBoot at top of flash
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ARCH_FLASH_OFFSET?=0xEFFE0000
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# CPC SRAM address (must match L2SRAM_ADDR in nxp_ppc.h)
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L2SRAM_ADDR?=0xF8F00000
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# Flash Sector Size
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WOLFBOOT_SECTOR_SIZE?=0x10000
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# wolfBoot start address
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WOLFBOOT_ORIGIN?=0xEFFE0000
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# wolfBoot partition size (custom)
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BOOTLOADER_PARTITION_SIZE=0x20000
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# The region [0xEFF00000, 0xEFFE0000) below wolfBoot is reserved for the FMan
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# microcode (FMAN_FW_ADDR=0xEFF00000, the U-Boot-standard slot). The partitions
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# below sit under it so a BOOT-partition erase/update never touches the ucode.
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# Application Partition Size
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WOLFBOOT_PARTITION_SIZE?=0x100000
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# Location in Flash for Application Partition (top = 0xEFF00000, below the ucode)
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WOLFBOOT_PARTITION_BOOT_ADDRESS?=0xEFE00000
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# Load Partition to RAM Address
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WOLFBOOT_LOAD_ADDRESS?=0x19000
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# Location in Flash for Update Partition
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WOLFBOOT_PARTITION_UPDATE_ADDRESS?=0xEFD00000
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# Location of temporary sector used during updates
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WOLFBOOT_PARTITION_SWAP_ADDRESS?=0xEFCF0000
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# DTS (Device Tree)
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WOLFBOOT_DTS_BOOT_ADDRESS?=0xE8040000
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WOLFBOOT_DTS_UPDATE_ADDRESS?=0xE8050000
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# DTS Load to RAM Address
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WOLFBOOT_LOAD_DTS_ADDRESS?=0x200000
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# -----------------------------------------------------------------------------
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# CW VPX3-152 overrides (256 MB NOR flash @ 0xF0000000, 4 GB DDR3L)
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# Uncomment ALL lines below when building for VPX3-152, AND uncomment
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# CFLAGS_EXTRA+=-DBOARD_CW_VPX3152 at the top of this file. This is the
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# known-good config used to boot VxWorks 7 and Green Hills INTEGRITY-178
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# tuMP (Ada Scheduler) on this board.
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# -----------------------------------------------------------------------------
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#ARCH_FLASH_OFFSET=0xFFFE0000
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#L2SRAM_ADDR=0xEE900000
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#WOLFBOOT_ORIGIN=0xFFFE0000
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# 8 MB partitions -- full RTOS images do not fit the 1 MB RDB default.
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#WOLFBOOT_PARTITION_SIZE=0x800000
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#WOLFBOOT_PARTITION_BOOT_ADDRESS=0xFF000000
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#WOLFBOOT_PARTITION_UPDATE_ADDRESS=0xFE800000
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#WOLFBOOT_PARTITION_SWAP_ADDRESS=0xFE7F0000
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#WOLFBOOT_DTS_BOOT_ADDRESS=0xF0040000
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#WOLFBOOT_DTS_UPDATE_ADDRESS=0xF0050000
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#WOLFBOOT_LOAD_DTS_ADDRESS=0x03FE6000
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# REQUIRED for 64-bit RTOS boot (VxWorks 7 / INTEGRITY-178 tuMP). Gates the
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# e6500 SMP spin-table (0x7FEE41C0) + DDR-LAW-slot-17 handoff in
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# hal/nxp_t2080.c. Without it the loader runs but the OS hangs silently after
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# "do_boot: jumping" (it is NOT a missing device tree -- tuMP has no FDT
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# parser; this build option is what was actually missing).
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#OS_64BIT=1
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# ELF staging buffer. wolfBoot copies the signed image here, then elf_load
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# scatters PT_LOAD segments IN PLACE to their vaddrs. It MUST sit ABOVE the
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# ELF's vaddr span (a VxWorks/INTEGRITY ELF spans ~0x2000-0x75F000) or the
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# in-place loader's collide-guard silently drops the segment overlapping the
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# program-header table -- the OS then executes unloaded memory and traps
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# early. The 0x19000 default overlaps the span; 0x900000 is above it, below
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# the 16 MB DDR stack, inside the 32 MB cache-inhibit window. Raw uImage
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# kernels override this via ih_load (unaffected).
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#WOLFBOOT_LOAD_ADDRESS=0x900000
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# Optional: verbose pre-OS register/TLB/LAW dump for handoff debugging.
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#CFLAGS_EXTRA+=-DWOLFBOOT_PPC_PRE_OS_DUMP
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# Flash erase/write/read test at update partition address
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#TEST_FLASH?=1
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# wolfCrypt Test and Benchmark (requires larger partition size)
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#WOLFCRYPT_TEST?=1
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#WOLFCRYPT_BENCHMARK?=1
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# -----------------------------------------------------------------------------
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# wolfIP network test in the test-app (optional)
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# -----------------------------------------------------------------------------
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# Compiles wolfIP + the NXP QorIQ FMan ethernet port (mEMAC/MDIO/SGMII,
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# FM1@DTSEC1) into the test-app and runs a board-side network test. Build the
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# app FLAT and 32-bit (ELF=0, OS_64BIT=0) at a low load address (the elf32 load
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# path and 64-bit RTOS handoff are unused). wolfIP objects are built -fno-plt
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# -D_FORTIFY_SOURCE=0 (no PLT/GOT runtime fixup). Point WOLFBOOT_LIB_WOLFIP at
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# a wolfIP checkout (or add it as lib/wolfip).
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#ENABLE_WOLFIP=1
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#WOLFBOOT_LIB_WOLFIP=../lib/wolfip
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# Build FLAT + 32-bit at a low load address (as above; siblings t1040/t1024 too):
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#ELF=0
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#OS_64BIT=0
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#WOLFBOOT_LOAD_ADDRESS=0x100000
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# Test mode (neither flag = acquire a DHCP lease and stop):
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# WOLFBOOT_TEST_TFTP=1 RRQ a file from a host tftpd, report size+checksum
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# (set CFLAGS_EXTRA TFTP_EXPECT_SIZE/TFTP_EXPECT_SUM to verify)
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# WOLFIP_SPEED_TEST=1 TCP throughput server on port 9 (drive with nc/dd/pv)
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#WOLFBOOT_TEST_TFTP=1
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#WOLFIP_SPEED_TEST=1
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#
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# Per-board wolfIP ethernet wiring (defaults above are CW VPX3-152 / RDB =
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# FM1@DTSEC1, SGMII, PHY probed at addr 0x2). Override per the board device
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# tree if the wired port differs:
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#
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# NAII 68PPC2 (hardware-verified): PRIME port is FM1@DTSEC3 = RGMII, Marvell
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# PHY at MDIO addr 0 (68ppc2.dts ethernet@e4000: "rgmii-id", ethernet-phy@0
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# reg <0>). The MDIO scan would otherwise grab DTSEC4's PHY at addr 1, so set
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# the address explicitly:
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#CFLAGS_EXTRA+=-DNXP_FMAN_MEMAC_IDX=3
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#CFLAGS_EXTRA+=-DNXP_FMAN_IF_SGMII=0
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#CFLAGS_EXTRA+=-DNXP_FMAN_PHY_ADDR=0
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#
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# NAII NOR is dual-bank with only the top 128KB boot sector common to both
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# banks; flash the ucode/app with the boot-bank select in its runtime state.
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