mirror of https://github.com/wolfSSL/wolfBoot.git
173 lines
6.6 KiB
Plaintext
173 lines
6.6 KiB
Plaintext
# PolarFire SoC MPFS250T M-Mode (Machine Mode) with LPDDR4 + SD card
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#
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# Standalone wolfBoot replacing HSS:
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# 1. eNVM (0x20220100) -> L2_SCRATCH (0x0A000000) - wolfBoot starts
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# 2. M-mode init: PLLs, DDR controller, LPDDR4 training (Video Kit)
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# 3. Load signed FIT from SD to DDR staging (0x82000000); after verify,
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# kernel -> 0x80200000 (FIT "load"), DTB -> 0x8A000000
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# 4. Verify ECC384/SHA384 signature
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# 5. Drop to S-mode and jump to kernel
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#
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# Flash via mpfsBootmodeProgrammer (bootmode 1):
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# java -jar mpfsBootmodeProgrammer.jar --bootmode 1 --die MPFS250T \
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# --package FCG1152 --workdir $PWD wolfboot.elf
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ARCH?=RISCV64
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TARGET?=mpfs250
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SIGN?=ECC384
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HASH?=SHA384
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IMAGE_HEADER_SIZE=512
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WOLFBOOT_VERSION?=1
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ARMORED?=0
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DEBUG?=0
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DEBUG_SYMBOLS?=1
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DEBUG_UART?=1
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VTOR?=1
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EXT_FLASH?=0
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SPI_FLASH?=0
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NO_XIP?=1
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NVM_FLASH_WRITEONCE?=0
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UART_FLASH?=0
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V?=0
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NO_MPU?=1
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RAM_CODE?=0
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SPMATH?=0
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SPMATHALL?=1
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DUALBANK_SWAP?=0
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PKA?=0
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ENCRYPT=0
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WOLFTPM?=0
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ELF?=1
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#DEBUG_ELF?=1
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OPTIMIZATION_LEVEL=1
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# M-Mode configuration: runs on E51 from L2 SRAM
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RISCV_MMODE?=1
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# Stack size per hart (L2 SRAM constraints). Single source of truth: this
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# Makefile var feeds both the startup asm (-DSTACK_SIZE_PER_HART) and the
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# linker script (@STACK_SIZE_PER_HART@ in mpfs250-m.ld).
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STACK_SIZE_PER_HART=4096
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# E51 core lacks RISC-V crypto extensions (Zknh), use portable C
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# RISC-V SHA256/384/512 assembly (wolfcrypt port/riscv) enabled by default.
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# Verified on the MPFS250 E51 (rv64imac); requires wolfSSL with the RISC-V
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# unaligned-access fix (PR #10530, present in the lib/wolfssl submodule).
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# The E51 handles unaligned access so the default (faster) asm path is used;
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# add -DWOLFSSL_RISCV_ASM_NO_UNALIGNED for RISC-V cores that trap on it.
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NO_ASM?=0
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# Enable LPDDR4 init in hal_init() by pointing at the Libero/HSS-generated
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# fpga_design_config directory for this board. The directory must contain
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# fpga_design_config.h and its sub-headers (memory_map/, ddr/, clocks/, ...).
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# Typical sources:
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# - HSS Video Kit build:
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# <hss>/build/boards/mpfs-video-kit/fpga_design_config
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# - Libero MSS Configurator export for the design.
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# The -I path is added and -DMPFS_DDR_INIT is set automatically when this is
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# non-empty (see arch.mk). Override on the command line for one-off builds:
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# make LIBERO_FPGA_CONFIG_DIR=/path/to/fpga_design_config
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LIBERO_FPGA_CONFIG_DIR?=
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# Boot Linux: drop to S-mode after wolfBoot verifies kernel
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CFLAGS_EXTRA+=-DWOLFBOOT_MMODE_SMODE_BOOT
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# SD card storage for kernel image (no QSPI flash)
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DISK_SDCARD?=1
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DISK_EMMC?=0
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# wolfBoot in L2 SRAM (256KB available)
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WOLFBOOT_ORIGIN?=0x0A000000
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# 4KB sector size (SD card flow is partition-based, not flash-erase-based)
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WOLFBOOT_SECTOR_SIZE?=0x1000
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# Scratch address where the signed FIT image is staged before signature
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# verification + FIT parse. Placed early in DDR (32 MB into 2 GB) so we
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# stay within the fully-trained region near 0x80000000 - the LPDDR4 TIP
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# completes BCLK_SCLK only (train_stat=0x1) on this Video Kit and higher
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# DDR addresses (e.g. 0x8E000000) have shown intermittent write
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# corruption during long disk loads.
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# After the FIT is parsed:
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# kernel is copied to 0x80200000 (FIT-internal "load")
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# DTB is copied to WOLFBOOT_LOAD_DTS_ADDRESS (0x8A000000)
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# Layout:
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# 0x80200000 - 0x814FFFFF : kernel (~19 MB after parse)
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# 0x82000000 - 0x832FFFFF : FIT scratch (~19 MB - overwritten on next boot)
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# 0x8A000000 - 0x8A004FFF : DTB
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WOLFBOOT_LOAD_ADDRESS?=0x82000000
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# DTB load address in DDR
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WOLFBOOT_LOAD_DTS_ADDRESS?=0x8A000000
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# Bound the UNAUTHENTICATED FIT image length before it drives the disk read
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# into the DDR staging region (required by src/update_disk.c). The FIT is
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# staged at WOLFBOOT_LOAD_ADDRESS (0x82000000); the DTB load region begins
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# 128 MB above at 0x8A000000, so cap the staged image at 128 MB so an
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# attacker-declared fw_size cannot overrun the DTB region before the
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# signature check runs.
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WOLFBOOT_RAMBOOT_MAX_SIZE=0x08000000
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# Use update_disk loader (partition A/B numbering instead of flash addresses).
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# BOOT_PART_A / BOOT_PART_B are 0-indexed GPT entry numbers. GPT partitions
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# in our SD card layout (see tools/scripts/program-sdcard.sh):
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# index 0 (parted "boot" 1 MiB - 33 MiB) -> active boot FIT
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# index 1 (parted "update" 33 MiB - 65 MiB) -> inactive/update slot
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# index 2 (parted "rootfs" 65 MiB - end) -> Linux rootfs
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WOLFBOOT_NO_PARTITIONS=1
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CFLAGS_EXTRA+=-DBOOT_PART_A=0
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CFLAGS_EXTRA+=-DBOOT_PART_B=1
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# Speed up disk partition read (512KB chunks - max DMA size)
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CFLAGS_EXTRA+=-DDISK_BLOCK_SIZE=0x80000
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# Disable SDMA on the Cadence SD4HC. SDMA hangs silently at first
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# multi-block read on the Video Kit (Cadence boundary-cross bug).
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# Use PIO single-block reads instead.
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CFLAGS_EXTRA+=-DSDHCI_SDMA_DISABLED
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# Force single-block (CMD17) reads. Multi-block PIO suffers a BRR
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# race on Arasan/Cadence-family controllers; single-block avoids it.
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CFLAGS_EXTRA+=-DSDHCI_FORCE_SINGLE_BLOCK_READ
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# Disk-load via PDMA staging. On this board, CPU AXI writes to DDR
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# (cached or non-cached) do NOT reliably land at the address that
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# subsequent cached reads will fetch from -- empirical alias probe
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# showed CPU writes via the 0xC0000000 non-cached window are silently
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# dropped, and cached PIO writes appear to allocate L2 lines that are
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# never written back to DDR before the integrity-check read.
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#
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# Workaround: SDHCI PIO into a small L2 Scratch staging buffer, then
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# mpfs_pdma_memcpy() copies the block into DDR via the PDMA master.
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# PDMA-via-non-cached is the only AXI write path verified to land in
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# DDR (the same path used by mpfs_clear_bootup_cache_ways pre-fill).
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CFLAGS_EXTRA+=-DSDHCI_BLOCK_VIA_PDMA
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# Video Kit routes the SD slot's Card Detect (CD#) signal through the FPGA
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# fabric rather than MSSIO, so the SDHCI controller's hardware CI/CDPL
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# detection always reads 'no card' in M-mode (no fabric configuration).
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# Force the SD bring-up code to assume a card is present.
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CFLAGS_EXTRA+=-DSDHCI_FORCE_CARD_DETECT
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# Optional encryption (kernel signed+encrypted with AES-256)
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#CUSTOM_ENCRYPT_KEY=1
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#ENCRYPT=1
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#ENCRYPT_WITH_AES256=1
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#OBJS_EXTRA=src/my_custom_encrypt_key.o
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# Used by test-application/ELF wrapper
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WOLFBOOT_PARTITION_BOOT_ADDRESS=0x80200000
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WOLFBOOT_PARTITION_SIZE=0x4000000
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# Debug options (useful for initial M-mode + DDR bring-up)
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CFLAGS_EXTRA+=-DDEBUG_BOOT
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#CFLAGS_EXTRA+=-DDEBUG_SDHCI
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#CFLAGS_EXTRA+=-DDEBUG_DISK
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#CFLAGS_EXTRA+=-DDISK_TEST
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# Verbose register-level DDR tracing (development aid). Historically the
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# DBG_DDR printf delays appeared load-bearing for TIP training; that was
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# resolved by the auto-init-disable training reorder and the WRCALIB
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# all-4-lane accept gate with retry, so this is safe to leave disabled.
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#CFLAGS_EXTRA+=-DDEBUG_DDR
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