mirror of https://github.com/wolfSSL/wolfBoot.git
124 lines
6.0 KiB
Plaintext
124 lines
6.0 KiB
Plaintext
ARCH?=ARM
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TARGET?=zynq7000
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SIGN?=ECC256
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HASH?=SHA256
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# Cortex-A9 Zynq-7000 SD-card boot variant. Uses the generic SDHCI driver
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# (src/sdhci.c) with HAL hooks in hal/zynq7000.c that translate between the
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# driver's Cadence SD4HC register layout and the Arasan SDHCI v2.0 standard
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# layout used by the Zynq-7000 controller (same IP family as ZynqMP's v3.0,
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# just an older revision; the translation is reused from hal/zynq.c).
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#
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# wolfBoot replaces U-Boot in the Z7 boot flow (BootROM -> FSBL -> wolfBoot
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# -> kernel/app, no U-Boot stage). This single config supports both
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# bare-metal and Linux payloads from SD card -- see the MMU/ELF block below.
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DEBUG?=0
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DEBUG_UART?=1
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V?=0
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SPMATH?=1
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# SD card boot - swaps update_ram.o for update_disk.o + GPT/disk support.
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DISK_SDCARD=1
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NO_XIP=1
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# One config for both bare-metal and Linux payloads. do_boot in
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# src/boot_arm32.c always emits the ARM Linux boot ABI (r0=0, r1=~0,
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# r2=DTB_phys, r3=0) when MMU=1; bare-metal apps simply ignore r0..r3,
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# so a single register-handoff covers both payload types.
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# MMU=1 -> pulls in src/fdt.o for FDT-aware paths in update_disk.c.
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# wolfBoot does NOT manage page tables; it inherits FSBL's
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# flat 1:1 DDR mapping.
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# ELF=1 -> wolfBoot understands ELF inputs (e.g. vmlinux) and loads
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# only their LOAD segments. Flat binaries (zImage, bare-metal
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# .bin) fall through to raw-binary boot.
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# For Linux from SD use tools/scripts/zynq7000/prepare_linux.sh APPENDED=1
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# (DTB concatenated to zImage and signed as one image). update_disk.c does
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# not read a separate PART_DTS_BOOT partition; the appended-DTB path is
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# what carries the device tree to the kernel via CONFIG_ARM_APPENDED_DTB.
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MMU=1
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ELF=1
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# Stage payload at low DDR (clear of wolfBoot at 0x04000000-0x040FFFFF).
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WOLFBOOT_LOAD_ADDRESS=0x10000000
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# Cap on the RAM load region. The disk image payload is copied to
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# WOLFBOOT_LOAD_ADDRESS before its header is authenticated, so the on-disk
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# fw_size must be bounded first (see src/update_disk.c). This is an example
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# config not tied to a real board, so the cap is just a sane sanity bound:
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# 700 MB is far larger than any realistic FIT image yet keeps the load well
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# clear of a 32-bit wrap back onto wolfBoot at 0x04000000. Size it to your
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# board's DDR (top_of_DDR - WOLFBOOT_LOAD_ADDRESS) for a real target.
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WOLFBOOT_RAMBOOT_MAX_SIZE=0x2BC00000
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# DTB load address (Linux only, used by update_disk.c when a FIT image
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# carries a DTB). Ignored for bare-metal and for the appended-DTB Linux
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# flow. 16 MB clear of WOLFBOOT_LOAD_ADDRESS.
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WOLFBOOT_LOAD_DTS_ADDRESS=0x11000000
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# MBR partition layout on the SD card. Pure MBR (no GPT) - the Zynq-7000
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# BootROM (UG821 ch.6.3) only accepts MBR with the first partition as
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# FAT32 and the Active flag set. wolfBoot's src/disk.c falls back to MBR
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# parsing when no protective-GPT entry is present.
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# MBR p1 (wolfBoot idx 0): FAT32-LBA Active - holds BOOT.BIN for BootROM.
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# MBR p2 (wolfBoot idx 1): Linux raw (0x83) - signed boot image.
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# MBR p3 (wolfBoot idx 2): Linux raw (0x83) - signed update image.
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# tools/scripts/zynq7000/prepare_sdcard.sh lays this out; BOOT_PART_A/B tell
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# update_disk.c which MBR entries (0-indexed) to use for boot/update.
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CFLAGS_EXTRA+=-DBOOT_PART_A=1 -DBOOT_PART_B=2
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# Arasan SDHCI v2.0 on Zynq-7000 is 3.3V-only, no UHS-I. The generic
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# driver tries to push the card to UHS-I SDR25 / 50 MHz / High Speed mode
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# which is invalid for our v2.0 + 3.3V combo and causes DTOE on the first
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# data transfer (MBR read). Cap the post-init clock at SD default-speed
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# 25 MHz; the HSE bit is also masked in hal/zynq7000.c sdhci_reg_write so
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# the controller stays in single-edge timing the card matches.
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# Cap the post-init SDHCI clock at 6 MHz. The Arasan SDHCI v2.0 on
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# Zynq-7000 has a clock-dependent state-cleanup issue: at 12 MHz multi-
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# block reads (CMD18) work, but a single-block read (CMD17) issued
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# immediately after a CMD18+CMD12 sequence times out (DTOE) on the first
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# data block. At 24 MHz even the very first CMD17 fails. 6 MHz / 4-bit
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# bus is plenty fast for boot-time loading (~3 MB/s) and is well below
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# the v2.0 quirk threshold; raise this if a future fix in src/sdhci.c
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# adds an explicit DAT-line reset between transfers.
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CFLAGS_EXTRA+=-DSDHCI_CLK_50MHZ=6000 -DSDHCI_CLK_25MHZ=6000
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# update_disk.c reads images in DISK_BLOCK_SIZE chunks. Default 512 B = one
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# disk_read = one CMD17 per 512 B, which makes a multi-MB Linux load issue
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# thousands of CMDs and stall the card with per-CMD overhead. Bump to
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# 512 KB so each disk_read pulls 1024 blocks via one CMD18 SDMA (matches
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# ZynqMP). Verified on ZC702 with a 4.76 MB appended-DTB zImage: 9 CMD18s
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# complete in well under a second. The default 4 KB SDMA buffer boundary
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# is left in place -- overriding it to 512 KB stalled SDMA on Arasan v2.0.
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CFLAGS_EXTRA+=-DDISK_BLOCK_SIZE=0x80000
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# Uncomment for verbose SDHCI driver logging when bringing up new boards
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# or debugging timing issues.
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#CFLAGS_EXTRA+=-DDEBUG_SDHCI
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# Image-header partition addresses are unused for disk boot (kept for the
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# Makefile sanity checks). update_disk.c finds images by GPT entry, not by
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# memory address.
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WOLFBOOT_PARTITION_BOOT_ADDRESS=0x00100000
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WOLFBOOT_PARTITION_UPDATE_ADDRESS=0x00700000
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WOLFBOOT_PARTITION_SWAP_ADDRESS=0x00D00000
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WOLFBOOT_PARTITION_SIZE=0x00600000
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# Sector size of WOLFBOOT_PARTITION (not the SD physical sector, which is
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# always 512 B). Used as the smallest erase/copy unit for the BOOT/UPDATE
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# partitions; must be > IMAGE_HEADER_SIZE.
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WOLFBOOT_SECTOR_SIZE=0x1000
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IMAGE_HEADER_SIZE=1024
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# Required by image.c when MMU=1 is set, even though update_disk.c never
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# opens PART_DTS_BOOT/PART_DTS_UPDATE on this target (the disk boot path
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# selects images by partition index -- BOOT_PART_A / BOOT_PART_B above --
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# not by memory-mapped address, and the DTB travels with the kernel via
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# appended-DTB or FIT). src/disk.c parses either GPT or MBR (it falls
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# back to MBR when there is no protective-GPT entry), so the layout
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# choice is orthogonal to this knob. Set to dummy addresses to satisfy
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# the build.
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WOLFBOOT_DTS_BOOT_ADDRESS=0x0
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WOLFBOOT_DTS_UPDATE_ADDRESS=0x0
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CROSS_COMPILE=arm-none-eabi-
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